Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * R7S9210 Clock Pulse Generator / Module Standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Based on r8a7795-cpg-mssr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2018 Chris Brandt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CPG_FRQCR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static u8 cpg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Internal Clock ratio table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	unsigned int g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned int p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	/* p0 is always 32 */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) } ratio_tab[5] = {	/* I,  G,  B, P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 			{  2,  4,  8, 16},	/* FRQCR = 0x012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			{  4,  4,  8, 16},	/* FRQCR = 0x112 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			{  8,  4,  8, 16},	/* FRQCR = 0x212 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			{ 16,  8, 16, 16},	/* FRQCR = 0x322 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			{ 16, 16, 32, 32},	/* FRQCR = 0x333 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) enum rz_clk_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	CLK_TYPE_RZA_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) enum clk_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/* Core Clock Outputs exported to DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	LAST_DT_CORE_CLK = R7S9210_CLK_P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* External Input Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	CLK_EXTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	CLK_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	MOD_CLK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct cpg_core_clk r7s9210_early_core_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* External Clock Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DEF_INPUT("extal",     CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	DEF_BASE(".pll",       CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* Core Clock Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DEF_FIXED("p1c",    R7S9210_CLK_P1C,   CLK_PLL,         16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	DEF_MOD_STB("ostm2",	 34,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	DEF_MOD_STB("ostm1",	 35,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	DEF_MOD_STB("ostm0",	 36,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static struct cpg_core_clk r7s9210_core_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* Core Clock Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	DEF_FIXED("i",      R7S9210_CLK_I,     CLK_PLL,          2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	DEF_FIXED("g",      R7S9210_CLK_G,     CLK_PLL,          4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	DEF_FIXED("b",      R7S9210_CLK_B,     CLK_PLL,          8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DEF_FIXED("p1",     R7S9210_CLK_P1,    CLK_PLL,         16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	DEF_FIXED("p0",     R7S9210_CLK_P0,    CLK_PLL,         32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	DEF_MOD_STB("scif4",	 43,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	DEF_MOD_STB("scif3",	 44,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DEF_MOD_STB("scif2",	 45,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	DEF_MOD_STB("scif1",	 46,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	DEF_MOD_STB("scif0",	 47,	R7S9210_CLK_P1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	DEF_MOD_STB("usb1",	 60,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	DEF_MOD_STB("usb0",	 61,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	DEF_MOD_STB("ether1",	 64,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	DEF_MOD_STB("ether0",	 65,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	DEF_MOD_STB("spibsc",	 83,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	DEF_MOD_STB("i2c3",	 84,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	DEF_MOD_STB("i2c2",	 85,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	DEF_MOD_STB("i2c1",	 86,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	DEF_MOD_STB("i2c0",	 87,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	DEF_MOD_STB("spi2",	 95,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	DEF_MOD_STB("spi1",	 96,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	DEF_MOD_STB("spi0",	 97,	R7S9210_CLK_P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	DEF_MOD_STB("sdhi11",	100,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	DEF_MOD_STB("sdhi10",	101,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	DEF_MOD_STB("sdhi01",	102,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	DEF_MOD_STB("sdhi00",	103,	R7S9210_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* The clock dividers in the table vary based on DT and register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void __init r7s9210_update_clk_table(struct clk *extal_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					    void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u16 frqcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* If EXTAL is above 12MHz, then we know it is Mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (clk_get_rate(extal_clk) > 12000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		cpg_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	frqcr = readl(base + CPG_FRQCR) & 0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (frqcr == 0x012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	else if (frqcr == 0x112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	else if (frqcr == 0x212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		index = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	else if (frqcr == 0x322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		index = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	else if (frqcr == 0x333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		index = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		BUG_ON(1);	/* Illegal FRQCR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		switch (r7s9210_core_clks[i].id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		case R7S9210_CLK_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			r7s9210_core_clks[i].div = ratio_tab[index].i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		case R7S9210_CLK_G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			r7s9210_core_clks[i].div = ratio_tab[index].g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		case R7S9210_CLK_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			r7s9210_core_clks[i].div = ratio_tab[index].b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		case R7S9210_CLK_P1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		case R7S9210_CLK_P1C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			r7s9210_core_clks[i].div = ratio_tab[index].p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		case R7S9210_CLK_P0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			r7s9210_core_clks[i].div = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct clk * __init rza2_cpg_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct clk **clks, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct raw_notifier_head *notifiers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned int mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	parent = clks[core->parent];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	switch (core->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	case CLK_MAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case CLK_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (cpg_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			mult = 44;	/* Divider 1 is 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			mult = 88;	/* Divider 1 is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (core->id == CLK_MAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		r7s9210_update_clk_table(parent, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return clk_register_fixed_factor(NULL, core->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					 __clk_get_name(parent), 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* Early Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.early_core_clks = r7s9210_early_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.early_mod_clks = r7s9210_early_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.core_clks = r7s9210_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.num_core_clks = ARRAY_SIZE(r7s9210_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.last_dt_core_clk = LAST_DT_CORE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.num_total_core_clks = MOD_CLK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.mod_clks = r7s9210_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.cpg_clk_register = rza2_cpg_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* RZ/A2 has Standby Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.reg_layout = CLK_REG_LAYOUT_RZ_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		      r7s9210_cpg_mssr_early_init);