^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sh73a0 Core CPG Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct sh73a0_cpg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clk_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CPG_FRQCRA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPG_FRQCRB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CPG_SD0CKCR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPG_SD1CKCR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPG_SD2CKCR 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPG_PLLECR 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPG_PLL0CR 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPG_PLL1CR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPG_PLL2CR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CPG_PLL3CR 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CPG_CKSCR 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CPG_DSI0PHYCR 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPG_DSI1PHYCR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_ENABLE_ON_INIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct div4_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct div4_clk div4_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "zg", "pll0", CPG_FRQCRA, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { "m3", "pll1", CPG_FRQCRA, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { "b", "pll1", CPG_FRQCRA, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { "m1", "pll1", CPG_FRQCRA, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { "m2", "pll1", CPG_FRQCRA, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "zx", "pll1", CPG_FRQCRB, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { "hp", "pll1", CPG_FRQCRB, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { NULL, NULL, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct clk_div_table div4_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 12, 7 }, { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct clk_div_table z_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* ZSEL == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* ZSEL == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct clk_div_table *table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int shift, reg, width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const char *parent_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!strcmp(name, "main")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* extal1, extal1_div2, extal2, extal2_div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) div = (parent_idx & 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } else if (!strncmp(name, "pll", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *enable_reg = cpg->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 enable_bit = name[3] - '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) parent_name = "main";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) switch (enable_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enable_reg += CPG_PLL0CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enable_reg += CPG_PLL1CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enable_reg += CPG_PLL2CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enable_reg += CPG_PLL3CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* handle CFG bit for PLL1 and PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (enable_bit == 1 || enable_bit == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (readl(enable_reg) & BIT(20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mult *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 phy_no = name[3] - '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __iomem *dsi_reg = cpg->reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) parent_name = phy_no ? "dsi1pck" : "dsi0pck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mult = __raw_readl(dsi_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!(mult & 0x8000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mult = (mult & 0x3f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else if (!strcmp(name, "z")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) parent_name = "pll0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) table = z_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg = CPG_FRQCRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) shift = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) width = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const struct div4_clk *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for (c = div4_clks; c->name; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!strcmp(name, c->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) parent_name = c->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) table = div4_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg = c->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) shift = c->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!c->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return clk_register_fixed_factor(NULL, name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return clk_register_divider_table(NULL, name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cpg->reg + reg, shift, width, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) table, &cpg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void __init sh73a0_cpg_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sh73a0_cpg *cpg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) num_clks = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (num_clks < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pr_err("%s: failed to count clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (cpg == NULL || clks == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* We're leaking memory on purpose, there's no point in cleaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * up as the system won't boot anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_lock_init(&cpg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cpg->data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cpg->data.clk_num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) cpg->reg = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (WARN_ON(cpg->reg == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Set SDHI clocks to a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel(0x108, cpg->reg + CPG_SD0CKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writel(0x108, cpg->reg + CPG_SD1CKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(0x108, cpg->reg + CPG_SD2CKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = 0; i < num_clks; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) of_property_read_string_index(np, "clock-output-names", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk = sh73a0_cpg_register_clock(np, cpg, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __func__, np, name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cpg->data.clks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sh73a0_cpg_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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