^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RZ/A1 Core CPG Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Ideas On Board SPRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct rz_cpg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clk_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CPG_FRQCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CPG_FRQCR2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PPR0 0xFCFE3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PIBC0 0xFCFE7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u16 __init rz_cpg_read_mode_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *ppr0, *pibc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ppr0 = ioremap(PPR0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pibc0 = ioremap(PIBC0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) BUG_ON(!ppr0 || !pibc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) iowrite16(4, pibc0); /* enable input buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) modes = ioread16(ppr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) iounmap(ppr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) iounmap(pibc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (strcmp(name, "pll") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mult = cpg_mode ? (32 / 4) : 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!cpg->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return ERR_PTR(-ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * and the constraint that always g <= i. To get the rz platform started,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * let them run at fixed current speed and implement the details later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (strcmp(name, "i") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) else if (strcmp(name, "g") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val = readl(cpg->reg + CPG_FRQCR2) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mult = frqcr_tab[val];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void __init rz_cpg_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct rz_cpg *cpg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) num_clks = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) BUG_ON(!cpg || !clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cpg->data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cpg->data.clk_num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) cpg->reg = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (i = 0; i < num_clks; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) of_property_read_string_index(np, "clock-output-names", i, &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk = rz_cpg_register_clock(np, cpg, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __func__, np, name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cpg->data.clks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cpg_mstp_add_clk_domain(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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