^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a7779 Core CPG Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013, 2014 Horms Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contact: Simon Horman <horms@verge.net.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/soc/renesas/rcar-rst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/r8a7779-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct r8a7779_cpg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * CPG Clock Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * MD1 = 1 MD1 = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * (PLLA = 1500) (PLLA = 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * (MHz) (MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *------------------------------------------------+--------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * clkz 1000 (2/3) 800 (1/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * clkzs 250 (1/6) 200 (1/8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * clki 750 (1/2) 800 (1/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * clks 250 (1/6) 200 (1/8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * clks1 125 (1/12) 100 (1/16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * clks3 187.5 (1/8) 200 (1/8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * clks4 93.7 (1/16) 100 (1/16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * clkp 62.5 (1/24) 50 (1/32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * clkg 62.5 (1/24) 66.6 (1/24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * clkb, CLKOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * (MD2 = 1) 41.6 (1/36) 50 (1/32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cpg_clk_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int z_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int z_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int zs_and_s_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int s1_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int b_and_out_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 1, 2, 8, 16, 32, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 2, 3, 6, 12, 24, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 1, 2, 8, 16, 32, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 2, 3, 6, 12, 24, 36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * MD PLLA Ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 12 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 0 0 x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 0 1 x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 1 0 x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * 1 1 x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const struct cpg_clk_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int plla_mult, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const char *parent_name = "plla";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!strcmp(name, "plla")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mult = plla_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } else if (!strcmp(name, "z")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) div = config->z_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mult = config->z_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) div = config->zs_and_s_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } else if (!strcmp(name, "s1")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) div = config->s1_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else if (!strcmp(name, "p")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) div = config->p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else if (!strcmp(name, "b") || !strcmp(name, "out")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) div = config->b_and_out_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void __init r8a7779_cpg_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct cpg_clk_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct r8a7779_cpg *cpg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int i, plla_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (rcar_rst_read_mode_pins(&mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) num_clks = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (num_clks < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_err("%s: failed to count clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (cpg == NULL || clks == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* We're leaking memory on purpose, there's no point in cleaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * up as the system won't boot anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) spin_lock_init(&cpg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cpg->data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cpg->data.clk_num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (i = 0; i < num_clks; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) of_property_read_string_index(np, "clock-output-names", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk = r8a7779_cpg_register_clock(np, cpg, config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) plla_mult, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __func__, np, name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cpg->data.clks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cpg_mstp_add_clk_domain(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) r8a7779_cpg_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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