^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a7778 Core CPG Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/soc/renesas/rcar-rst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct r8a7778_cpg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct clk_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* PLL multipliers per bits 11, 12, and 18 of MODEMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long plla_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long pllb_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) } r8a7778_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [0] = { 21, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [1] = { 24, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [2] = { 28, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [3] = { 32, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [5] = { 24, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [6] = { 28, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [7] = { 32, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Clock dividers per bits 1 and 2 of MODEMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int div[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } r8a7778_divs[6] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { "b", { 12, 12, 16, 18 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "out", { 12, 12, 16, 18 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { "p", { 16, 12, 16, 12 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { "s", { 4, 3, 4, 3 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { "s1", { 8, 6, 8, 6 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static u32 cpg_mode_rates __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static u32 cpg_mode_divs __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!strcmp(name, "plla")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return clk_register_fixed_factor(NULL, "plla",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) of_clk_get_parent_name(np, 0), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) r8a7778_rates[cpg_mode_rates].plla_mult, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } else if (!strcmp(name, "pllb")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return clk_register_fixed_factor(NULL, "pllb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) of_clk_get_parent_name(np, 0), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!strcmp(name, r8a7778_divs[i].name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return clk_register_fixed_factor(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) r8a7778_divs[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "plla", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) r8a7778_divs[i].div[cpg_mode_divs]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void __init r8a7778_cpg_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct r8a7778_cpg *cpg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (rcar_rst_read_mode_pins(&mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BUG_ON(!(mode & BIT(19)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (!!(mode & BIT(12)) << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) (!!(mode & BIT(11)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (!!(mode & BIT(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) num_clks = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (num_clks < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_err("%s: failed to count clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (cpg == NULL || clks == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* We're leaking memory on purpose, there's no point in cleaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * up as the system won't boot anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spin_lock_init(&cpg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) cpg->data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cpg->data.clk_num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cpg->reg = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (WARN_ON(cpg->reg == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) for (i = 0; i < num_clks; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) of_property_read_string_index(np, "clock-output-names", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk = r8a7778_cpg_register_clock(np, cpg, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __func__, np, name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cpg->data.clks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cpg_mstp_add_clk_domain(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) r8a7778_cpg_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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