Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * r8a73a4 Core CPG Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014  Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct r8a73a4_cpg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct clk_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CPG_CKSCR	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CPG_FRQCRA	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CPG_FRQCRB	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CPG_FRQCRC	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CPG_PLL0CR	0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CPG_PLL1CR	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CPG_PLL2CR	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CPG_PLL2HCR	0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CPG_PLL2SCR	0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_ENABLE_ON_INIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct div4_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static struct div4_clk div4_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ "i",	CPG_FRQCRA, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ "m3", CPG_FRQCRA, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ "b",	CPG_FRQCRA,  8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ "m1", CPG_FRQCRA,  4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ "m2", CPG_FRQCRA,  0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ "zx", CPG_FRQCRB, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ "zs", CPG_FRQCRB,  8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ "hp", CPG_FRQCRB,  4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ NULL, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static const struct clk_div_table div4_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ 12, 10 }, { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static struct clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			     const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	const struct clk_div_table *table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int shift, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (!strcmp(name, "main")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		u32 ckscr = readl(cpg->reg + CPG_CKSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		switch ((ckscr >> 28) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		case 0:	/* extal1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		case 1:	/* extal1 / 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		case 2: /* extal2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			parent_name = of_clk_get_parent_name(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		case 3: /* extal2 / 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			parent_name = of_clk_get_parent_name(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} else if (!strcmp(name, "pll0")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		/* PLL0/1 are configurable multiplier clocks. Register them as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		 * fixed factor clocks for now as there's no generic multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 * clock implementation and we currently have no need to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * the multiplier value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		u32 value = readl(cpg->reg + CPG_PLL0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		parent_name = "main";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		mult = ((value >> 24) & 0x7f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (value & BIT(20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	} else if (!strcmp(name, "pll1")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		u32 value = readl(cpg->reg + CPG_PLL1CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		parent_name = "main";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		/* XXX: enable bit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		mult = ((value >> 24) & 0x7f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		if (value & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	} else if (!strncmp(name, "pll2", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		u32 value, cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		switch (name[4]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			cr = CPG_PLL2CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		case 's':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			cr = CPG_PLL2SCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		case 'h':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			cr = CPG_PLL2HCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		value = readl(cpg->reg + cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		switch ((value >> 5) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			parent_name = "main";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			parent_name = "extal2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			parent_name = "extal2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			parent_name = "main";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			parent_name = "extal2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			pr_warn("%s: unexpected parent of %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		/* XXX: enable bit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		mult = ((value >> 24) & 0x7f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	} else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		u32 shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		parent_name = "pll0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (name[1] == '2') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		div *= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		struct div4_clk *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		for (c = div4_clks; c->name; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			if (!strcmp(name, c->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (!c->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		parent_name = "pll1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		table = div4_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		reg = c->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		shift = c->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return clk_register_fixed_factor(NULL, name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 						 mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return clk_register_divider_table(NULL, name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 						  cpg->reg + reg, shift, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 						  table, &cpg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct r8a73a4_cpg *cpg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	num_clks = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (num_clks < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		pr_err("%s: failed to count clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (cpg == NULL || clks == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		/* We're leaking memory on purpose, there's no point in cleaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		 * up as the system won't boot anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	spin_lock_init(&cpg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	cpg->data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	cpg->data.clk_num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	cpg->reg = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (WARN_ON(cpg->reg == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	for (i = 0; i < num_clks; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		of_property_read_string_index(np, "clock-output-names", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					      &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		clk = r8a73a4_cpg_register_clock(np, cpg, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			       __func__, np, name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			cpg->data.clks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	       r8a73a4_cpg_clocks_init);