Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * R-Car MSTP clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Ideas On Board SPRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pm_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * MSTP clocks. We can't use standard gate clocks as we need to poll on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * status register when enabling the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MSTP_MAX_CLOCKS		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * struct mstp_clock_group - MSTP gating clocks group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @data: clock specifier translation for clocks in this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @smstpcr: module stop control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @mstpsr: module stop status register (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @lock: protects writes to SMSTPCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @width_8bit: registers are 8-bit, not 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @clks: clocks in this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct mstp_clock_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct clk_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void __iomem *smstpcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void __iomem *mstpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	bool width_8bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct clk *clks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * struct mstp_clock - MSTP gating clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @bit_index: control bit index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @group: MSTP clocks group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct mstp_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 bit_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct mstp_clock_group *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 				u32 __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return group->width_8bit ? readb(reg) : readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				  u32 __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	group->width_8bit ? writeb(val, reg) : writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct mstp_clock *clock = to_mstp_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct mstp_clock_group *group = clock->group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 bitmask = BIT(clock->bit_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	spin_lock_irqsave(&group->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	value = cpg_mstp_read(group, group->smstpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		value &= ~bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		value |= bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	cpg_mstp_write(group, value, group->smstpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (!group->mstpsr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/* dummy read to ensure write has completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		cpg_mstp_read(group, group->smstpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		barrier_data(group->smstpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_unlock_irqrestore(&group->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (!enable || !group->mstpsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	for (i = 1000; i > 0; --i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		pr_err("%s: failed to enable %p[%d]\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		       group->smstpcr, clock->bit_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int cpg_mstp_clock_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return cpg_mstp_clock_endisable(hw, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void cpg_mstp_clock_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	cpg_mstp_clock_endisable(hw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct mstp_clock *clock = to_mstp_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct mstp_clock_group *group = clock->group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (group->mstpsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		value = cpg_mstp_read(group, group->mstpsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		value = cpg_mstp_read(group, group->smstpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return !(value & BIT(clock->bit_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct clk_ops cpg_mstp_clock_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.enable = cpg_mstp_clock_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.disable = cpg_mstp_clock_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.is_enabled = cpg_mstp_clock_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct clk * __init cpg_mstp_clock_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	const char *parent_name, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct mstp_clock_group *group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct mstp_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	init.ops = &cpg_mstp_clock_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* INTC-SYS is the module clock of the GIC, and must not be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (!strcmp(name, "intc-sys")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		init.flags |= CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clock->bit_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	clock->group = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	clock->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	clk = clk_register(NULL, &clock->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		kfree(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void __init cpg_mstp_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct mstp_clock_group *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	const char *idxname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (!group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	clks = group->clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	spin_lock_init(&group->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	group->data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	group->smstpcr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	group->mstpsr = of_iomap(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (group->smstpcr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		pr_err("%s: failed to remap SMSTPCR\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		kfree(group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		group->width_8bit = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		clks[i] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (of_find_property(np, "clock-indices", &i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		idxname = "clock-indices";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		idxname = "renesas,clock-indices";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		u32 clkidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		/* Skip clocks with no name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		ret = of_property_read_string_index(np, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 						    i, &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (ret < 0 || strlen(name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		parent_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		ret = of_property_read_u32_index(np, idxname, i, &clkidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (parent_name == NULL || ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (clkidx >= MSTP_MAX_CLOCKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			pr_err("%s: invalid clock %pOFn %s index %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			       __func__, np, name, clkidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 						       clkidx, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (!IS_ERR(clks[clkidx])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			group->data.clk_num = max(group->data.clk_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 						  clkidx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			 * Register a clkdev to let board code retrieve the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			 * clock by name and register aliases for non-DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			 * devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			 * FIXME: Remove this when all devices that require a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			 * clock will be instantiated from DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			clk_register_clkdev(clks[clkidx], name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			       __func__, np, name, PTR_ERR(clks[clkidx]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 					   &clkspec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (of_device_is_compatible(clkspec.np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 					    "renesas,cpg-mstp-clocks"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		/* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		if (of_node_name_eq(clkspec.np, "zb_clk"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		of_node_put(clkspec.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	clk = of_clk_get_from_provider(&clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	of_node_put(clkspec.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	error = pm_clk_create(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		goto fail_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	error = pm_clk_add_clk(dev, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		goto fail_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) fail_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	pm_clk_destroy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) fail_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (!pm_clk_no_clocks(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		pm_clk_destroy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void __init cpg_mstp_add_clk_domain(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct generic_pm_domain *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	u32 ncells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		pr_warn("%pOF lacks #power-domain-cells\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	pd->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		    GENPD_FLAG_ACTIVE_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	pd->attach_dev = cpg_mstp_attach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	pd->detach_dev = cpg_mstp_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	pm_genpd_init(pd, &pm_domain_always_on_gov, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	of_genpd_add_provider_simple(np, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }