Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * EMMA Mobile EV2 common clock framework support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2012 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* EMEV2 SMU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define USIAU0_RSTCTRL 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USIBU1_RSTCTRL 0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define USIBU2_RSTCTRL 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define USIBU3_RSTCTRL 0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IIC0_RSTCTRL 0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IIC1_RSTCTRL 0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STI_RSTCTRL 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STI_CLKSEL 0x688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_SPINLOCK(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* not pretty, but hey */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void __iomem *smu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void __init emev2_smu_write(unsigned long value, int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	BUG_ON(!smu_base || (offs >= PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	writel_relaxed(value, smu_base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct of_device_id smu_id[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	{ .compatible = "renesas,emev2-smu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void __init emev2_smu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	np = of_find_matching_node(NULL, smu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	BUG_ON(!np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	smu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	BUG_ON(!smu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	/* setup STI timer to run on 32.768 kHz and deassert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	emev2_smu_write(0, STI_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	emev2_smu_write(1, STI_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	/* deassert reset for UART0->UART3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	emev2_smu_write(2, USIAU0_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	emev2_smu_write(2, USIBU1_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	emev2_smu_write(2, USIBU2_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	emev2_smu_write(2, USIBU3_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	/* deassert reset for IIC0->IIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	emev2_smu_write(1, IIC0_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	emev2_smu_write(1, IIC1_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void __init emev2_smu_clkdiv_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	u32 reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	const char *parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	if (!smu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		emev2_smu_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	clk = clk_register_divider(NULL, np->name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 				   smu_base + reg[0], reg[1], 8, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	clk_register_clkdev(clk, np->full_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	pr_debug("## %s %pOFn %p\n", __func__, np, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		emev2_smu_clkdiv_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void __init emev2_smu_gclk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	u32 reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	const char *parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	if (!smu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 		emev2_smu_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 	clk = clk_register_gate(NULL, np->name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 				smu_base + reg[0], reg[1], 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 	of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 	clk_register_clkdev(clk, np->full_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 	pr_debug("## %s %pOFn %p\n", __func__, np, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);