^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) config CLK_RENESAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) default y if ARCH_RENESAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) select CLK_EMEV2 if ARCH_EMEV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) select CLK_RZA1 if ARCH_R7S72100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) select CLK_R7S9210 if ARCH_R7S9210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) select CLK_R8A73A4 if ARCH_R8A73A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) select CLK_R8A7740 if ARCH_R8A7740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) select CLK_R8A7742 if ARCH_R8A7742
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) select CLK_R8A7745 if ARCH_R8A7745
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) select CLK_R8A77470 if ARCH_R8A77470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) select CLK_R8A774A1 if ARCH_R8A774A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) select CLK_R8A774B1 if ARCH_R8A774B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) select CLK_R8A774C0 if ARCH_R8A774C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) select CLK_R8A774E1 if ARCH_R8A774E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) select CLK_R8A7778 if ARCH_R8A7778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) select CLK_R8A7779 if ARCH_R8A7779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) select CLK_R8A7790 if ARCH_R8A7790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) select CLK_R8A7792 if ARCH_R8A7792
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) select CLK_R8A7794 if ARCH_R8A7794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) select CLK_R8A77960 if ARCH_R8A77960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) select CLK_R8A77961 if ARCH_R8A77961
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) select CLK_R8A77965 if ARCH_R8A77965
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) select CLK_R8A77970 if ARCH_R8A77970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) select CLK_R8A77980 if ARCH_R8A77980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) select CLK_R8A77990 if ARCH_R8A77990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) select CLK_R8A77995 if ARCH_R8A77995
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) select CLK_R8A779A0 if ARCH_R8A779A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) select CLK_R9A06G032 if ARCH_R9A06G032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) select CLK_SH73A0 if ARCH_SH73A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if CLK_RENESAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) config CLK_EMEV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool "Emma Mobile EV2 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) config CLK_RZA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool "RZ/A1H clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) select CLK_RENESAS_CPG_MSTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) config CLK_R7S9210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool "RZ/A2 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) select CLK_RENESAS_CPG_MSSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) config CLK_R8A73A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool "R-Mobile APE6 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) select CLK_RENESAS_CPG_MSTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) select CLK_RENESAS_DIV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) config CLK_R8A7740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool "R-Mobile A1 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) select CLK_RENESAS_CPG_MSTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) select CLK_RENESAS_DIV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) config CLK_R8A7742
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool "RZ/G1H clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) config CLK_R8A7743
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bool "RZ/G1M clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) config CLK_R8A7745
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool "RZ/G1E clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) config CLK_R8A77470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bool "RZ/G1C clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) config CLK_R8A774A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool "RZ/G2M clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) config CLK_R8A774B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bool "RZ/G2N clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) config CLK_R8A774C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool "RZ/G2E clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) config CLK_R8A774E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bool "RZ/G2H clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) config CLK_R8A7778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bool "R-Car M1A clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) select CLK_RENESAS_CPG_MSTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) config CLK_R8A7779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bool "R-Car H1 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) select CLK_RENESAS_CPG_MSTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) config CLK_R8A7790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool "R-Car H2 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) config CLK_R8A7791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bool "R-Car M2-W/N clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) config CLK_R8A7792
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool "R-Car V2H clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) config CLK_R8A7794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool "R-Car E2 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) select CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) config CLK_R8A7795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bool "R-Car H3 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) config CLK_R8A77960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool "R-Car M3-W clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) config CLK_R8A77961
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bool "R-Car M3-W+ clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config CLK_R8A77965
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bool "R-Car M3-N clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) config CLK_R8A77970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bool "R-Car V3M clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) config CLK_R8A77980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool "R-Car V3H clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) config CLK_R8A77990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool "R-Car E3 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) config CLK_R8A77995
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bool "R-Car D3 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) select CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) config CLK_R8A779A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool "R-Car V3U clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) select CLK_RENESAS_CPG_MSSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) config CLK_R9A06G032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool "Renesas R9A06G032 clock driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) This is a driver for R9A06G032 clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) config CLK_SH73A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bool "SH-Mobile AG5 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) select CLK_RENESAS_CPG_MSTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) select CLK_RENESAS_DIV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # Family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) config CLK_RCAR_GEN2_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) select CLK_RENESAS_CPG_MSSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) config CLK_RCAR_GEN3_CPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) select CLK_RENESAS_CPG_MSSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) config CLK_RCAR_USB2_CLOCK_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bool "Renesas R-Car USB2 clock selector support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) depends on ARCH_RENESAS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) select RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) This is a driver for R-Car USB2 clock selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # Generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) config CLK_RENESAS_CPG_MSSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool "CPG/MSSR clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) select CLK_RENESAS_DIV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) config CLK_RENESAS_CPG_MSTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool "MSTP clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) config CLK_RENESAS_DIV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bool "DIV6 clock support" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) endif # CLK_RENESAS
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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