^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/qcom,videocc-sm8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) P_CHIP_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_VIDEO_PLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_VIDEO_PLL1_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct pll_vco lucid_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { 249600000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct alpha_pll_config video_pll0_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .l = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .alpha = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .config_ctl_val = 0x20485699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .config_ctl_hi_val = 0x00002261,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .config_ctl_hi1_val = 0x329A699C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .user_ctl_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .user_ctl_hi_val = 0x00000805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .user_ctl_hi1_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct clk_alpha_pll video_pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .offset = 0x42c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .vco_table = lucid_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .num_vco = ARRAY_SIZE(lucid_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .name = "video_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .ops = &clk_alpha_pll_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct alpha_pll_config video_pll1_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .l = 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .alpha = 0xC000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .config_ctl_val = 0x20485699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .config_ctl_hi_val = 0x00002261,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .config_ctl_hi1_val = 0x329A699C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .user_ctl_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .user_ctl_hi_val = 0x00000805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .user_ctl_hi1_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct clk_alpha_pll video_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .offset = 0x7d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .vco_table = lucid_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .num_vco = ARRAY_SIZE(lucid_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "video_pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ops = &clk_alpha_pll_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct parent_map video_cc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { P_VIDEO_PLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct clk_parent_data video_cc_parent_data_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .hw = &video_pll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct parent_map video_cc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { P_VIDEO_PLL1_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct clk_parent_data video_cc_parent_data_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { .hw = &video_pll1.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct clk_rcg2 video_cc_mvs0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .cmd_rcgr = 0xb94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .parent_map = video_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .freq_tbl = ftbl_video_cc_mvs0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "video_cc_mvs0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .parent_data = video_cc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct clk_rcg2 video_cc_mvs1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .cmd_rcgr = 0xbb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .parent_map = video_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .freq_tbl = ftbl_video_cc_mvs1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = "video_cc_mvs1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .parent_data = video_cc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg = 0xc54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "video_cc_mvs0c_div2_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .hw = &video_cc_mvs0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .reg = 0xcf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "video_cc_mvs1c_div2_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .hw = &video_cc_mvs1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct clk_branch video_cc_mvs0c_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .halt_reg = 0xc34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .enable_reg = 0xc34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "video_cc_mvs0c_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .hw = &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct clk_branch video_cc_mvs1_div2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .halt_reg = 0xdf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .enable_reg = 0xdf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .name = "video_cc_mvs1_div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct clk_branch video_cc_mvs1c_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .halt_reg = 0xcd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .enable_reg = 0xcd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .name = "video_cc_mvs1c_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct gdsc mvs0c_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .gdscr = 0xbf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "mvs0c_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct gdsc mvs1c_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .gdscr = 0xc98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .name = "mvs1c_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct gdsc mvs0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .gdscr = 0xd18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "mvs0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct gdsc mvs1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .gdscr = 0xd98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "mvs1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct clk_regmap *video_cc_sm8250_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [VIDEO_CC_PLL0] = &video_pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [VIDEO_CC_PLL1] = &video_pll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct qcom_reset_map video_cc_sm8250_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct gdsc *video_cc_sm8250_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [MVS0C_GDSC] = &mvs0c_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [MVS1C_GDSC] = &mvs1c_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [MVS0_GDSC] = &mvs0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [MVS1_GDSC] = &mvs1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct regmap_config video_cc_sm8250_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .max_register = 0xf4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct qcom_cc_desc video_cc_sm8250_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .config = &video_cc_sm8250_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .clks = video_cc_sm8250_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .num_clks = ARRAY_SIZE(video_cc_sm8250_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .resets = video_cc_sm8250_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .num_resets = ARRAY_SIZE(video_cc_sm8250_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .gdscs = video_cc_sm8250_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .num_gdscs = ARRAY_SIZE(video_cc_sm8250_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct of_device_id video_cc_sm8250_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .compatible = "qcom,sm8250-videocc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int video_cc_sm8250_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct platform_driver video_cc_sm8250_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .probe = video_cc_sm8250_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .name = "sm8250-videocc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .of_match_table = video_cc_sm8250_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int __init video_cc_sm8250_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return platform_driver_register(&video_cc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) subsys_initcall(video_cc_sm8250_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void __exit video_cc_sm8250_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) platform_driver_unregister(&video_cc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) module_exit(video_cc_sm8250_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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