Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <dt-bindings/clock/qcom,videocc-sm8150.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	P_CHIP_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	P_VIDEO_PLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	P_VIDEO_PLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	P_VIDEO_PLL0_OUT_ODD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static struct pll_vco trion_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{ 249600000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static struct alpha_pll_config video_pll0_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.l = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.alpha = 0xD555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.config_ctl_val = 0x20485699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.config_ctl_hi_val = 0x00002267,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.config_ctl_hi1_val = 0x00000024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.user_ctl_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.user_ctl_hi_val = 0x00000805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.user_ctl_hi1_val = 0x000000D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static struct clk_alpha_pll video_pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.offset = 0x42c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.vco_table = trion_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.num_vco = ARRAY_SIZE(trion_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			.name = "video_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			.parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				.fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			.ops = &clk_alpha_pll_trion_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const struct parent_map video_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ P_VIDEO_PLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct clk_parent_data video_cc_parent_data_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ .hw = &video_pll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static struct clk_rcg2 video_cc_iris_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.cmd_rcgr = 0x7f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.parent_map = video_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.freq_tbl = ftbl_video_cc_iris_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.name = "video_cc_iris_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.parent_data = video_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static struct clk_branch video_cc_iris_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.halt_reg = 0x8f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.enable_reg = 0x8f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			.name = "video_cc_iris_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			.parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				.hw = &video_cc_iris_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct clk_branch video_cc_mvs0_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.halt_reg = 0x890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.enable_reg = 0x890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			.name = "video_cc_mvs0_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			.parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				.hw = &video_cc_iris_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct clk_branch video_cc_mvs1_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.halt_reg = 0x8d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.enable_reg = 0x8d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			.name = "video_cc_mvs1_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			.parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				.hw = &video_cc_iris_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct clk_branch video_cc_mvsc_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.halt_reg = 0x850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.enable_reg = 0x850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			.name = "video_cc_mvsc_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			.parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				.hw = &video_cc_iris_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct gdsc venus_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.gdscr = 0x814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.name = "venus_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct gdsc vcodec0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.gdscr = 0x874,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.name = "vcodec0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct gdsc vcodec1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.gdscr = 0x8b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.name = "vcodec1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct clk_regmap *video_cc_sm8150_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	[VIDEO_CC_PLL0] = &video_pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct gdsc *video_cc_sm8150_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	[VENUS_GDSC] = &venus_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	[VCODEC0_GDSC] = &vcodec0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	[VCODEC1_GDSC] = &vcodec1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct regmap_config video_cc_sm8150_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.max_register	= 0xb94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.fast_io	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct qcom_reset_map video_cc_sm8150_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct qcom_cc_desc video_cc_sm8150_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.config = &video_cc_sm8150_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.clks = video_cc_sm8150_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.resets = video_cc_sm8150_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.gdscs = video_cc_sm8150_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct of_device_id video_cc_sm8150_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{ .compatible = "qcom,sm8150-videocc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int video_cc_sm8150_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	regmap_update_bits(regmap, 0x984, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct platform_driver video_cc_sm8150_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.probe = video_cc_sm8150_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.name	= "video_cc-sm8150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.of_match_table = video_cc_sm8150_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int __init video_cc_sm8150_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return platform_driver_register(&video_cc_sm8150_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) subsys_initcall(video_cc_sm8150_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void __exit video_cc_sm8150_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	platform_driver_unregister(&video_cc_sm8150_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) module_exit(video_cc_sm8150_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");