Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <dt-bindings/clock/qcom,videocc-sdm845.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	P_VIDEO_PLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	P_VIDEO_PLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	P_VIDEO_PLL0_OUT_ODD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static const struct parent_map video_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{ P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{ P_VIDEO_PLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ P_VIDEO_PLL0_OUT_EVEN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ P_VIDEO_PLL0_OUT_ODD, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	{ P_CORE_BI_PLL_TEST_SE, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static const char * const video_cc_parent_names_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	"bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	"video_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	"video_pll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	"video_pll0_out_odd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	"core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static const struct alpha_pll_config video_pll0_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.l = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.alpha = 0xaaab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static struct clk_alpha_pll video_pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.offset = 0x42c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			.name = "video_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			.parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			.ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct clk_rcg2 video_cc_venus_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.cmd_rcgr = 0x7f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.parent_map = video_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.freq_tbl = ftbl_video_cc_venus_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.name = "video_cc_venus_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.parent_names = video_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static struct clk_branch video_cc_apb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.halt_reg = 0x990,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.enable_reg = 0x990,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			.name = "video_cc_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct clk_branch video_cc_at_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.halt_reg = 0x9f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.enable_reg = 0x9f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			.name = "video_cc_at_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct clk_branch video_cc_qdss_trig_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.halt_reg = 0x970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.enable_reg = 0x970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			.name = "video_cc_qdss_trig_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.halt_reg = 0x9d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.enable_reg = 0x9d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			.name = "video_cc_qdss_tsctr_div8_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clk_branch video_cc_vcodec0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.halt_reg = 0x930,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.enable_reg = 0x930,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			.name = "video_cc_vcodec0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clk_branch video_cc_vcodec0_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.halt_reg = 0x890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.enable_reg = 0x890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			.name = "video_cc_vcodec0_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			.parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				"video_cc_venus_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct clk_branch video_cc_vcodec1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.halt_reg = 0x950,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.enable_reg = 0x950,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			.name = "video_cc_vcodec1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clk_branch video_cc_vcodec1_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.halt_reg = 0x8d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.enable_reg = 0x8d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			.name = "video_cc_vcodec1_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			.parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				"video_cc_venus_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct clk_branch video_cc_venus_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.halt_reg = 0x9b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.enable_reg = 0x9b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			.name = "video_cc_venus_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct clk_branch video_cc_venus_ctl_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.halt_reg = 0x910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.enable_reg = 0x910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			.name = "video_cc_venus_ctl_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct clk_branch video_cc_venus_ctl_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.halt_reg = 0x850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.enable_reg = 0x850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			.name = "video_cc_venus_ctl_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			.parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				"video_cc_venus_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct gdsc venus_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.gdscr = 0x814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.name = "venus_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.cxcs = (unsigned int []){ 0x850, 0x910 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct gdsc vcodec0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.gdscr = 0x874,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.name = "vcodec0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.cxcs = (unsigned int []){ 0x890, 0x930 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.flags = HW_CTRL | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct gdsc vcodec1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.gdscr = 0x8b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.name = "vcodec1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.cxcs = (unsigned int []){ 0x8d0, 0x950 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.flags = HW_CTRL | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct clk_regmap *video_cc_sdm845_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	[VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	[VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	[VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	[VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	[VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	[VIDEO_PLL0] = &video_pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct gdsc *video_cc_sdm845_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	[VENUS_GDSC] = &venus_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	[VCODEC0_GDSC] = &vcodec0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	[VCODEC1_GDSC] = &vcodec1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct regmap_config video_cc_sdm845_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.max_register	= 0xb90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.fast_io	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct qcom_cc_desc video_cc_sdm845_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.config = &video_cc_sdm845_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.clks = video_cc_sdm845_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.gdscs = video_cc_sdm845_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct of_device_id video_cc_sdm845_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{ .compatible = "qcom,sdm845-videocc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int video_cc_sdm845_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct platform_driver video_cc_sdm845_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.probe		= video_cc_sdm845_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.name	= "sdm845-videocc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.of_match_table = video_cc_sdm845_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.sync_state = clk_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int __init video_cc_sdm845_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return platform_driver_register(&video_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) subsys_initcall(video_cc_sdm845_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void __exit video_cc_sdm845_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	platform_driver_unregister(&video_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) module_exit(video_cc_sdm845_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MODULE_LICENSE("GPL v2");