^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct clk_branch turing_wrapper_aon_cbcr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .halt_reg = 0x5098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .enable_reg = 0x5098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = "turing_wrapper_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .ops = &clk_branch2_aon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct clk_branch turing_q6ss_ahbm_aon_cbcr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .halt_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .enable_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .name = "turing_q6ss_ahbm_aon_cbcr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct clk_branch turing_q6ss_q6_axim_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .halt_reg = 0xb000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .enable_reg = 0xb000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .name = "turing_q6ss_q6_axim_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .ops = &clk_branch2_aon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct clk_branch turing_q6ss_ahbs_aon_cbcr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .halt_reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .enable_reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "turing_q6ss_ahbs_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .ops = &clk_branch2_aon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct clk_branch turing_wrapper_qos_ahbs_aon_cbcr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .halt_reg = 0x11014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .enable_reg = 0x11014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .name = "turing_wrapper_qos_ahbs_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ops = &clk_branch2_aon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct clk_regmap *turingcc_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [TURING_WRAPPER_AON_CLK] = &turing_wrapper_aon_cbcr.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [TURING_Q6SS_AHBM_AON_CLK] = &turing_q6ss_ahbm_aon_cbcr.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [TURING_Q6SS_Q6_AXIM_CLK] = &turing_q6ss_q6_axim_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [TURING_Q6SS_AHBS_AON_CLK] = &turing_q6ss_ahbs_aon_cbcr.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [TURING_WRAPPER_QOS_AHBS_AON_CLK] = &turing_wrapper_qos_ahbs_aon_cbcr.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct regmap_config turingcc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .max_register = 0x23004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct qcom_cc_desc turingcc_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .config = &turingcc_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .clks = turingcc_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_clks = ARRAY_SIZE(turingcc_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int turingcc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = pm_clk_create(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto disable_pm_runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = pm_clk_add(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_err(&pdev->dev, "failed to acquire iface clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = qcom_cc_probe(pdev, &turingcc_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) destroy_pm_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) disable_pm_runtime:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int turingcc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct dev_pm_ops turingcc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct of_device_id turingcc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .compatible = "qcom,qcs404-turingcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MODULE_DEVICE_TABLE(of, turingcc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct platform_driver turingcc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .probe = turingcc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .remove = turingcc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = "qcs404-turingcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .of_match_table = turingcc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pm = &turingcc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) module_platform_driver(turingcc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MODULE_DESCRIPTION("Qualcomm QCS404 Turing Clock Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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