Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	rcdev->ops->assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	rcdev->ops->deassert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct qcom_reset_controller *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	const struct qcom_reset_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	rst = to_qcom_reset_controller(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	map = &rst->reset_map[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	mask = BIT(map->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return regmap_update_bits(rst->regmap, map->reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct qcom_reset_controller *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	const struct qcom_reset_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	rst = to_qcom_reset_controller(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	map = &rst->reset_map[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	mask = BIT(map->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	return regmap_update_bits(rst->regmap, map->reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const struct reset_control_ops qcom_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	.reset = qcom_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.assert = qcom_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.deassert = qcom_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) EXPORT_SYMBOL_GPL(qcom_reset_ops);