Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pm_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <dt-bindings/clock/qcom,q6sstopcc-qcs404.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static struct clk_branch lcc_ahbfabric_cbc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	.halt_reg = 0x1b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.enable_reg = 0x1b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			.name = "lcc_ahbfabric_cbc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static struct clk_branch lcc_q6ss_ahbs_cbc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.halt_reg = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.enable_reg = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			.name = "lcc_q6ss_ahbs_cbc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.halt_reg = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.enable_reg = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			.name = "lcc_q6ss_tcm_slave_cbc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static struct clk_branch lcc_q6ss_ahbm_cbc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.halt_reg = 0x22004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.enable_reg = 0x22004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			.name = "lcc_q6ss_ahbm_cbc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct clk_branch lcc_q6ss_axim_cbc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.halt_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.enable_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			.name = "lcc_q6ss_axim_cbc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static struct clk_branch lcc_q6ss_bcr_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.halt_reg = 0x6004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.enable_reg = 0x6004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			.name = "lcc_q6ss_bcr_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* TCSR clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct clk_branch tcsr_lcc_csr_cbcr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.halt_reg = 0x8008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.enable_reg = 0x8008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			.name = "tcsr_lcc_csr_cbcr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct regmap_config q6sstop_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.fast_io	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct clk_regmap *q6sstop_qcs404_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[LCC_AHBFABRIC_CBC_CLK] = &lcc_ahbfabric_cbc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	[LCC_Q6SS_AHBS_CBC_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	[LCC_Q6SS_TCM_SLAVE_CBC_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	[LCC_Q6SS_AHBM_CBC_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	[LCC_Q6SS_AXIM_CBC_CLK] = &lcc_q6ss_axim_cbc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	[LCC_Q6SS_BCR_SLEEP_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct qcom_reset_map q6sstop_qcs404_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	[Q6SSTOP_BCR_RESET] = { 0x6000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct qcom_cc_desc q6sstop_qcs404_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.config = &q6sstop_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.clks = q6sstop_qcs404_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.num_clks = ARRAY_SIZE(q6sstop_qcs404_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.resets = q6sstop_qcs404_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.num_resets = ARRAY_SIZE(q6sstop_qcs404_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct clk_regmap *tcsr_qcs404_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	[TCSR_Q6SS_LCC_CBCR_CLK] = &tcsr_lcc_csr_cbcr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct qcom_cc_desc tcsr_qcs404_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.config = &q6sstop_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.clks = tcsr_qcs404_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.num_clks = ARRAY_SIZE(tcsr_qcs404_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct of_device_id q6sstopcc_qcs404_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ .compatible = "qcom,qcs404-q6sstopcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MODULE_DEVICE_TABLE(of, q6sstopcc_qcs404_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int q6sstopcc_qcs404_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	const struct qcom_cc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ret = pm_clk_create(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto disable_pm_runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ret = pm_clk_add(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		dev_err(&pdev->dev, "failed to acquire iface clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	q6sstop_regmap_config.name = "q6sstop_tcsr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	desc = &tcsr_qcs404_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ret = qcom_cc_probe_by_index(pdev, 1, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	q6sstop_regmap_config.name = "q6sstop_cc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	desc = &q6sstop_qcs404_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ret = qcom_cc_probe_by_index(pdev, 0, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) destroy_pm_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) disable_pm_runtime:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int q6sstopcc_qcs404_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct dev_pm_ops q6sstopcc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct platform_driver q6sstopcc_qcs404_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.probe		= q6sstopcc_qcs404_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.remove		= q6sstopcc_qcs404_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.name	= "qcs404-q6sstopcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.of_match_table = q6sstopcc_qcs404_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.pm = &q6sstopcc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) module_platform_driver(q6sstopcc_qcs404_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_LICENSE("GPL v2");