^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL0_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_MMPLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_MMPLL1_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_MMPLL3_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_MMPLL4_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_MMPLL5_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_MMPLL6_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_MMPLL7_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_MMPLL10_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_DSI0PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_DSI1PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_DSI0PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) P_DSI1PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) P_HDMIPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) P_DPVCO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) P_DPLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct clk_fixed_factor gpll0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "mmss_gpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .fw_name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = "gpll0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct clk_div_table post_div_table_fabia_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 0x0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0x3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0x7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct clk_alpha_pll mmpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .offset = 0xc000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .enable_reg = 0x1e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct clk_alpha_pll_postdiv mmpll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .offset = 0xc000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "mmpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clk_alpha_pll mmpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .offset = 0xc050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .enable_reg = 0x1e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct clk_alpha_pll_postdiv mmpll1_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .offset = 0xc050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "mmpll1_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct clk_alpha_pll mmpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct clk_alpha_pll_postdiv mmpll3_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "mmpll3_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct clk_alpha_pll mmpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .offset = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct clk_alpha_pll_postdiv mmpll4_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .offset = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "mmpll4_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct clk_alpha_pll mmpll5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .offset = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "mmpll5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct clk_alpha_pll_postdiv mmpll5_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .offset = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "mmpll5_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct clk_alpha_pll mmpll6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .offset = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "mmpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct clk_alpha_pll_postdiv mmpll6_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .offset = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "mmpll6_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct clk_alpha_pll mmpll7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .offset = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "mmpll7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct clk_alpha_pll_postdiv mmpll7_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .offset = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "mmpll7_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct clk_alpha_pll mmpll10 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .offset = 0x190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .name = "mmpll10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct clk_alpha_pll_postdiv mmpll10_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .offset = 0x190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "mmpll10_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct parent_map mmss_xo_hdmi_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { P_HDMIPLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct clk_parent_data mmss_xo_hdmi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { .fw_name = "hdmipll", .name = "hdmipll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { P_DSI0PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { P_DSI1PLL, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { .fw_name = "dsi0dsi", .name = "dsi0dsi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { .fw_name = "dsi1dsi", .name = "dsi1dsi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct parent_map mmss_xo_dsibyte_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { P_DSI0PLL_BYTE, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { P_DSI1PLL_BYTE, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct clk_parent_data mmss_xo_dsibyte[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { .fw_name = "dsi0byte", .name = "dsi0byte" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { .fw_name = "dsi1byte", .name = "dsi1byte" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct parent_map mmss_xo_dp_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { P_DPLINK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { P_DPVCO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct clk_parent_data mmss_xo_dp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .fw_name = "dplink", .name = "dplink" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .fw_name = "dpvco", .name = "dpvco" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { P_MMPLL0_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .hw = &mmpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { P_MMPLL0_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { P_MMPLL1_OUT_EVEN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { .hw = &mmpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { .hw = &mmpll1_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { P_MMPLL0_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { P_MMPLL5_OUT_EVEN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .hw = &mmpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { .hw = &mmpll5_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { P_MMPLL0_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { P_MMPLL3_OUT_EVEN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { P_MMPLL6_OUT_EVEN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { .hw = &mmpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { .hw = &mmpll3_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .hw = &mmpll6_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { P_MMPLL4_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { P_MMPLL7_OUT_EVEN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { P_MMPLL10_OUT_EVEN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { .hw = &mmpll4_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { .hw = &mmpll7_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { .hw = &mmpll10_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { P_MMPLL0_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { P_MMPLL7_OUT_EVEN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { P_MMPLL10_OUT_EVEN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { .hw = &mmpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { .hw = &mmpll7_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { .hw = &mmpll10_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { P_MMPLL0_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { P_MMPLL4_OUT_EVEN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { P_MMPLL7_OUT_EVEN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { P_MMPLL10_OUT_EVEN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { P_GPLL0_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { P_CORE_BI_PLL_TEST_SE, 7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { .fw_name = "xo", .name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { .hw = &mmpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { .hw = &mmpll4_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { .hw = &mmpll7_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { .hw = &mmpll10_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { .hw = &gpll0_div.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct clk_rcg2 byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .cmd_rcgr = 0x2120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .parent_data = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static struct clk_rcg2 byte1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .cmd_rcgr = 0x2140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .name = "byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .parent_data = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct freq_tbl ftbl_cci_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct clk_rcg2 cci_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .cmd_rcgr = 0x3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .freq_tbl = ftbl_cci_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .name = "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct freq_tbl ftbl_cpp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) F(600000000, P_GPLL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct clk_rcg2 cpp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .cmd_rcgr = 0x3640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .freq_tbl = ftbl_cpp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const struct freq_tbl ftbl_csi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct clk_rcg2 csi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .cmd_rcgr = 0x3090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .freq_tbl = ftbl_csi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct clk_rcg2 csi1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .cmd_rcgr = 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .freq_tbl = ftbl_csi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct clk_rcg2 csi2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .cmd_rcgr = 0x3160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .freq_tbl = ftbl_csi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .name = "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static struct clk_rcg2 csi3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .cmd_rcgr = 0x31c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .freq_tbl = ftbl_csi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .name = "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct freq_tbl ftbl_csiphy_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static struct clk_rcg2 csiphy_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .cmd_rcgr = 0x3800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .freq_tbl = ftbl_csiphy_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .name = "csiphy_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static struct clk_rcg2 csi0phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .cmd_rcgr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .freq_tbl = ftbl_csiphytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .name = "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static struct clk_rcg2 csi1phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .cmd_rcgr = 0x3030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .freq_tbl = ftbl_csiphytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .name = "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct clk_rcg2 csi2phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .cmd_rcgr = 0x3060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .freq_tbl = ftbl_csiphytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .name = "csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static struct clk_rcg2 dp_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .cmd_rcgr = 0x2260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .parent_map = mmss_xo_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .freq_tbl = ftbl_dp_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .name = "dp_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .parent_data = mmss_xo_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) F(101250, P_DPLINK, 1, 5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) F(168750, P_DPLINK, 1, 5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) F(337500, P_DPLINK, 1, 5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static struct clk_rcg2 dp_crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .cmd_rcgr = 0x2220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .parent_map = mmss_xo_dp_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .freq_tbl = ftbl_dp_crypto_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .name = "dp_crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .parent_data = mmss_xo_dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const struct freq_tbl ftbl_dp_link_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) F(162000, P_DPLINK, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) F(270000, P_DPLINK, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) F(540000, P_DPLINK, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static struct clk_rcg2 dp_link_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .cmd_rcgr = 0x2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .parent_map = mmss_xo_dp_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .freq_tbl = ftbl_dp_link_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .name = "dp_link_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .parent_data = mmss_xo_dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) F(154000000, P_DPVCO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) F(337500000, P_DPVCO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) F(675000000, P_DPVCO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct clk_rcg2 dp_pixel_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .cmd_rcgr = 0x2240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .parent_map = mmss_xo_dp_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .freq_tbl = ftbl_dp_pixel_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .name = "dp_pixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .parent_data = mmss_xo_dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const struct freq_tbl ftbl_esc_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static struct clk_rcg2 esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .cmd_rcgr = 0x2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .freq_tbl = ftbl_esc_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .name = "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .parent_data = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static struct clk_rcg2 esc1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .cmd_rcgr = 0x2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .freq_tbl = ftbl_esc_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .name = "esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .parent_data = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const struct freq_tbl ftbl_extpclk_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { .src = P_HDMIPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static struct clk_rcg2 extpclk_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .cmd_rcgr = 0x2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .parent_map = mmss_xo_hdmi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .freq_tbl = ftbl_extpclk_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "extpclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .parent_data = mmss_xo_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .ops = &clk_byte_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const struct freq_tbl ftbl_fd_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static struct clk_rcg2 fd_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .cmd_rcgr = 0x3b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .freq_tbl = ftbl_fd_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .name = "fd_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const struct freq_tbl ftbl_hdmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct clk_rcg2 hdmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .cmd_rcgr = 0x2100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .parent_map = mmss_xo_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .freq_tbl = ftbl_hdmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "hdmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .parent_data = mmss_xo_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct clk_rcg2 jpeg0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .cmd_rcgr = 0x3500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .freq_tbl = ftbl_jpeg0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .name = "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const struct freq_tbl ftbl_maxi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) F(75000000, P_GPLL0_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) F(171428571, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static struct clk_rcg2 maxi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .cmd_rcgr = 0xf020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .freq_tbl = ftbl_maxi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .name = "maxi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct freq_tbl ftbl_mclk_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) F(6000000, P_GPLL0_DIV, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) F(8000000, P_GPLL0_DIV, 1, 2, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) F(16666667, P_GPLL0_DIV, 2, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) F(24000000, P_GPLL0_DIV, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) F(33333333, P_GPLL0_DIV, 1, 2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) F(48000000, P_GPLL0, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) F(66666667, P_GPLL0, 1, 2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static struct clk_rcg2 mclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .cmd_rcgr = 0x3360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .freq_tbl = ftbl_mclk_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static struct clk_rcg2 mclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .cmd_rcgr = 0x3390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .freq_tbl = ftbl_mclk_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .name = "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct clk_rcg2 mclk2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .cmd_rcgr = 0x33c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .freq_tbl = ftbl_mclk_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .name = "mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static struct clk_rcg2 mclk3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .cmd_rcgr = 0x33f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .freq_tbl = ftbl_mclk_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .name = "mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const struct freq_tbl ftbl_mdp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) F(85714286, P_GPLL0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) F(171428571, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static struct clk_rcg2 mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .cmd_rcgr = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .freq_tbl = ftbl_mdp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .name = "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const struct freq_tbl ftbl_vsync_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static struct clk_rcg2 vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .cmd_rcgr = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .parent_map = mmss_xo_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .freq_tbl = ftbl_vsync_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .name = "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .parent_data = mmss_xo_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const struct freq_tbl ftbl_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) F(40000000, P_GPLL0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static struct clk_rcg2 ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .cmd_rcgr = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .freq_tbl = ftbl_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .name = "ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const struct freq_tbl ftbl_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) F(171428571, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) F(240000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* RO to linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static struct clk_rcg2 axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .cmd_rcgr = 0xd000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .freq_tbl = ftbl_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .name = "axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct clk_rcg2 pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .cmd_rcgr = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .name = "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .parent_data = mmss_xo_dsi0pll_dsi1pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static struct clk_rcg2 pclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .cmd_rcgr = 0x2020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .name = "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .parent_data = mmss_xo_dsi0pll_dsi1pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const struct freq_tbl ftbl_rot_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) F(171428571, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static struct clk_rcg2 rot_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .cmd_rcgr = 0x21a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .freq_tbl = ftbl_rot_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .name = "rot_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const struct freq_tbl ftbl_video_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static struct clk_rcg2 video_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .cmd_rcgr = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .freq_tbl = ftbl_video_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .name = "video_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static struct clk_rcg2 video_subcore0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .cmd_rcgr = 0x1060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .freq_tbl = ftbl_video_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .name = "video_subcore0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static struct clk_rcg2 video_subcore1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .cmd_rcgr = 0x1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .freq_tbl = ftbl_video_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .name = "video_subcore1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct freq_tbl ftbl_vfe_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) F(600000000, P_GPLL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static struct clk_rcg2 vfe0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .cmd_rcgr = 0x3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .freq_tbl = ftbl_vfe_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .name = "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static struct clk_rcg2 vfe1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .cmd_rcgr = 0x3620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .freq_tbl = ftbl_vfe_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .name = "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .num_parents = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static struct clk_branch misc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .halt_reg = 0x328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .enable_reg = 0x328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .name = "misc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static struct clk_branch video_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .halt_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .enable_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .name = "video_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static struct clk_branch video_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .halt_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .enable_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .name = "video_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static struct clk_branch video_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .halt_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .enable_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .name = "video_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static struct clk_branch video_maxi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .halt_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .enable_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .name = "video_maxi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static struct clk_branch video_subcore0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .halt_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .enable_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .name = "video_subcore0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static struct clk_branch video_subcore1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .halt_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .enable_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .name = "video_subcore1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static struct clk_branch mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .halt_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .enable_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .name = "mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static struct clk_branch mdss_hdmi_dp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .halt_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .enable_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .name = "mdss_hdmi_dp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static struct clk_branch mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .halt_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .enable_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .name = "mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static struct clk_branch mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .halt_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .enable_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .name = "mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static struct clk_branch mdss_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .halt_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .enable_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .name = "mdss_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static struct clk_branch mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .halt_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .enable_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .name = "mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static struct clk_branch mdss_mdp_lut_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .halt_reg = 0x2320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .enable_reg = 0x2320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .name = "mdss_mdp_lut_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static struct clk_branch mdss_extpclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .halt_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .enable_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .name = "mdss_extpclk_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static struct clk_branch mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .halt_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .enable_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .name = "mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static struct clk_branch mdss_hdmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .halt_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .enable_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .name = "mdss_hdmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static struct clk_branch mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .halt_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .enable_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .name = "mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static struct clk_branch mdss_byte1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .halt_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .enable_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .name = "mdss_byte1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static struct clk_branch mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .halt_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .enable_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .name = "mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static struct clk_branch mdss_esc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .halt_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .name = "mdss_esc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static struct clk_branch mdss_rot_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .halt_reg = 0x2350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .enable_reg = 0x2350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .name = "mdss_rot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static struct clk_branch mdss_dp_link_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .halt_reg = 0x2354,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .enable_reg = 0x2354,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .name = "mdss_dp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static struct clk_branch mdss_dp_link_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .halt_reg = 0x2358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .enable_reg = 0x2358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .name = "mdss_dp_link_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static struct clk_branch mdss_dp_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .halt_reg = 0x235c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .enable_reg = 0x235c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .name = "mdss_dp_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static struct clk_branch mdss_dp_pixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .halt_reg = 0x2360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .enable_reg = 0x2360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .name = "mdss_dp_pixel_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static struct clk_branch mdss_dp_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .halt_reg = 0x2364,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .enable_reg = 0x2364,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .name = "mdss_dp_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static struct clk_branch mdss_byte0_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .halt_reg = 0x2374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .enable_reg = 0x2374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .name = "mdss_byte0_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static struct clk_branch mdss_byte1_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .halt_reg = 0x2378,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .enable_reg = 0x2378,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .name = "mdss_byte1_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static struct clk_branch camss_csi0phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .halt_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .enable_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .name = "camss_csi0phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static struct clk_branch camss_csi1phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .halt_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .enable_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .name = "camss_csi1phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static struct clk_branch camss_csi2phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .halt_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .enable_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .name = "camss_csi2phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static struct clk_branch camss_csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .halt_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .enable_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .name = "camss_csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static struct clk_branch camss_csi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .halt_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .enable_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .name = "camss_csi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static struct clk_branch camss_csi0rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .halt_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .enable_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .name = "camss_csi0rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static struct clk_branch camss_csi0pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .halt_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .enable_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .name = "camss_csi0pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) static struct clk_branch camss_csi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .halt_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .enable_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .name = "camss_csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static struct clk_branch camss_csi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .halt_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .enable_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .name = "camss_csi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static struct clk_branch camss_csi1rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .halt_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .enable_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .name = "camss_csi1rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static struct clk_branch camss_csi1pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .halt_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .enable_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .name = "camss_csi1pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static struct clk_branch camss_csi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .halt_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .enable_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .name = "camss_csi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static struct clk_branch camss_csi2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .halt_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .enable_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .name = "camss_csi2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static struct clk_branch camss_csi2rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .halt_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .enable_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .name = "camss_csi2rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static struct clk_branch camss_csi2pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .halt_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .enable_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .name = "camss_csi2pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static struct clk_branch camss_csi3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .halt_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .enable_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .name = "camss_csi3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static struct clk_branch camss_csi3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .halt_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .enable_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .name = "camss_csi3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static struct clk_branch camss_csi3rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .halt_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .enable_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .name = "camss_csi3rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static struct clk_branch camss_csi3pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .halt_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .enable_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .name = "camss_csi3pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static struct clk_branch camss_ispif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .halt_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .enable_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .name = "camss_ispif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static struct clk_branch camss_cci_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .halt_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .enable_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .name = "camss_cci_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static struct clk_branch camss_cci_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .halt_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .enable_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .name = "camss_cci_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static struct clk_branch camss_mclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .halt_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .enable_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .name = "camss_mclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static struct clk_branch camss_mclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .halt_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .enable_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .name = "camss_mclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static struct clk_branch camss_mclk2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .halt_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .enable_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .name = "camss_mclk2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static struct clk_branch camss_mclk3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .halt_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .enable_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .name = "camss_mclk3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static struct clk_branch camss_top_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .halt_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .enable_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .name = "camss_top_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static struct clk_branch camss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .halt_reg = 0x348c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .enable_reg = 0x348c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .name = "camss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static struct clk_branch camss_micro_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .halt_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .enable_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .name = "camss_micro_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static struct clk_branch camss_jpeg0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .halt_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .enable_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .name = "camss_jpeg0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) static struct clk_branch camss_jpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .halt_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .enable_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .name = "camss_jpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) static struct clk_branch camss_jpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .halt_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .enable_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .name = "camss_jpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static struct clk_branch camss_vfe0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .halt_reg = 0x3668,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .enable_reg = 0x3668,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .name = "camss_vfe0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static struct clk_branch camss_vfe1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .halt_reg = 0x3678,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .enable_reg = 0x3678,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .name = "camss_vfe1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) static struct clk_branch camss_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .halt_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .enable_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .name = "camss_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) static struct clk_branch camss_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .halt_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .enable_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .name = "camss_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static struct clk_branch camss_cpp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .halt_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .enable_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .name = "camss_cpp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static struct clk_branch camss_cpp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .halt_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .enable_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .name = "camss_cpp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) static struct clk_branch camss_vfe_vbif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .halt_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .enable_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .name = "camss_vfe_vbif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static struct clk_branch camss_vfe_vbif_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .halt_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .enable_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .name = "camss_vfe_vbif_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static struct clk_branch camss_cpp_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .halt_reg = 0x36c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .enable_reg = 0x36c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .name = "camss_cpp_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static struct clk_branch camss_cpp_vbif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .halt_reg = 0x36c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .enable_reg = 0x36c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .name = "camss_cpp_vbif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) static struct clk_branch camss_csi_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .halt_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .enable_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .name = "camss_csi_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) static struct clk_branch camss_csi_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .halt_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .enable_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .name = "camss_csi_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static struct clk_branch camss_vfe0_stream_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .halt_reg = 0x3720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .enable_reg = 0x3720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .name = "camss_vfe0_stream_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static struct clk_branch camss_vfe1_stream_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .halt_reg = 0x3724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .enable_reg = 0x3724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .name = "camss_vfe1_stream_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static struct clk_branch camss_cphy_csid0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .halt_reg = 0x3730,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .enable_reg = 0x3730,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .name = "camss_cphy_csid0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static struct clk_branch camss_cphy_csid1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .halt_reg = 0x3734,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .enable_reg = 0x3734,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .name = "camss_cphy_csid1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static struct clk_branch camss_cphy_csid2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .halt_reg = 0x3738,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .enable_reg = 0x3738,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .name = "camss_cphy_csid2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) static struct clk_branch camss_cphy_csid3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .halt_reg = 0x373c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .enable_reg = 0x373c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .name = "camss_cphy_csid3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static struct clk_branch camss_csiphy0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .halt_reg = 0x3740,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .enable_reg = 0x3740,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .name = "camss_csiphy0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) static struct clk_branch camss_csiphy1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .halt_reg = 0x3744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .enable_reg = 0x3744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .name = "camss_csiphy1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static struct clk_branch camss_csiphy2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .halt_reg = 0x3748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .enable_reg = 0x3748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .name = "camss_csiphy2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static struct clk_branch fd_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .halt_reg = 0x3b68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .enable_reg = 0x3b68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .name = "fd_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static struct clk_branch fd_core_uar_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .halt_reg = 0x3b6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .enable_reg = 0x3b6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .name = "fd_core_uar_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static struct clk_branch fd_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .halt_reg = 0x3b74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .enable_reg = 0x3b74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .name = "fd_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) static struct clk_branch mnoc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .halt_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .enable_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .name = "mnoc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) static struct clk_branch bimc_smmu_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .halt_reg = 0xe004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .enable_reg = 0xe004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .name = "bimc_smmu_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) static struct clk_branch bimc_smmu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .halt_reg = 0xe008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .enable_reg = 0xe008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .name = "bimc_smmu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) static struct clk_branch mnoc_maxi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .halt_reg = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .enable_reg = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .name = "mnoc_maxi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) static struct clk_branch vmem_maxi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .halt_reg = 0xf064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .enable_reg = 0xf064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .name = "vmem_maxi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) static struct clk_branch vmem_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .halt_reg = 0xf068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .enable_reg = 0xf068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .name = "vmem_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static struct clk_hw *mmcc_msm8998_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) &gpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static struct gdsc video_top_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .gdscr = 0x1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .name = "video_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static struct gdsc video_subcore0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .gdscr = 0x1040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .name = "video_subcore0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .parent = &video_top_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static struct gdsc video_subcore1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .gdscr = 0x1044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .name = "video_subcore1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .parent = &video_top_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .gdscr = 0x2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .cxc_count = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .name = "mdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) static struct gdsc camss_top_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .gdscr = 0x34a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) 0x35a8, 0x3868 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .cxc_count = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .name = "camss_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static struct gdsc camss_vfe0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .gdscr = 0x3664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .name = "camss_vfe0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .parent = &camss_top_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static struct gdsc camss_vfe1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .gdscr = 0x3674,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .name = "camss_vfe1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .parent = &camss_top_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) static struct gdsc camss_cpp_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .gdscr = 0x36d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .name = "camss_cpp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .parent = &camss_top_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static struct gdsc bimc_smmu_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .gdscr = 0xe020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .gds_hw_ctrl = 0xe024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .name = "bimc_smmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static struct clk_regmap *mmcc_msm8998_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) [MMPLL0] = &mmpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) [MMPLL1] = &mmpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) [MMPLL3] = &mmpll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) [MMPLL4] = &mmpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) [MMPLL5] = &mmpll5.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) [MMPLL6] = &mmpll6.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) [MMPLL7] = &mmpll7.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) [MMPLL10] = &mmpll10.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) [CCI_CLK_SRC] = &cci_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) [CPP_CLK_SRC] = &cpp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) [MDP_CLK_SRC] = &mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) [AHB_CLK_SRC] = &ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) [AXI_CLK_SRC] = &axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) [ROT_CLK_SRC] = &rot_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) [VIDEO_CORE_CLK] = &video_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) [FD_CORE_CLK] = &fd_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [FD_AHB_CLK] = &fd_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static struct gdsc *mmcc_msm8998_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) [VIDEO_TOP_GDSC] = &video_top_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) [CAMSS_TOP_GDSC] = &camss_top_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) static const struct qcom_reset_map mmcc_msm8998_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) [SPDM_BCR] = { 0x200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) [SPDM_RM_BCR] = { 0x300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) [MISC_BCR] = { 0x320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) [VIDEO_TOP_BCR] = { 0x1020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) [THROTTLE_VIDEO_BCR] = { 0x1180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) [MDSS_BCR] = { 0x2300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) [THROTTLE_MDSS_BCR] = { 0x2460 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) [CAMSS_PHY0_BCR] = { 0x3020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) [CAMSS_PHY1_BCR] = { 0x3050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) [CAMSS_PHY2_BCR] = { 0x3080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) [CAMSS_CSI0_BCR] = { 0x30b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) [CAMSS_CSI1_BCR] = { 0x3120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) [CAMSS_CSI1RDI_BCR] = { 0x3140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) [CAMSS_CSI1PIX_BCR] = { 0x3150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) [CAMSS_CSI2_BCR] = { 0x3180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) [CAMSS_CSI3_BCR] = { 0x31e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) [CAMSS_CSI3RDI_BCR] = { 0x3200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) [CAMSS_CSI3PIX_BCR] = { 0x3210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) [CAMSS_ISPIF_BCR] = { 0x3220 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) [CAMSS_CCI_BCR] = { 0x3340 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) [CAMSS_TOP_BCR] = { 0x3480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) [CAMSS_AHB_BCR] = { 0x3488 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) [CAMSS_MICRO_BCR] = { 0x3490 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) [CAMSS_JPEG_BCR] = { 0x35a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) [CAMSS_VFE0_BCR] = { 0x3660 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) [CAMSS_VFE1_BCR] = { 0x3670 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) [CAMSS_CPP_BCR] = { 0x36d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) [CAMSS_FD_BCR] = { 0x3b60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) [THROTTLE_CAMSS_BCR] = { 0x3c30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) [MNOCAHB_BCR] = { 0x5020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) [MNOCAXI_BCR] = { 0xd020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) [BMIC_SMMU_BCR] = { 0xe000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) [MNOC_MAXI_BCR] = { 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) [VMEM_BCR] = { 0xf060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) [BTO_BCR] = { 0x10004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static const struct regmap_config mmcc_msm8998_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .max_register = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) static const struct qcom_cc_desc mmcc_msm8998_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .config = &mmcc_msm8998_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .clks = mmcc_msm8998_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .resets = mmcc_msm8998_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .gdscs = mmcc_msm8998_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .clk_hws = mmcc_msm8998_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) static const struct of_device_id mmcc_msm8998_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) { .compatible = "qcom,mmcc-msm8998" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) static int mmcc_msm8998_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) static struct platform_driver mmcc_msm8998_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .probe = mmcc_msm8998_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .name = "mmcc-msm8998",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .of_match_table = mmcc_msm8998_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) module_platform_driver(mmcc_msm8998_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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