^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_MMPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL0_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_MMPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_MMPLL9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_MMPLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_MMPLL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_MMPLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_DSI0PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_DSI1PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_MMPLL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_HDMIPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) P_DSI0PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) P_DSI1PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) P_MMPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct parent_map mmss_xo_hdmi_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { P_HDMIPLL, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const char * const mmss_xo_hdmi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "hdmipll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { P_DSI0PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { P_DSI1PLL, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "dsi1pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char * const mmss_xo_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct parent_map mmss_xo_dsibyte_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { P_DSI0PLL_BYTE, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { P_DSI1PLL_BYTE, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const mmss_xo_dsibyte[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "dsi0pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dsi1pllbyte"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { P_MMPLL3, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { P_MMPLL5, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "mmpll5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { P_MMPLL4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { P_MMPLL9, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { P_MMPLL2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { P_MMPLL8, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { P_GPLL0, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "mmpll9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "mmpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "mmpll8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "gpll0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { P_MMPLL9, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { P_MMPLL2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { P_MMPLL8, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "mmpll9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "mmpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "mmpll8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { P_MMPLL4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { P_MMPLL3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { P_GPLL0_DIV, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "gpll0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct clk_fixed_factor gpll0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "gpll0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct pll_vco mmpll_p_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 250000000, 500000000, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 500000000, 1000000000, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 1000000000, 1500000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 1500000000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct pll_vco mmpll_gfx_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 400000000, 1000000000, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 1000000000, 1500000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 1500000000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct pll_vco mmpll_t_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 500000000, 1500000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct clk_alpha_pll mmpll0_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .vco_table = mmpll_p_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_vco = ARRAY_SIZE(mmpll_p_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .enable_reg = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "mmpll0_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct clk_alpha_pll_postdiv mmpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .name = "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .parent_names = (const char *[]){ "mmpll0_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct clk_alpha_pll mmpll1_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .offset = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .vco_table = mmpll_p_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .num_vco = ARRAY_SIZE(mmpll_p_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .enable_reg = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "mmpll1_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct clk_alpha_pll_postdiv mmpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .offset = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .parent_names = (const char *[]){ "mmpll1_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct clk_alpha_pll mmpll2_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .offset = 0x4100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .vco_table = mmpll_gfx_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "mmpll2_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct clk_alpha_pll_postdiv mmpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .offset = 0x4100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .name = "mmpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .parent_names = (const char *[]){ "mmpll2_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct clk_alpha_pll mmpll3_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .offset = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .vco_table = mmpll_p_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .num_vco = ARRAY_SIZE(mmpll_p_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "mmpll3_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct clk_alpha_pll_postdiv mmpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .offset = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .parent_names = (const char *[]){ "mmpll3_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct clk_alpha_pll mmpll4_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .offset = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .vco_table = mmpll_t_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .num_vco = ARRAY_SIZE(mmpll_t_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "mmpll4_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct clk_alpha_pll_postdiv mmpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .offset = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .parent_names = (const char *[]){ "mmpll4_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct clk_alpha_pll mmpll5_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .offset = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .vco_table = mmpll_p_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .num_vco = ARRAY_SIZE(mmpll_p_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "mmpll5_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct clk_alpha_pll_postdiv mmpll5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .offset = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .name = "mmpll5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .parent_names = (const char *[]){ "mmpll5_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct clk_alpha_pll mmpll8_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .offset = 0x4130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .vco_table = mmpll_gfx_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "mmpll8_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct clk_alpha_pll_postdiv mmpll8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .offset = 0x4130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = "mmpll8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .parent_names = (const char *[]){ "mmpll8_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static struct clk_alpha_pll mmpll9_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .offset = 0x4200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .vco_table = mmpll_t_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .num_vco = ARRAY_SIZE(mmpll_t_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .name = "mmpll9_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct clk_alpha_pll_postdiv mmpll9 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .offset = 0x4200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .name = "mmpll9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .parent_names = (const char *[]){ "mmpll9_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct freq_tbl ftbl_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) F(80000000, P_MMPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct clk_rcg2 ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .cmd_rcgr = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .freq_tbl = ftbl_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .name = "ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct freq_tbl ftbl_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) F(75000000, P_GPLL0_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) F(171430000, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static struct clk_rcg2 axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .cmd_rcgr = 0x5040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .freq_tbl = ftbl_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct clk_rcg2 maxi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .cmd_rcgr = 0x5090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .freq_tbl = ftbl_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .name = "maxi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct clk_rcg2 gfx3d_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .cmd_rcgr = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .ops = &clk_gfx3d_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static struct clk_rcg2 rbbmtimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .cmd_rcgr = 0x4090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .freq_tbl = ftbl_rbbmtimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .name = "rbbmtimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static struct clk_rcg2 isense_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .cmd_rcgr = 0x4010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .name = "isense_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static struct clk_rcg2 rbcpr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .cmd_rcgr = 0x4060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .freq_tbl = ftbl_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct freq_tbl ftbl_video_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) F(75000000, P_GPLL0_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) F(346666667, P_MMPLL3, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) F(520000000, P_MMPLL3, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static struct clk_rcg2 video_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .cmd_rcgr = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .freq_tbl = ftbl_video_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "video_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct clk_rcg2 video_subcore0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .cmd_rcgr = 0x1060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .freq_tbl = ftbl_video_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .name = "video_subcore0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static struct clk_rcg2 video_subcore1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .cmd_rcgr = 0x1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .freq_tbl = ftbl_video_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .name = "video_subcore1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static struct clk_rcg2 pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .cmd_rcgr = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .name = "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .parent_names = mmss_xo_dsi0pll_dsi1pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static struct clk_rcg2 pclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .cmd_rcgr = 0x2020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .name = "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .parent_names = mmss_xo_dsi0pll_dsi1pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const struct freq_tbl ftbl_mdp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) F(85714286, P_GPLL0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) F(171428571, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) F(275000000, P_MMPLL5, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) F(330000000, P_MMPLL5, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) F(412500000, P_MMPLL5, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct clk_rcg2 mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .cmd_rcgr = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .freq_tbl = ftbl_mdp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .name = "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static struct freq_tbl extpclk_freq_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { .src = P_HDMIPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static struct clk_rcg2 extpclk_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .cmd_rcgr = 0x2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .parent_map = mmss_xo_hdmi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .freq_tbl = extpclk_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "extpclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .parent_names = mmss_xo_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .ops = &clk_byte_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static struct freq_tbl ftbl_mdss_vsync_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct clk_rcg2 vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .cmd_rcgr = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .parent_map = mmss_xo_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .freq_tbl = ftbl_mdss_vsync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .parent_names = mmss_xo_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct clk_rcg2 hdmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .cmd_rcgr = 0x2100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .parent_map = mmss_xo_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .freq_tbl = ftbl_mdss_hdmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .name = "hdmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .parent_names = mmss_xo_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static struct clk_rcg2 byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .cmd_rcgr = 0x2120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .parent_names = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static struct clk_rcg2 byte1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .cmd_rcgr = 0x2140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .name = "byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .parent_names = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static struct clk_rcg2 esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .cmd_rcgr = 0x2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .freq_tbl = ftbl_mdss_esc0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .name = "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .parent_names = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static struct clk_rcg2 esc1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .cmd_rcgr = 0x2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .parent_map = mmss_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .freq_tbl = ftbl_mdss_esc0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .name = "esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .parent_names = mmss_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) F(10000, P_XO, 16, 1, 120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) F(24000, P_XO, 16, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) F(6000000, P_GPLL0_DIV, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) F(12000000, P_GPLL0_DIV, 1, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) F(13000000, P_GPLL0_DIV, 2, 13, 150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) F(24000000, P_GPLL0_DIV, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct clk_rcg2 camss_gp0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .cmd_rcgr = 0x3420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .freq_tbl = ftbl_camss_gp0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .name = "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static struct clk_rcg2 camss_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .cmd_rcgr = 0x3450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .freq_tbl = ftbl_camss_gp0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .name = "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const struct freq_tbl ftbl_mclk0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) F(6000000, P_GPLL0_DIV, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) F(8000000, P_GPLL0_DIV, 1, 2, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) F(16666667, P_GPLL0_DIV, 2, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) F(24000000, P_GPLL0_DIV, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) F(33333333, P_GPLL0_DIV, 1, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) F(48000000, P_GPLL0, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) F(66666667, P_GPLL0, 1, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static struct clk_rcg2 mclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .cmd_rcgr = 0x3360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .freq_tbl = ftbl_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .name = "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static struct clk_rcg2 mclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .cmd_rcgr = 0x3390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .freq_tbl = ftbl_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .name = "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct clk_rcg2 mclk2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .cmd_rcgr = 0x33c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .freq_tbl = ftbl_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .name = "mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static struct clk_rcg2 mclk3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .cmd_rcgr = 0x33f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .freq_tbl = ftbl_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .name = "mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const struct freq_tbl ftbl_cci_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct clk_rcg2 cci_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .cmd_rcgr = 0x3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .freq_tbl = ftbl_cci_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .name = "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) F(100000000, P_GPLL0_DIV, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) F(266666667, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static struct clk_rcg2 csi0phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .cmd_rcgr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .freq_tbl = ftbl_csi0phytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .name = "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static struct clk_rcg2 csi1phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .cmd_rcgr = 0x3030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .freq_tbl = ftbl_csi0phytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .name = "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static struct clk_rcg2 csi2phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .cmd_rcgr = 0x3060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .freq_tbl = ftbl_csi0phytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .name = "csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) F(100000000, P_GPLL0_DIV, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) F(320000000, P_MMPLL4, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) F(384000000, P_MMPLL4, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static struct clk_rcg2 csiphy0_3p_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .cmd_rcgr = 0x3240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .freq_tbl = ftbl_csiphy0_3p_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .name = "csiphy0_3p_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static struct clk_rcg2 csiphy1_3p_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .cmd_rcgr = 0x3260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .freq_tbl = ftbl_csiphy0_3p_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .name = "csiphy1_3p_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static struct clk_rcg2 csiphy2_3p_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .cmd_rcgr = 0x3280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .freq_tbl = ftbl_csiphy0_3p_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .name = "csiphy2_3p_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) F(75000000, P_GPLL0_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) F(228571429, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) F(266666667, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) F(480000000, P_MMPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static struct clk_rcg2 jpeg0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .cmd_rcgr = 0x3500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .freq_tbl = ftbl_jpeg0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .name = "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) F(75000000, P_GPLL0_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) F(228571429, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) F(266666667, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static struct clk_rcg2 jpeg2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .cmd_rcgr = 0x3540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .freq_tbl = ftbl_jpeg2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .name = "jpeg2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct clk_rcg2 jpeg_dma_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .cmd_rcgr = 0x3560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .freq_tbl = ftbl_jpeg0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .name = "jpeg_dma_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static const struct freq_tbl ftbl_vfe0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) F(75000000, P_GPLL0_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) F(100000000, P_GPLL0_DIV, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) F(480000000, P_MMPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) F(600000000, P_GPLL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static struct clk_rcg2 vfe0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .cmd_rcgr = 0x3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .freq_tbl = ftbl_vfe0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .name = "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static struct clk_rcg2 vfe1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .cmd_rcgr = 0x3620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .freq_tbl = ftbl_vfe0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .name = "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const struct freq_tbl ftbl_cpp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) F(100000000, P_GPLL0_DIV, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) F(480000000, P_MMPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) F(640000000, P_MMPLL4, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static struct clk_rcg2 cpp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .cmd_rcgr = 0x3640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .freq_tbl = ftbl_cpp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .name = "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const struct freq_tbl ftbl_csi0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) F(100000000, P_GPLL0_DIV, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) F(266666667, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) F(480000000, P_MMPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) F(600000000, P_GPLL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static struct clk_rcg2 csi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .cmd_rcgr = 0x3090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .freq_tbl = ftbl_csi0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .name = "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static struct clk_rcg2 csi1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .cmd_rcgr = 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .freq_tbl = ftbl_csi0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .name = "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static struct clk_rcg2 csi2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .cmd_rcgr = 0x3160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .freq_tbl = ftbl_csi0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .name = "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static struct clk_rcg2 csi3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .cmd_rcgr = 0x31c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .freq_tbl = ftbl_csi0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .name = "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const struct freq_tbl ftbl_fd_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) F(100000000, P_GPLL0_DIV, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static struct clk_rcg2 fd_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .cmd_rcgr = 0x3b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .freq_tbl = ftbl_fd_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .name = "fd_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static struct clk_branch mmss_mmagic_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .halt_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .enable_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .name = "mmss_mmagic_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .halt_reg = 0x5054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .enable_reg = 0x5054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .name = "mmss_mmagic_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static struct clk_branch mmss_misc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .halt_reg = 0x5018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .enable_reg = 0x5018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .name = "mmss_misc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static struct clk_branch mmss_misc_cxo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .halt_reg = 0x5014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .enable_reg = 0x5014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .name = "mmss_misc_cxo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static struct clk_branch mmss_mmagic_maxi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .halt_reg = 0x5074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .enable_reg = 0x5074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .name = "mmss_mmagic_maxi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .parent_names = (const char *[]){ "maxi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static struct clk_branch mmagic_camss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .halt_reg = 0x3c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .enable_reg = 0x3c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .name = "mmagic_camss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .halt_reg = 0x3c48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .enable_reg = 0x3c48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .name = "mmagic_camss_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static struct clk_branch smmu_vfe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .halt_reg = 0x3c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .enable_reg = 0x3c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .name = "smmu_vfe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static struct clk_branch smmu_vfe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .halt_reg = 0x3c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .enable_reg = 0x3c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .name = "smmu_vfe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static struct clk_branch smmu_cpp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .halt_reg = 0x3c14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .enable_reg = 0x3c14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .name = "smmu_cpp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static struct clk_branch smmu_cpp_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .halt_reg = 0x3c18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .enable_reg = 0x3c18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .name = "smmu_cpp_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static struct clk_branch smmu_jpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .halt_reg = 0x3c24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .enable_reg = 0x3c24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .name = "smmu_jpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static struct clk_branch smmu_jpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .halt_reg = 0x3c28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .enable_reg = 0x3c28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .name = "smmu_jpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static struct clk_branch mmagic_mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .halt_reg = 0x2474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .enable_reg = 0x2474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .name = "mmagic_mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .halt_reg = 0x2478,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .enable_reg = 0x2478,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .name = "mmagic_mdss_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static struct clk_branch smmu_rot_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .halt_reg = 0x2444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_reg = 0x2444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .name = "smmu_rot_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static struct clk_branch smmu_rot_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .halt_reg = 0x2448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .enable_reg = 0x2448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .name = "smmu_rot_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static struct clk_branch smmu_mdp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .halt_reg = 0x2454,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .enable_reg = 0x2454,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .name = "smmu_mdp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static struct clk_branch smmu_mdp_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .halt_reg = 0x2458,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .enable_reg = 0x2458,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .name = "smmu_mdp_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static struct clk_branch mmagic_video_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .halt_reg = 0x1194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .enable_reg = 0x1194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .name = "mmagic_video_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .halt_reg = 0x1198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .enable_reg = 0x1198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .name = "mmagic_video_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static struct clk_branch smmu_video_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .halt_reg = 0x1174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .enable_reg = 0x1174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .name = "smmu_video_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static struct clk_branch smmu_video_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .halt_reg = 0x1178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .enable_reg = 0x1178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .name = "smmu_video_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .halt_reg = 0x5298,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .enable_reg = 0x5298,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .name = "mmagic_bimc_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static struct clk_branch gpu_gx_gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .halt_reg = 0x4028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .enable_reg = 0x4028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .name = "gpu_gx_gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .parent_names = (const char *[]){ "gfx3d_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static struct clk_branch gpu_gx_rbbmtimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .halt_reg = 0x40b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .enable_reg = 0x40b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .name = "gpu_gx_rbbmtimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .parent_names = (const char *[]){ "rbbmtimer_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static struct clk_branch gpu_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .halt_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .enable_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .name = "gpu_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static struct clk_branch gpu_aon_isense_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .halt_reg = 0x4044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .enable_reg = 0x4044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .name = "gpu_aon_isense_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .parent_names = (const char *[]){ "isense_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static struct clk_branch vmem_maxi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .halt_reg = 0x1204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .enable_reg = 0x1204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .name = "vmem_maxi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .parent_names = (const char *[]){ "maxi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static struct clk_branch vmem_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .halt_reg = 0x1208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .enable_reg = 0x1208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .name = "vmem_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static struct clk_branch mmss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .halt_reg = 0x4084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .enable_reg = 0x4084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .name = "mmss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .parent_names = (const char *[]){ "rbcpr_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static struct clk_branch mmss_rbcpr_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .halt_reg = 0x4088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .enable_reg = 0x4088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .name = "mmss_rbcpr_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static struct clk_branch video_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .halt_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .enable_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .name = "video_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .parent_names = (const char *[]){ "video_core_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static struct clk_branch video_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .halt_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .enable_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .name = "video_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static struct clk_branch video_maxi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .halt_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .enable_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .name = "video_maxi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .parent_names = (const char *[]){ "maxi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static struct clk_branch video_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .halt_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .enable_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .name = "video_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static struct clk_branch video_subcore0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .halt_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .enable_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .name = "video_subcore0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .parent_names = (const char *[]){ "video_subcore0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static struct clk_branch video_subcore1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .halt_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .enable_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .name = "video_subcore1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .parent_names = (const char *[]){ "video_subcore1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static struct clk_branch mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .halt_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .enable_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .name = "mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static struct clk_branch mdss_hdmi_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .halt_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .enable_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .name = "mdss_hdmi_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static struct clk_branch mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .halt_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .enable_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .name = "mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static struct clk_branch mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .halt_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .enable_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .name = "mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .parent_names = (const char *[]){ "pclk0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static struct clk_branch mdss_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .halt_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .enable_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .name = "mdss_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .parent_names = (const char *[]){ "pclk1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static struct clk_branch mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .halt_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .enable_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .name = "mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .parent_names = (const char *[]){ "mdp_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static struct clk_branch mdss_extpclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .halt_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .enable_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .name = "mdss_extpclk_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .parent_names = (const char *[]){ "extpclk_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static struct clk_branch mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .halt_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .enable_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .name = "mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .parent_names = (const char *[]){ "vsync_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static struct clk_branch mdss_hdmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .halt_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .enable_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .name = "mdss_hdmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .parent_names = (const char *[]){ "hdmi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static struct clk_branch mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .halt_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .enable_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .name = "mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .parent_names = (const char *[]){ "byte0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static struct clk_branch mdss_byte1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .halt_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .enable_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .name = "mdss_byte1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .parent_names = (const char *[]){ "byte1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static struct clk_branch mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .halt_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .enable_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .name = "mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .parent_names = (const char *[]){ "esc0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) static struct clk_branch mdss_esc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .halt_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .enable_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .name = "mdss_esc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .parent_names = (const char *[]){ "esc1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static struct clk_branch camss_top_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .halt_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .enable_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .name = "camss_top_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static struct clk_branch camss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .halt_reg = 0x348c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .enable_reg = 0x348c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .name = "camss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) static struct clk_branch camss_micro_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .halt_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .enable_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .name = "camss_micro_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static struct clk_branch camss_gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .halt_reg = 0x3444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .enable_reg = 0x3444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .name = "camss_gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .parent_names = (const char *[]){ "camss_gp0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static struct clk_branch camss_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .halt_reg = 0x3474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .enable_reg = 0x3474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .name = "camss_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .parent_names = (const char *[]){ "camss_gp1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static struct clk_branch camss_mclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .halt_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .enable_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .name = "camss_mclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .parent_names = (const char *[]){ "mclk0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static struct clk_branch camss_mclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .halt_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .enable_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .name = "camss_mclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .parent_names = (const char *[]){ "mclk1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static struct clk_branch camss_mclk2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .halt_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .enable_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .name = "camss_mclk2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .parent_names = (const char *[]){ "mclk2_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static struct clk_branch camss_mclk3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .halt_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .enable_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .name = "camss_mclk3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .parent_names = (const char *[]){ "mclk3_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static struct clk_branch camss_cci_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .halt_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .enable_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .name = "camss_cci_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .parent_names = (const char *[]){ "cci_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) static struct clk_branch camss_cci_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .halt_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .enable_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .name = "camss_cci_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static struct clk_branch camss_csi0phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .halt_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .enable_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .name = "camss_csi0phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .parent_names = (const char *[]){ "csi0phytimer_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) static struct clk_branch camss_csi1phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .halt_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .enable_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .name = "camss_csi1phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .parent_names = (const char *[]){ "csi1phytimer_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static struct clk_branch camss_csi2phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .halt_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .enable_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .name = "camss_csi2phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .parent_names = (const char *[]){ "csi2phytimer_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static struct clk_branch camss_csiphy0_3p_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .halt_reg = 0x3234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .enable_reg = 0x3234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .name = "camss_csiphy0_3p_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) static struct clk_branch camss_csiphy1_3p_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .halt_reg = 0x3254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .enable_reg = 0x3254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .name = "camss_csiphy1_3p_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static struct clk_branch camss_csiphy2_3p_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .halt_reg = 0x3274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .enable_reg = 0x3274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .name = "camss_csiphy2_3p_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static struct clk_branch camss_jpeg0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .halt_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .enable_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .name = "camss_jpeg0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .parent_names = (const char *[]){ "jpeg0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) static struct clk_branch camss_jpeg2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .halt_reg = 0x35b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .enable_reg = 0x35b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .name = "camss_jpeg2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .parent_names = (const char *[]){ "jpeg2_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static struct clk_branch camss_jpeg_dma_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .halt_reg = 0x35c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .enable_reg = 0x35c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .name = "camss_jpeg_dma_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .parent_names = (const char *[]){ "jpeg_dma_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static struct clk_branch camss_jpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .halt_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .enable_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .name = "camss_jpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static struct clk_branch camss_jpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .halt_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .enable_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .name = "camss_jpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static struct clk_branch camss_vfe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .halt_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .enable_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .name = "camss_vfe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static struct clk_branch camss_vfe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .halt_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .enable_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .name = "camss_vfe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) static struct clk_branch camss_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .halt_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .enable_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .name = "camss_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .parent_names = (const char *[]){ "vfe0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static struct clk_branch camss_vfe0_stream_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .halt_reg = 0x3720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .enable_reg = 0x3720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .name = "camss_vfe0_stream_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .parent_names = (const char *[]){ "vfe0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) static struct clk_branch camss_vfe0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .halt_reg = 0x3668,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .enable_reg = 0x3668,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .name = "camss_vfe0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) static struct clk_branch camss_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .halt_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .enable_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .name = "camss_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .parent_names = (const char *[]){ "vfe1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static struct clk_branch camss_vfe1_stream_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .halt_reg = 0x3724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .enable_reg = 0x3724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .name = "camss_vfe1_stream_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .parent_names = (const char *[]){ "vfe1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) static struct clk_branch camss_vfe1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .halt_reg = 0x3678,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .enable_reg = 0x3678,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .name = "camss_vfe1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) static struct clk_branch camss_csi_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .halt_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .enable_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .name = "camss_csi_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .parent_names = (const char *[]){ "vfe0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) static struct clk_branch camss_csi_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .halt_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .enable_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .name = "camss_csi_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .parent_names = (const char *[]){ "vfe1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static struct clk_branch camss_cpp_vbif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .halt_reg = 0x36c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .enable_reg = 0x36c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .name = "camss_cpp_vbif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static struct clk_branch camss_cpp_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .halt_reg = 0x36c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .enable_reg = 0x36c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .name = "camss_cpp_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .parent_names = (const char *[]){ "axi_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) static struct clk_branch camss_cpp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .halt_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .enable_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .name = "camss_cpp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .parent_names = (const char *[]){ "cpp_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static struct clk_branch camss_cpp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .halt_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .enable_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .name = "camss_cpp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static struct clk_branch camss_csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .halt_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .enable_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .name = "camss_csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .parent_names = (const char *[]){ "csi0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) static struct clk_branch camss_csi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .halt_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .enable_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .name = "camss_csi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static struct clk_branch camss_csi0phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .halt_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .enable_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .name = "camss_csi0phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .parent_names = (const char *[]){ "csi0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) static struct clk_branch camss_csi0rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .halt_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .enable_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .name = "camss_csi0rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .parent_names = (const char *[]){ "csi0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static struct clk_branch camss_csi0pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .halt_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .enable_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .name = "camss_csi0pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .parent_names = (const char *[]){ "csi0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static struct clk_branch camss_csi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .halt_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .enable_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .name = "camss_csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .parent_names = (const char *[]){ "csi1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) static struct clk_branch camss_csi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .halt_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .enable_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .name = "camss_csi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static struct clk_branch camss_csi1phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .halt_reg = 0x3134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .enable_reg = 0x3134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .name = "camss_csi1phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .parent_names = (const char *[]){ "csi1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) static struct clk_branch camss_csi1rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .halt_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .enable_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .name = "camss_csi1rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .parent_names = (const char *[]){ "csi1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static struct clk_branch camss_csi1pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .halt_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .enable_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .name = "camss_csi1pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .parent_names = (const char *[]){ "csi1_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static struct clk_branch camss_csi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .halt_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .enable_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .name = "camss_csi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .parent_names = (const char *[]){ "csi2_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static struct clk_branch camss_csi2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .halt_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .enable_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .name = "camss_csi2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static struct clk_branch camss_csi2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .halt_reg = 0x3194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .enable_reg = 0x3194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .name = "camss_csi2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .parent_names = (const char *[]){ "csi2_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) static struct clk_branch camss_csi2rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .halt_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .enable_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .name = "camss_csi2rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .parent_names = (const char *[]){ "csi2_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) static struct clk_branch camss_csi2pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .halt_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .enable_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .name = "camss_csi2pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .parent_names = (const char *[]){ "csi2_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static struct clk_branch camss_csi3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .halt_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .enable_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .name = "camss_csi3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .parent_names = (const char *[]){ "csi3_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) static struct clk_branch camss_csi3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .halt_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .enable_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .name = "camss_csi3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) static struct clk_branch camss_csi3phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .halt_reg = 0x31f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .enable_reg = 0x31f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .name = "camss_csi3phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .parent_names = (const char *[]){ "csi3_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) static struct clk_branch camss_csi3rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .halt_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .enable_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .name = "camss_csi3rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .parent_names = (const char *[]){ "csi3_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) static struct clk_branch camss_csi3pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .halt_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .enable_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .name = "camss_csi3pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .parent_names = (const char *[]){ "csi3_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) static struct clk_branch camss_ispif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .halt_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .enable_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .name = "camss_ispif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) static struct clk_branch fd_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .halt_reg = 0x3b68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .enable_reg = 0x3b68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .name = "fd_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .parent_names = (const char *[]){ "fd_core_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static struct clk_branch fd_core_uar_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .halt_reg = 0x3b6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .enable_reg = 0x3b6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .name = "fd_core_uar_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .parent_names = (const char *[]){ "fd_core_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) static struct clk_branch fd_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .halt_reg = 0x3ba74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .enable_reg = 0x3ba74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .name = "fd_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .parent_names = (const char *[]){ "ahb_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) static struct clk_hw *mmcc_msm8996_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) &gpll0_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) static struct gdsc mmagic_bimc_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .gdscr = 0x529c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .name = "mmagic_bimc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .flags = ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) static struct gdsc mmagic_video_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .gdscr = 0x119c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .gds_hw_ctrl = 0x120c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .name = "mmagic_video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .flags = VOTABLE | ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) static struct gdsc mmagic_mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .gdscr = 0x247c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .gds_hw_ctrl = 0x2480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .name = "mmagic_mdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .flags = VOTABLE | ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) static struct gdsc mmagic_camss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) .gdscr = 0x3c4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) .gds_hw_ctrl = 0x3c50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) .name = "mmagic_camss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .flags = VOTABLE | ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) static struct gdsc venus_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .gdscr = 0x1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .cxc_count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .name = "venus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .parent = &mmagic_video_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) static struct gdsc venus_core0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .gdscr = 0x1040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .cxcs = (unsigned int []){ 0x1048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .name = "venus_core0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .parent = &venus_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) static struct gdsc venus_core1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .gdscr = 0x1044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .cxcs = (unsigned int []){ 0x104c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .name = "venus_core1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .parent = &venus_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) static struct gdsc camss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .gdscr = 0x34a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) .cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .name = "camss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .parent = &mmagic_camss_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) static struct gdsc vfe0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .gdscr = 0x3664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .cxcs = (unsigned int []){ 0x36a8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .name = "vfe0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .parent = &camss_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static struct gdsc vfe1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .gdscr = 0x3674,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .cxcs = (unsigned int []){ 0x36ac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .name = "vfe1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .parent = &camss_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) static struct gdsc jpeg_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .gdscr = 0x35a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .cxc_count = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .name = "jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .parent = &camss_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) static struct gdsc cpp_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .gdscr = 0x36d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .cxcs = (unsigned int []){ 0x36b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .name = "cpp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .parent = &camss_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) static struct gdsc fd_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .gdscr = 0x3b64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) .name = "fd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .parent = &camss_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .gdscr = 0x2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .cxcs = (unsigned int []){ 0x2310, 0x231c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) .cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) .name = "mdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) .parent = &mmagic_mdss_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) static struct gdsc gpu_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .gdscr = 0x4034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .gds_hw_ctrl = 0x4038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .name = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) static struct gdsc gpu_gx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .gdscr = 0x4024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .clamp_io_ctrl = 0x4300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) .cxcs = (unsigned int []){ 0x4028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .name = "gpu_gx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .parent = &gpu_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .flags = CLAMP_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .supply = "vdd-gfx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) static struct clk_regmap *mmcc_msm8996_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) [MMPLL0_EARLY] = &mmpll0_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) [MMPLL0_PLL] = &mmpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) [MMPLL1_EARLY] = &mmpll1_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) [MMPLL1_PLL] = &mmpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) [MMPLL2_EARLY] = &mmpll2_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) [MMPLL2_PLL] = &mmpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) [MMPLL3_EARLY] = &mmpll3_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) [MMPLL3_PLL] = &mmpll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) [MMPLL4_EARLY] = &mmpll4_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) [MMPLL4_PLL] = &mmpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) [MMPLL5_EARLY] = &mmpll5_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) [MMPLL5_PLL] = &mmpll5.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) [MMPLL8_EARLY] = &mmpll8_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) [MMPLL8_PLL] = &mmpll8.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) [MMPLL9_EARLY] = &mmpll9_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) [MMPLL9_PLL] = &mmpll9.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) [AHB_CLK_SRC] = &ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) [AXI_CLK_SRC] = &axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) [MDP_CLK_SRC] = &mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) [CCI_CLK_SRC] = &cci_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) [CPP_CLK_SRC] = &cpp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) [VIDEO_CORE_CLK] = &video_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) [FD_CORE_CLK] = &fd_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) [FD_AHB_CLK] = &fd_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) static struct gdsc *mmcc_msm8996_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) [VENUS_GDSC] = &venus_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) [CAMSS_GDSC] = &camss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) [VFE0_GDSC] = &vfe0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) [VFE1_GDSC] = &vfe1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) [JPEG_GDSC] = &jpeg_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) [CPP_GDSC] = &cpp_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) [FD_GDSC] = &fd_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) [GPU_GDSC] = &gpu_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) [GPU_GX_GDSC] = &gpu_gx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) static const struct qcom_reset_map mmcc_msm8996_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) [MMAGICAHB_BCR] = { 0x5020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) [MMAGIC_CFG_BCR] = { 0x5050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) [MISC_BCR] = { 0x5010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) [BTO_BCR] = { 0x5030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) [MMAGICAXI_BCR] = { 0x5060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) [MMAGICMAXI_BCR] = { 0x5070 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) [DSA_BCR] = { 0x50a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) [MMAGIC_CAMSS_BCR] = { 0x3c40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) [THROTTLE_CAMSS_BCR] = { 0x3c30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) [SMMU_VFE_BCR] = { 0x3c00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) [SMMU_CPP_BCR] = { 0x3c10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) [SMMU_JPEG_BCR] = { 0x3c20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) [MMAGIC_MDSS_BCR] = { 0x2470 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) [THROTTLE_MDSS_BCR] = { 0x2460 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) [SMMU_ROT_BCR] = { 0x2440 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) [SMMU_MDP_BCR] = { 0x2450 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) [MMAGIC_VIDEO_BCR] = { 0x1190 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) [THROTTLE_VIDEO_BCR] = { 0x1180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) [SMMU_VIDEO_BCR] = { 0x1170 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) [MMAGIC_BIMC_BCR] = { 0x5290 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) [GPU_GX_BCR] = { 0x4020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) [GPU_BCR] = { 0x4030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) [GPU_AON_BCR] = { 0x4040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) [VMEM_BCR] = { 0x1200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) [MMSS_RBCPR_BCR] = { 0x4080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) [VIDEO_BCR] = { 0x1020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) [MDSS_BCR] = { 0x2300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) [CAMSS_TOP_BCR] = { 0x3480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) [CAMSS_AHB_BCR] = { 0x3488 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) [CAMSS_MICRO_BCR] = { 0x3490 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) [CAMSS_CCI_BCR] = { 0x3340 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) [CAMSS_PHY0_BCR] = { 0x3020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) [CAMSS_PHY1_BCR] = { 0x3050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) [CAMSS_PHY2_BCR] = { 0x3080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) [CAMSS_JPEG_BCR] = { 0x35a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) [CAMSS_VFE_BCR] = { 0x36a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) [CAMSS_VFE0_BCR] = { 0x3660 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) [CAMSS_VFE1_BCR] = { 0x3670 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) [CAMSS_CPP_BCR] = { 0x36d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) [CAMSS_CSI0_BCR] = { 0x30b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) [CAMSS_CSI1_BCR] = { 0x3120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) [CAMSS_CSI1RDI_BCR] = { 0x3140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [CAMSS_CSI1PIX_BCR] = { 0x3150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [CAMSS_CSI2_BCR] = { 0x3180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [CAMSS_CSI3_BCR] = { 0x31e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [CAMSS_CSI3RDI_BCR] = { 0x3200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [CAMSS_CSI3PIX_BCR] = { 0x3210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [CAMSS_ISPIF_BCR] = { 0x3220 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [FD_BCR] = { 0x3b60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [MMSS_SPDM_RM_BCR] = { 0x300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) static const struct regmap_config mmcc_msm8996_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) .max_register = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) static const struct qcom_cc_desc mmcc_msm8996_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .config = &mmcc_msm8996_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) .clks = mmcc_msm8996_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) .resets = mmcc_msm8996_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) .gdscs = mmcc_msm8996_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) .clk_hws = mmcc_msm8996_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) static const struct of_device_id mmcc_msm8996_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) { .compatible = "qcom,mmcc-msm8996" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) static int mmcc_msm8996_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /* Disable the AHB DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) regmap_update_bits(regmap, 0x5054, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static struct platform_driver mmcc_msm8996_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) .probe = mmcc_msm8996_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) .name = "mmcc-msm8996",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) .of_match_table = mmcc_msm8996_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) module_platform_driver(mmcc_msm8996_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) MODULE_ALIAS("platform:mmcc-msm8996");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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