^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_MMPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_EDPLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_MMPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_HDMIPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_EDPVCO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_GPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_DSI0PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_DSI0PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_MMPLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_MMPLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_DSI1PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_DSI1PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { P_GPLL0, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { P_HDMIPLL, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { P_DSI0PLL, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { P_DSI1PLL, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "dsi1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { P_MMPLL2, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "mmpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { P_MMPLL3, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { P_GPLL1, 4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { P_EDPLINK, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { P_HDMIPLL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { P_EDPVCO, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { P_DSI0PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { P_DSI1PLL, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char * const mmcc_xo_dsi_hdmi_edp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "edp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "edp_vco_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "dsi1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { P_EDPLINK, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { P_HDMIPLL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { P_DSI0PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { P_DSI1PLL, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "edp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "dsi1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { P_EDPLINK, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { P_HDMIPLL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { P_DSI0PLL_BYTE, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { P_DSI1PLL_BYTE, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "edp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "dsi0pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "dsi1pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct clk_pll mmpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .l_reg = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .m_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .n_reg = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .config_reg = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .mode_reg = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .status_reg = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct clk_regmap mmpll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .enable_reg = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .parent_names = (const char *[]){ "mmpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct clk_pll mmpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .l_reg = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .m_reg = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .n_reg = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .config_reg = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .mode_reg = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .status_reg = 0x005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct clk_regmap mmpll1_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .enable_reg = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .parent_names = (const char *[]){ "mmpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct clk_pll mmpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .l_reg = 0x4104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .m_reg = 0x4108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .n_reg = 0x410c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .config_reg = 0x4110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .mode_reg = 0x4100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .status_reg = 0x411c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "mmpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct clk_pll mmpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .l_reg = 0x0084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .m_reg = 0x0088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .n_reg = 0x008c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .config_reg = 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .mode_reg = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .status_reg = 0x009c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct clk_rcg2 mmss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .cmd_rcgr = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct freq_tbl ftbl_mmss_axi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) F( 19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) F( 37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) F( 50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) F( 75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) F(291750000, P_MMPLL1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) F(466800000, P_MMPLL1, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct clk_rcg2 mmss_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .cmd_rcgr = 0x5040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .freq_tbl = ftbl_mmss_axi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .name = "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct freq_tbl ftbl_ocmemnoc_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) F( 19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) F( 37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) F( 50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) F( 75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) F(291750000, P_MMPLL1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct clk_rcg2 ocmemnoc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .cmd_rcgr = 0x5090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .freq_tbl = ftbl_ocmemnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct clk_rcg2 csi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .cmd_rcgr = 0x3090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct clk_rcg2 csi1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .cmd_rcgr = 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct clk_rcg2 csi2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .cmd_rcgr = 0x3160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct clk_rcg2 csi3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .cmd_rcgr = 0x31c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) F(80000000, P_GPLL0, 7.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) F(109090000, P_GPLL0, 5.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) F(228570000, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) F(465000000, P_MMPLL3, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct clk_rcg2 vfe0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .cmd_rcgr = 0x3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static struct clk_rcg2 vfe1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .cmd_rcgr = 0x3620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct freq_tbl ftbl_mdss_mdp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) F(85710000, P_GPLL0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) F(133330000, P_MMPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) F(160000000, P_MMPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) F(228570000, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) F(240000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct clk_rcg2 mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .cmd_rcgr = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .freq_tbl = ftbl_mdss_mdp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .name = "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) F(228570000, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct clk_rcg2 jpeg0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .cmd_rcgr = 0x3500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct clk_rcg2 jpeg1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .cmd_rcgr = 0x3520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .name = "jpeg1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct clk_rcg2 jpeg2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .cmd_rcgr = 0x3540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = "jpeg2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct clk_rcg2 pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .cmd_rcgr = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .name = "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct clk_rcg2 pclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .cmd_rcgr = 0x2020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .name = "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) F(133330000, P_MMPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) F(465000000, P_MMPLL3, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct clk_rcg2 vcodec0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .cmd_rcgr = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .freq_tbl = ftbl_venus0_vcodec0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .name = "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static struct clk_rcg2 cci_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .cmd_rcgr = 0x3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .freq_tbl = ftbl_camss_cci_cci_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .name = "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) F(10000, P_XO, 16, 1, 120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) F(24000, P_XO, 16, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) F(6000000, P_GPLL0, 10, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) F(12000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) F(13000000, P_GPLL0, 4, 13, 150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct clk_rcg2 camss_gp0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .cmd_rcgr = 0x3420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .freq_tbl = ftbl_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct clk_rcg2 camss_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .cmd_rcgr = 0x3450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .freq_tbl = ftbl_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .name = "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) F(6000000, P_GPLL0, 10, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) F(8000000, P_GPLL0, 15, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) F(16000000, P_GPLL0, 12.5, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) F(32000000, P_MMPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) F(48000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) F(64000000, P_MMPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) F(66670000, P_GPLL0, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static struct clk_rcg2 mclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .cmd_rcgr = 0x3360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .name = "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static struct clk_rcg2 mclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .cmd_rcgr = 0x3390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .name = "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct clk_rcg2 mclk2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .cmd_rcgr = 0x33c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = "mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static struct clk_rcg2 mclk3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .cmd_rcgr = 0x33f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = "mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static struct clk_rcg2 csi0phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .cmd_rcgr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .name = "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static struct clk_rcg2 csi1phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .cmd_rcgr = 0x3030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .name = "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static struct clk_rcg2 csi2phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .cmd_rcgr = 0x3060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .name = "csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) F(465000000, P_MMPLL3, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static struct clk_rcg2 cpp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .cmd_rcgr = 0x3640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .freq_tbl = ftbl_camss_vfe_cpp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .name = "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static struct freq_tbl byte_freq_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { .src = P_DSI0PLL_BYTE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct clk_rcg2 byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .cmd_rcgr = 0x2120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .freq_tbl = byte_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static struct clk_rcg2 byte1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .cmd_rcgr = 0x2140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .freq_tbl = byte_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .name = "byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static struct clk_rcg2 edpaux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .cmd_rcgr = 0x20e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .freq_tbl = ftbl_mdss_edpaux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "edpaux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static struct freq_tbl ftbl_mdss_edplink_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) F(135000000, P_EDPLINK, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) F(270000000, P_EDPLINK, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static struct clk_rcg2 edplink_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .cmd_rcgr = 0x20c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .freq_tbl = ftbl_mdss_edplink_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .name = "edplink_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static struct freq_tbl edp_pixel_freq_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { .src = P_EDPVCO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static struct clk_rcg2 edppixel_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .cmd_rcgr = 0x20a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .parent_map = mmcc_xo_dsi_hdmi_edp_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .freq_tbl = edp_pixel_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .name = "edppixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .parent_names = mmcc_xo_dsi_hdmi_edp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .ops = &clk_edp_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct clk_rcg2 esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .cmd_rcgr = 0x2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .freq_tbl = ftbl_mdss_esc0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .name = "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static struct clk_rcg2 esc1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .cmd_rcgr = 0x2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .freq_tbl = ftbl_mdss_esc0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .name = "esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct freq_tbl extpclk_freq_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { .src = P_HDMIPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static struct clk_rcg2 extpclk_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .cmd_rcgr = 0x2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .freq_tbl = extpclk_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .name = "extpclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .ops = &clk_byte_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static struct clk_rcg2 hdmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .cmd_rcgr = 0x2100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .freq_tbl = ftbl_mdss_hdmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .name = "hdmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static struct freq_tbl ftbl_mdss_vsync_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static struct clk_rcg2 vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .cmd_rcgr = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .freq_tbl = ftbl_mdss_vsync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .name = "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static struct clk_branch camss_cci_cci_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .halt_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .enable_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .name = "camss_cci_cci_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static struct clk_branch camss_cci_cci_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .halt_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .enable_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = "camss_cci_cci_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static struct clk_branch camss_csi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .halt_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .enable_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .name = "camss_csi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static struct clk_branch camss_csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .halt_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .enable_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .name = "camss_csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static struct clk_branch camss_csi0phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .halt_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .enable_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .name = "camss_csi0phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static struct clk_branch camss_csi0pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .halt_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .enable_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .name = "camss_csi0pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static struct clk_branch camss_csi0rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .halt_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .enable_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .name = "camss_csi0rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static struct clk_branch camss_csi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .halt_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .enable_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .name = "camss_csi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static struct clk_branch camss_csi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .halt_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .enable_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .name = "camss_csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static struct clk_branch camss_csi1phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .halt_reg = 0x3134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .enable_reg = 0x3134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .name = "camss_csi1phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct clk_branch camss_csi1pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .halt_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .enable_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .name = "camss_csi1pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static struct clk_branch camss_csi1rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .halt_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .enable_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .name = "camss_csi1rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static struct clk_branch camss_csi2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .halt_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .enable_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .name = "camss_csi2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static struct clk_branch camss_csi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .halt_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .enable_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .name = "camss_csi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static struct clk_branch camss_csi2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .halt_reg = 0x3194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .enable_reg = 0x3194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .name = "camss_csi2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static struct clk_branch camss_csi2pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .halt_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .enable_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .name = "camss_csi2pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static struct clk_branch camss_csi2rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .halt_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .enable_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .name = "camss_csi2rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static struct clk_branch camss_csi3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .halt_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .enable_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .name = "camss_csi3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static struct clk_branch camss_csi3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .halt_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .enable_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .name = "camss_csi3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static struct clk_branch camss_csi3phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .halt_reg = 0x31f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .enable_reg = 0x31f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .name = "camss_csi3phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static struct clk_branch camss_csi3pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .halt_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .enable_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .name = "camss_csi3pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static struct clk_branch camss_csi3rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .halt_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .enable_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .name = "camss_csi3rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static struct clk_branch camss_csi_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .halt_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .enable_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .name = "camss_csi_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static struct clk_branch camss_csi_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .halt_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .enable_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .name = "camss_csi_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static struct clk_branch camss_gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .halt_reg = 0x3444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .enable_reg = 0x3444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .name = "camss_gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static struct clk_branch camss_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .halt_reg = 0x3474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .enable_reg = 0x3474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .name = "camss_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static struct clk_branch camss_ispif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .halt_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .enable_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .name = "camss_ispif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static struct clk_branch camss_jpeg_jpeg0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .halt_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .enable_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .name = "camss_jpeg_jpeg0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static struct clk_branch camss_jpeg_jpeg1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .halt_reg = 0x35ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .enable_reg = 0x35ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .name = "camss_jpeg_jpeg1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) "jpeg1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static struct clk_branch camss_jpeg_jpeg2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .halt_reg = 0x35b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .enable_reg = 0x35b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .name = "camss_jpeg_jpeg2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) "jpeg2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .halt_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .enable_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .name = "camss_jpeg_jpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static struct clk_branch camss_jpeg_jpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .halt_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .enable_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .name = "camss_jpeg_jpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .halt_reg = 0x35bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .enable_reg = 0x35bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .name = "camss_jpeg_jpeg_ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static struct clk_branch camss_mclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .halt_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .enable_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .name = "camss_mclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static struct clk_branch camss_mclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .halt_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .enable_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .name = "camss_mclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static struct clk_branch camss_mclk2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .halt_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .enable_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .name = "camss_mclk2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) "mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct clk_branch camss_mclk3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .halt_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .enable_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .name = "camss_mclk3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) "mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static struct clk_branch camss_micro_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .halt_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .enable_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .name = "camss_micro_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static struct clk_branch camss_phy0_csi0phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .halt_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .enable_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .name = "camss_phy0_csi0phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) static struct clk_branch camss_phy1_csi1phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .halt_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .enable_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .name = "camss_phy1_csi1phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static struct clk_branch camss_phy2_csi2phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .halt_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .enable_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .name = "camss_phy2_csi2phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) "csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static struct clk_branch camss_top_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .halt_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .enable_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .name = "camss_top_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static struct clk_branch camss_vfe_cpp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .halt_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .enable_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .name = "camss_vfe_cpp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static struct clk_branch camss_vfe_cpp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .halt_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .enable_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .name = "camss_vfe_cpp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static struct clk_branch camss_vfe_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .halt_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .enable_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .name = "camss_vfe_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static struct clk_branch camss_vfe_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .halt_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .enable_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .name = "camss_vfe_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static struct clk_branch camss_vfe_vfe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .halt_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .enable_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .name = "camss_vfe_vfe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static struct clk_branch camss_vfe_vfe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .halt_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .enable_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .name = "camss_vfe_vfe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .halt_reg = 0x36c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .enable_reg = 0x36c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .name = "camss_vfe_vfe_ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) static struct clk_branch mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .halt_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .enable_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .name = "mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static struct clk_branch mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .halt_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .enable_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .name = "mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static struct clk_branch mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .halt_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .enable_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .name = "mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static struct clk_branch mdss_byte1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .halt_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .enable_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .name = "mdss_byte1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) "byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static struct clk_branch mdss_edpaux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .halt_reg = 0x2334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .enable_reg = 0x2334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .name = "mdss_edpaux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) "edpaux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static struct clk_branch mdss_edplink_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .halt_reg = 0x2330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .enable_reg = 0x2330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .name = "mdss_edplink_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) "edplink_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static struct clk_branch mdss_edppixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .halt_reg = 0x232c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .enable_reg = 0x232c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .name = "mdss_edppixel_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) "edppixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static struct clk_branch mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .halt_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .enable_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .name = "mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static struct clk_branch mdss_esc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .halt_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .enable_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .name = "mdss_esc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static struct clk_branch mdss_extpclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .halt_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .enable_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .name = "mdss_extpclk_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) "extpclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static struct clk_branch mdss_hdmi_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .halt_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .enable_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .name = "mdss_hdmi_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static struct clk_branch mdss_hdmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .halt_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .enable_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .name = "mdss_hdmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "hdmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) static struct clk_branch mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .halt_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .enable_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .name = "mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static struct clk_branch mdss_mdp_lut_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .halt_reg = 0x2320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .enable_reg = 0x2320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .name = "mdss_mdp_lut_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) static struct clk_branch mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .halt_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .enable_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .name = "mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static struct clk_branch mdss_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .halt_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .enable_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .name = "mdss_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static struct clk_branch mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .halt_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .enable_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .name = "mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static struct clk_branch mmss_misc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .halt_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .enable_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .name = "mmss_misc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static struct clk_branch mmss_mmssnoc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .halt_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .enable_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .name = "mmss_mmssnoc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .halt_reg = 0x5028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .enable_reg = 0x5028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .name = "mmss_mmssnoc_bto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static struct clk_branch mmss_mmssnoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .halt_reg = 0x506c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .enable_reg = 0x506c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .name = "mmss_mmssnoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static struct clk_branch mmss_s0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .halt_reg = 0x5064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .enable_reg = 0x5064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .name = "mmss_s0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static struct clk_branch ocmemcx_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .halt_reg = 0x405c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .enable_reg = 0x405c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .name = "ocmemcx_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) static struct clk_branch ocmemcx_ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .halt_reg = 0x4058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .enable_reg = 0x4058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .name = "ocmemcx_ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static struct clk_branch oxili_ocmemgx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .halt_reg = 0x402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .enable_reg = 0x402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .name = "oxili_ocmemgx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static struct clk_branch ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .halt_reg = 0x50b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .enable_reg = 0x50b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .name = "ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) static struct clk_branch oxili_gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .halt_reg = 0x4028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .enable_reg = 0x4028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .name = "oxili_gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static struct clk_branch oxilicx_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .halt_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .enable_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .name = "oxilicx_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static struct clk_branch oxilicx_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .halt_reg = 0x4038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .enable_reg = 0x4038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .name = "oxilicx_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static struct clk_branch venus0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .halt_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .enable_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .name = "venus0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static struct clk_branch venus0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .halt_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .enable_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .name = "venus0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) static struct clk_branch venus0_ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .halt_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .enable_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .name = "venus0_ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static struct clk_branch venus0_vcodec0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .halt_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .enable_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .name = "venus0_vcodec0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) static const struct pll_config mmpll1_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .l = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .m = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .n = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .vco_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .vco_mask = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .pre_div_mask = 0x7 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .post_div_mask = 0x3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .mn_ena_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static struct pll_config mmpll3_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .l = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .m = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .n = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .vco_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .vco_mask = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .pre_div_mask = 0x7 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .post_div_mask = 0x3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .mn_ena_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .aux_output_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static struct gdsc venus0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .gdscr = 0x1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .cxcs = (unsigned int []){ 0x1028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .resets = (unsigned int []){ VENUS0_RESET },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .reset_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .name = "venus0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .gdscr = 0x2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .cxcs = (unsigned int []){ 0x231c, 0x2320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .name = "mdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) static struct gdsc camss_jpeg_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .gdscr = 0x35a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .cxc_count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .name = "camss_jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) static struct gdsc camss_vfe_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .gdscr = 0x36a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .cxc_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .name = "camss_vfe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static struct gdsc oxili_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .gdscr = 0x4024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .cxcs = (unsigned int []){ 0x4028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .name = "oxili",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static struct gdsc oxilicx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .gdscr = 0x4034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .name = "oxilicx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .parent = &oxili_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) static struct clk_regmap *mmcc_msm8974_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) [MMPLL0] = &mmpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) [MMPLL0_VOTE] = &mmpll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) [MMPLL1] = &mmpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) [MMPLL1_VOTE] = &mmpll1_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) [MMPLL2] = &mmpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) [MMPLL3] = &mmpll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) [MDP_CLK_SRC] = &mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) [CCI_CLK_SRC] = &cci_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) [CPP_CLK_SRC] = &cpp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static const struct qcom_reset_map mmcc_msm8974_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) [SPDM_RESET] = { 0x0200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) [SPDM_RM_RESET] = { 0x0300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) [VENUS0_RESET] = { 0x1020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) [MDSS_RESET] = { 0x2300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) [CAMSS_PHY0_RESET] = { 0x3020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) [CAMSS_PHY1_RESET] = { 0x3050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) [CAMSS_PHY2_RESET] = { 0x3080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) [CAMSS_CSI0_RESET] = { 0x30b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) [CAMSS_CSI1_RESET] = { 0x3120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) [CAMSS_CSI1PHY_RESET] = { 0x3130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) [CAMSS_CSI1RDI_RESET] = { 0x3140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) [CAMSS_CSI1PIX_RESET] = { 0x3150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) [CAMSS_CSI2_RESET] = { 0x3180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) [CAMSS_CSI2PHY_RESET] = { 0x3190 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) [CAMSS_CSI3_RESET] = { 0x31e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) [CAMSS_CSI3RDI_RESET] = { 0x3200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) [CAMSS_CSI3PIX_RESET] = { 0x3210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) [CAMSS_ISPIF_RESET] = { 0x3220 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) [CAMSS_CCI_RESET] = { 0x3340 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) [CAMSS_MCLK0_RESET] = { 0x3380 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) [CAMSS_MCLK1_RESET] = { 0x33b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) [CAMSS_MCLK2_RESET] = { 0x33e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) [CAMSS_MCLK3_RESET] = { 0x3410 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) [CAMSS_GP0_RESET] = { 0x3440 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) [CAMSS_GP1_RESET] = { 0x3470 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) [CAMSS_TOP_RESET] = { 0x3480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) [CAMSS_MICRO_RESET] = { 0x3490 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) [CAMSS_JPEG_RESET] = { 0x35a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) [CAMSS_VFE_RESET] = { 0x36a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) [OXILI_RESET] = { 0x4020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) [OXILICX_RESET] = { 0x4030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) [OCMEMCX_RESET] = { 0x4050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) [MMSS_RBCRP_RESET] = { 0x4080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) [MMSSNOCAHB_RESET] = { 0x5020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) [MMSSNOCAXI_RESET] = { 0x5060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) [OCMEMNOC_RESET] = { 0x50b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static struct gdsc *mmcc_msm8974_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) [VENUS0_GDSC] = &venus0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) [OXILI_GDSC] = &oxili_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) [OXILICX_GDSC] = &oxilicx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) static const struct regmap_config mmcc_msm8974_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .max_register = 0x5104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) static const struct qcom_cc_desc mmcc_msm8974_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .config = &mmcc_msm8974_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .clks = mmcc_msm8974_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .resets = mmcc_msm8974_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .gdscs = mmcc_msm8974_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static const struct of_device_id mmcc_msm8974_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) { .compatible = "qcom,mmcc-msm8974" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static int mmcc_msm8974_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) static struct platform_driver mmcc_msm8974_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .probe = mmcc_msm8974_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .name = "mmcc-msm8974",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .of_match_table = mmcc_msm8974_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) module_platform_driver(mmcc_msm8974_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) MODULE_ALIAS("platform:mmcc-msm8974");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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