^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_PXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_PLL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_PLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_PLL15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_HDMI_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_DSI1_PLL_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_DSI2_PLL_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_DSI1_PLL_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_DSI2_PLL_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { P_PLL8, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { P_PLL2, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char * const mmcc_pxo_pll8_pll2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { P_PLL8, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { P_PLL2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { P_PLL3, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char * const mmcc_pxo_pll8_pll2_pll15[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "pll15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { P_PLL8, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { P_PLL2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { P_PLL15, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const char * const mmcc_pxo_pll8_pll2_pll3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { P_DSI2_PLL_DSICLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { P_DSI1_PLL_DSICLK, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char * const mmcc_pxo_dsi2_dsi1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "dsi2pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "dsi1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { P_DSI1_PLL_BYTECLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { P_DSI2_PLL_BYTECLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char * const mmcc_pxo_dsi1_dsi2_byte[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "dsi1pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "dsi2pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct clk_pll pll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .l_reg = 0x320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .m_reg = 0x324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .n_reg = 0x328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .config_reg = 0x32c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .mode_reg = 0x31c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .status_reg = 0x334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct clk_pll pll15 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .l_reg = 0x33c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .m_reg = 0x340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .n_reg = 0x344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .config_reg = 0x348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mode_reg = 0x338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .status_reg = 0x350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "pll15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct pll_config pll15_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .l = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .m = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .n = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .vco_val = 0x2 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .vco_mask = 0x3 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .pre_div_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .post_div_mask = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .mn_ena_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .main_output_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct freq_tbl clk_tbl_cam[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 6000000, P_PLL8, 4, 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 8000000, P_PLL8, 4, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 12000000, P_PLL8, 4, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 19200000, P_PLL8, 4, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 32000000, P_PLL8, 4, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 64000000, P_PLL8, 3, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 96000000, P_PLL8, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 128000000, P_PLL8, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct clk_rcg camclk0_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .ns_reg = 0x0148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .md_reg = 0x0144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .mnctr_reset_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .reset_in_cc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .freq_tbl = clk_tbl_cam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .enable_reg = 0x0140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "camclk0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct clk_branch camclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .enable_reg = 0x0140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "camclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .parent_names = (const char *[]){ "camclk0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct clk_rcg camclk1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .ns_reg = 0x015c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .md_reg = 0x0158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .mnctr_reset_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .reset_in_cc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .freq_tbl = clk_tbl_cam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .enable_reg = 0x0154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .name = "camclk1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct clk_branch camclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .enable_reg = 0x0154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "camclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .parent_names = (const char *[]){ "camclk1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct clk_rcg camclk2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .ns_reg = 0x0228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .md_reg = 0x0224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .mnctr_reset_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .reset_in_cc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .freq_tbl = clk_tbl_cam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .enable_reg = 0x0220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "camclk2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct clk_branch camclk2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .enable_reg = 0x0220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "camclk2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .parent_names = (const char *[]){ "camclk2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct freq_tbl clk_tbl_csi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 85330000, P_PLL8, 1, 2, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 177780000, P_PLL2, 1, 2, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct clk_rcg csi0_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .ns_reg = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .md_reg = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .freq_tbl = clk_tbl_csi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .enable_reg = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "csi0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct clk_branch csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .enable_reg = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .parent_names = (const char *[]){ "csi0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct clk_branch csi0_phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .enable_reg = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .parent_names = (const char *[]){ "csi0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "csi0_phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct clk_rcg csi1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .ns_reg = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .md_reg = 0x0028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .freq_tbl = clk_tbl_csi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .enable_reg = 0x0024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .name = "csi1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct clk_branch csi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .enable_reg = 0x0024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .parent_names = (const char *[]){ "csi1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct clk_branch csi1_phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .enable_reg = 0x0024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .parent_names = (const char *[]){ "csi1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = "csi1_phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct clk_rcg csi2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .ns_reg = 0x0234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .md_reg = 0x022c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .freq_tbl = clk_tbl_csi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .enable_reg = 0x022c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .name = "csi2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct clk_branch csi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .halt_bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .enable_reg = 0x022c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .parent_names = (const char *[]){ "csi2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "csi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct clk_branch csi2_phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .halt_bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .enable_reg = 0x022c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .parent_names = (const char *[]){ "csi2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = "csi2_phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct clk_pix_rdi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 s_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 s_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 s2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 s2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define to_clk_pix_rdi(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * These clocks select three inputs via two muxes. One mux selects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * between csi0 and csi1 and the second mux selects between that mux's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * output and csi2. The source and destination selections for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * mux must be clocking for the switch to succeed so just turn on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * all three sources because it's easier than figuring out what source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * needs to be on at what time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) for (i = 0; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = clk_prepare_enable(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (index == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val = rdi->s2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * Wait at least 6 cycles of slowest clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * for the glitch-free MUX to fully switch sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (index == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val = rdi->s_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Wait at least 6 cycles of slowest clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * for the glitch-free MUX to fully switch sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i--; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_disable_unprepare(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static u8 pix_rdi_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (val & rdi->s2_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (val & rdi->s_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct clk_ops clk_ops_pix_rdi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .set_parent = pix_rdi_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .get_parent = pix_rdi_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const char * const pix_rdi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "csi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static struct clk_pix_rdi csi_pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .s_reg = 0x0058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .s_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .s2_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .s2_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .enable_reg = 0x0058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = "csi_pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .parent_names = pix_rdi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .ops = &clk_ops_pix_rdi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static struct clk_pix_rdi csi_pix1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .s_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .s_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .s2_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .s2_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .enable_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "csi_pix1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .parent_names = pix_rdi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .ops = &clk_ops_pix_rdi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct clk_pix_rdi csi_rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .s_reg = 0x0058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .s_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .s2_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .s2_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .enable_reg = 0x0058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .name = "csi_rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .parent_names = pix_rdi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .ops = &clk_ops_pix_rdi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static struct clk_pix_rdi csi_rdi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .s_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .s_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .s2_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .s2_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .enable_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .name = "csi_rdi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .parent_names = pix_rdi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .ops = &clk_ops_pix_rdi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static struct clk_pix_rdi csi_rdi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .s_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .s_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .s2_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .s2_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .enable_reg = 0x0238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .name = "csi_rdi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .parent_names = pix_rdi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .ops = &clk_ops_pix_rdi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct freq_tbl clk_tbl_csiphytimer[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { 85330000, P_PLL8, 1, 2, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { 177780000, P_PLL2, 1, 2, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static struct clk_rcg csiphytimer_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .ns_reg = 0x0168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .md_reg = 0x0164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .mnctr_reset_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .reset_in_cc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .freq_tbl = clk_tbl_csiphytimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .enable_reg = 0x0160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = "csiphytimer_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const char * const csixphy_timer_src[] = { "csiphytimer_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static struct clk_branch csiphy0_timer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .enable_reg = 0x0160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .parent_names = csixphy_timer_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .name = "csiphy0_timer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static struct clk_branch csiphy1_timer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .enable_reg = 0x0160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .parent_names = csixphy_timer_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "csiphy1_timer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static struct clk_branch csiphy2_timer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .halt_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .enable_reg = 0x0160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .parent_names = csixphy_timer_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .name = "csiphy2_timer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static struct freq_tbl clk_tbl_gfx2d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) F_MN( 27000000, P_PXO, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) F_MN( 48000000, P_PLL8, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) F_MN( 54857000, P_PLL8, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) F_MN( 64000000, P_PLL8, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) F_MN( 76800000, P_PLL8, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) F_MN( 96000000, P_PLL8, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) F_MN(128000000, P_PLL8, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) F_MN(145455000, P_PLL2, 2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) F_MN(160000000, P_PLL2, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) F_MN(177778000, P_PLL2, 2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) F_MN(200000000, P_PLL2, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) F_MN(228571000, P_PLL2, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static struct clk_dyn_rcg gfx2d0_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .ns_reg[0] = 0x0070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .ns_reg[1] = 0x0070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .md_reg[0] = 0x0064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .md_reg[1] = 0x0068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .bank_reg = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .mnctr_reset_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .mnctr_mode_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .n_val_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .mnctr_reset_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .src_sel_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .mux_sel_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .freq_tbl = clk_tbl_gfx2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .enable_reg = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .name = "gfx2d0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static struct clk_branch gfx2d0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .halt_reg = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .enable_reg = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .name = "gfx2d0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .parent_names = (const char *[]){ "gfx2d0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static struct clk_dyn_rcg gfx2d1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .ns_reg[0] = 0x007c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .ns_reg[1] = 0x007c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .md_reg[0] = 0x0078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .md_reg[1] = 0x006c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .bank_reg = 0x0074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .mnctr_reset_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .mnctr_mode_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .n_val_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .mnctr_reset_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .src_sel_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .mux_sel_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .freq_tbl = clk_tbl_gfx2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .enable_reg = 0x0074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .name = "gfx2d1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static struct clk_branch gfx2d1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .halt_reg = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .enable_reg = 0x0074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .name = "gfx2d1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .parent_names = (const char *[]){ "gfx2d1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct freq_tbl clk_tbl_gfx3d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) F_MN( 27000000, P_PXO, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) F_MN( 48000000, P_PLL8, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) F_MN( 54857000, P_PLL8, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) F_MN( 64000000, P_PLL8, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) F_MN( 76800000, P_PLL8, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) F_MN( 96000000, P_PLL8, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) F_MN(128000000, P_PLL8, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) F_MN(145455000, P_PLL2, 2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) F_MN(160000000, P_PLL2, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) F_MN(177778000, P_PLL2, 2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) F_MN(200000000, P_PLL2, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) F_MN(228571000, P_PLL2, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) F_MN(266667000, P_PLL2, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) F_MN(300000000, P_PLL3, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) F_MN(320000000, P_PLL2, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) F_MN(400000000, P_PLL2, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct freq_tbl clk_tbl_gfx3d_8064[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) F_MN( 27000000, P_PXO, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) F_MN( 48000000, P_PLL8, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) F_MN( 54857000, P_PLL8, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) F_MN( 64000000, P_PLL8, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) F_MN( 76800000, P_PLL8, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) F_MN( 96000000, P_PLL8, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) F_MN(128000000, P_PLL8, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) F_MN(145455000, P_PLL2, 2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) F_MN(160000000, P_PLL2, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) F_MN(177778000, P_PLL2, 2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) F_MN(192000000, P_PLL8, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) F_MN(200000000, P_PLL2, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) F_MN(228571000, P_PLL2, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) F_MN(266667000, P_PLL2, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) F_MN(320000000, P_PLL2, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) F_MN(400000000, P_PLL2, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) F_MN(450000000, P_PLL15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static struct clk_dyn_rcg gfx3d_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .ns_reg[0] = 0x008c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .ns_reg[1] = 0x008c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .md_reg[0] = 0x0084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .md_reg[1] = 0x0088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .bank_reg = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .mnctr_reset_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .mnctr_mode_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .n_val_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .mnctr_reset_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .n_val_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .src_sel_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .mux_sel_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .freq_tbl = clk_tbl_gfx3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .enable_reg = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .name = "gfx3d_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .parent_names = mmcc_pxo_pll8_pll2_pll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const struct clk_init_data gfx3d_8064_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .name = "gfx3d_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .parent_names = mmcc_pxo_pll8_pll2_pll15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static struct clk_branch gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .halt_reg = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .enable_reg = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .name = "gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .parent_names = (const char *[]){ "gfx3d_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static struct freq_tbl clk_tbl_vcap[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) F_MN( 27000000, P_PXO, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) F_MN( 54860000, P_PLL8, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) F_MN( 64000000, P_PLL8, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) F_MN( 76800000, P_PLL8, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) F_MN(128000000, P_PLL8, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) F_MN(160000000, P_PLL2, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) F_MN(200000000, P_PLL2, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static struct clk_dyn_rcg vcap_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .ns_reg[0] = 0x021c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .ns_reg[1] = 0x021c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .md_reg[0] = 0x01ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .md_reg[1] = 0x0218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .bank_reg = 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .mnctr_reset_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .mnctr_mode_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .n_val_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .mnctr_reset_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .n_val_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .m_val_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .src_sel_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .mux_sel_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .freq_tbl = clk_tbl_vcap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .enable_reg = 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .name = "vcap_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static struct clk_branch vcap_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .halt_reg = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .enable_reg = 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .name = "vcap_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .parent_names = (const char *[]){ "vcap_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static struct clk_branch vcap_npl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .halt_reg = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .halt_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .enable_reg = 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .name = "vcap_npl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .parent_names = (const char *[]){ "vcap_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static struct freq_tbl clk_tbl_ijpeg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) { 36570000, P_PLL8, 1, 2, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) { 54860000, P_PLL8, 7, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) { 96000000, P_PLL8, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) { 109710000, P_PLL8, 1, 2, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) { 128000000, P_PLL8, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) { 153600000, P_PLL8, 1, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) { 200000000, P_PLL2, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) { 228571000, P_PLL2, 1, 2, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) { 266667000, P_PLL2, 1, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) { 320000000, P_PLL2, 1, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static struct clk_rcg ijpeg_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .ns_reg = 0x00a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .md_reg = 0x009c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .freq_tbl = clk_tbl_ijpeg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .enable_reg = 0x0098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .name = "ijpeg_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static struct clk_branch ijpeg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .halt_reg = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .enable_reg = 0x0098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .name = "ijpeg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .parent_names = (const char *[]){ "ijpeg_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static struct freq_tbl clk_tbl_jpegd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) { 64000000, P_PLL8, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) { 76800000, P_PLL8, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) { 96000000, P_PLL8, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) { 160000000, P_PLL2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) { 200000000, P_PLL2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static struct clk_rcg jpegd_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .ns_reg = 0x00ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .freq_tbl = clk_tbl_jpegd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .enable_reg = 0x00a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .name = "jpegd_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static struct clk_branch jpegd_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .halt_reg = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .enable_reg = 0x00a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .name = "jpegd_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .parent_names = (const char *[]){ "jpegd_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static struct freq_tbl clk_tbl_mdp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) { 9600000, P_PLL8, 1, 1, 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) { 13710000, P_PLL8, 1, 1, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) { 29540000, P_PLL8, 1, 1, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) { 34910000, P_PLL8, 1, 1, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) { 38400000, P_PLL8, 1, 1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) { 59080000, P_PLL8, 1, 2, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) { 76800000, P_PLL8, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) { 85330000, P_PLL8, 1, 2, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) { 96000000, P_PLL8, 1, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) { 128000000, P_PLL8, 1, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) { 160000000, P_PLL2, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) { 177780000, P_PLL2, 1, 2, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) { 200000000, P_PLL2, 1, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) { 228571000, P_PLL2, 1, 2, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) { 266667000, P_PLL2, 1, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static struct clk_dyn_rcg mdp_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .ns_reg[0] = 0x00d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .ns_reg[1] = 0x00d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .md_reg[0] = 0x00c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .md_reg[1] = 0x00c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .bank_reg = 0x00c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .mnctr_reset_bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .mnctr_mode_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .n_val_shift = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .mnctr_reset_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .n_val_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .src_sel_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .mux_sel_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .freq_tbl = clk_tbl_mdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .enable_reg = 0x00c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .name = "mdp_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static struct clk_branch mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .halt_reg = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .enable_reg = 0x00c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .name = "mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .parent_names = (const char *[]){ "mdp_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static struct clk_branch mdp_lut_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .enable_reg = 0x016c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .parent_names = (const char *[]){ "mdp_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .name = "mdp_lut_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static struct clk_branch mdp_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .enable_reg = 0x0058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .name = "mdp_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .ops = &clk_branch_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static struct freq_tbl clk_tbl_rot[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { 27000000, P_PXO, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { 29540000, P_PLL8, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { 32000000, P_PLL8, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { 38400000, P_PLL8, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { 48000000, P_PLL8, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) { 54860000, P_PLL8, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) { 64000000, P_PLL8, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) { 76800000, P_PLL8, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) { 96000000, P_PLL8, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) { 100000000, P_PLL2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) { 114290000, P_PLL2, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) { 133330000, P_PLL2, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) { 160000000, P_PLL2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) { 200000000, P_PLL2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static struct clk_dyn_rcg rot_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .ns_reg[0] = 0x00e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .ns_reg[1] = 0x00e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .bank_reg = 0x00e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .pre_div_shift = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .pre_div_shift = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .src_sel_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .src_sel_shift = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .mux_sel_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .freq_tbl = clk_tbl_rot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .enable_reg = 0x00e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .name = "rot_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static struct clk_branch rot_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .halt_reg = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .enable_reg = 0x00e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .name = "rot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .parent_names = (const char *[]){ "rot_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static const struct parent_map mmcc_pxo_hdmi_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) { P_HDMI_PLL, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static const char * const mmcc_pxo_hdmi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) "hdmi_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static struct freq_tbl clk_tbl_tv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) { .src = P_HDMI_PLL, .pre_div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static struct clk_rcg tv_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .ns_reg = 0x00f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .md_reg = 0x00f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .parent_map = mmcc_pxo_hdmi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .freq_tbl = clk_tbl_tv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .enable_reg = 0x00ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .name = "tv_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .parent_names = mmcc_pxo_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .ops = &clk_rcg_bypass_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static const char * const tv_src_name[] = { "tv_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static struct clk_branch tv_enc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .halt_reg = 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .enable_reg = 0x00ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .parent_names = tv_src_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .name = "tv_enc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static struct clk_branch tv_dac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .halt_reg = 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .enable_reg = 0x00ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .parent_names = tv_src_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .name = "tv_dac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static struct clk_branch mdp_tv_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .halt_reg = 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .enable_reg = 0x00ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .parent_names = tv_src_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .name = "mdp_tv_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static struct clk_branch hdmi_tv_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .halt_reg = 0x01d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .enable_reg = 0x00ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .parent_names = tv_src_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .name = "hdmi_tv_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static struct clk_branch rgb_tv_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .halt_reg = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .enable_reg = 0x0124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .parent_names = tv_src_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .name = "rgb_tv_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static struct clk_branch npl_tv_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .halt_reg = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .enable_reg = 0x0124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .parent_names = tv_src_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .name = "npl_tv_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static struct clk_branch hdmi_app_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .halt_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .enable_reg = 0x005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .name = "hdmi_app_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static struct freq_tbl clk_tbl_vcodec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) F_MN( 27000000, P_PXO, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) F_MN( 32000000, P_PLL8, 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) F_MN( 48000000, P_PLL8, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) F_MN( 54860000, P_PLL8, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) F_MN( 96000000, P_PLL8, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) F_MN(133330000, P_PLL2, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) F_MN(200000000, P_PLL2, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) F_MN(228570000, P_PLL2, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) F_MN(266670000, P_PLL2, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static struct clk_dyn_rcg vcodec_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .ns_reg[0] = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .ns_reg[1] = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .md_reg[0] = 0x00fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .md_reg[1] = 0x0128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .bank_reg = 0x00f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .mnctr_reset_bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .n_val_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .mnctr_en_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .mnctr_reset_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .mnctr_mode_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .n_val_shift = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .src_sel_shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .mux_sel_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .freq_tbl = clk_tbl_vcodec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .enable_reg = 0x00f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .name = "vcodec_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static struct clk_branch vcodec_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .halt_reg = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .halt_bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .enable_reg = 0x00f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .name = "vcodec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .parent_names = (const char *[]){ "vcodec_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static struct freq_tbl clk_tbl_vpe[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) { 27000000, P_PXO, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) { 34909000, P_PLL8, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) { 38400000, P_PLL8, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) { 64000000, P_PLL8, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) { 76800000, P_PLL8, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) { 96000000, P_PLL8, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) { 100000000, P_PLL2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) { 160000000, P_PLL2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static struct clk_rcg vpe_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .ns_reg = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .freq_tbl = clk_tbl_vpe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .enable_reg = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .name = "vpe_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static struct clk_branch vpe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .halt_reg = 0x01c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .halt_bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .enable_reg = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .name = "vpe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .parent_names = (const char *[]){ "vpe_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static struct freq_tbl clk_tbl_vfe[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) { 13960000, P_PLL8, 1, 2, 55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) { 36570000, P_PLL8, 1, 2, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) { 38400000, P_PLL8, 2, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) { 45180000, P_PLL8, 1, 2, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) { 48000000, P_PLL8, 2, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) { 54860000, P_PLL8, 1, 1, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) { 76800000, P_PLL8, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) { 96000000, P_PLL8, 2, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) { 109710000, P_PLL8, 1, 2, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) { 128000000, P_PLL8, 1, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) { 153600000, P_PLL8, 1, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) { 200000000, P_PLL2, 2, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) { 228570000, P_PLL2, 1, 2, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) { 266667000, P_PLL2, 1, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) { 320000000, P_PLL2, 1, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static struct clk_rcg vfe_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .ns_reg = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .pre_div_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .pre_div_width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .parent_map = mmcc_pxo_pll8_pll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .freq_tbl = clk_tbl_vfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .enable_reg = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .name = "vfe_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .parent_names = mmcc_pxo_pll8_pll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static struct clk_branch vfe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .enable_reg = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .name = "vfe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .parent_names = (const char *[]){ "vfe_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static struct clk_branch vfe_csi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .enable_reg = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .parent_names = (const char *[]){ "vfe_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .name = "vfe_csi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static struct clk_branch gmem_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .enable_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .enable_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .name = "gmem_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static struct clk_branch ijpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .hwcg_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .hwcg_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .enable_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .name = "ijpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static struct clk_branch mmss_imem_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .hwcg_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .hwcg_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .enable_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .name = "mmss_imem_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static struct clk_branch jpegd_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .enable_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .name = "jpegd_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static struct clk_branch vcodec_axi_b_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .hwcg_reg = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .hwcg_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .halt_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .enable_reg = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .enable_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .name = "vcodec_axi_b_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static struct clk_branch vcodec_axi_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .hwcg_reg = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .hwcg_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .enable_reg = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .name = "vcodec_axi_a_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static struct clk_branch vcodec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .hwcg_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .hwcg_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .enable_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .name = "vcodec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static struct clk_branch vfe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .enable_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .name = "vfe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static struct clk_branch mdp_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .hwcg_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .hwcg_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .enable_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .enable_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .name = "mdp_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static struct clk_branch rot_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .hwcg_reg = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .hwcg_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .enable_reg = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .enable_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .name = "rot_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static struct clk_branch vcap_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .halt_reg = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .hwcg_reg = 0x0244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .hwcg_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .enable_reg = 0x0244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .name = "vcap_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct clk_branch vpe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .hwcg_reg = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .hwcg_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .enable_reg = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .name = "vpe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static struct clk_branch gfx3d_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .hwcg_reg = 0x0244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .hwcg_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .halt_reg = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .halt_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .enable_reg = 0x0244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .name = "gfx3d_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) static struct clk_branch amp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .enable_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .name = "amp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static struct clk_branch csi_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .name = "csi_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static struct clk_branch dsi_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .name = "dsi_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static struct clk_branch dsi_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .hwcg_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .name = "dsi_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static struct clk_branch dsi2_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .halt_reg = 0x01d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .name = "dsi2_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static struct clk_branch dsi2_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .hwcg_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .name = "dsi2_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static struct clk_rcg dsi1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .ns_reg = 0x0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .md_reg = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .parent_map = mmcc_pxo_dsi2_dsi1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .enable_reg = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .name = "dsi1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .parent_names = mmcc_pxo_dsi2_dsi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .ops = &clk_rcg_bypass2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) static struct clk_branch dsi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .halt_reg = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .enable_reg = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .name = "dsi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .parent_names = (const char *[]){ "dsi1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static struct clk_rcg dsi2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .ns_reg = 0x012c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .md_reg = 0x00a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .pre_div_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .parent_map = mmcc_pxo_dsi2_dsi1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .enable_reg = 0x003c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .name = "dsi2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .parent_names = mmcc_pxo_dsi2_dsi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .ops = &clk_rcg_bypass2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) static struct clk_branch dsi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .halt_reg = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .enable_reg = 0x003c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .name = "dsi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .parent_names = (const char *[]){ "dsi2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) static struct clk_rcg dsi1_byte_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .ns_reg = 0x00b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .enable_reg = 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .name = "dsi1_byte_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .parent_names = mmcc_pxo_dsi1_dsi2_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .ops = &clk_rcg_bypass2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static struct clk_branch dsi1_byte_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .enable_reg = 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .name = "dsi1_byte_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .parent_names = (const char *[]){ "dsi1_byte_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static struct clk_rcg dsi2_byte_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .ns_reg = 0x012c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .enable_reg = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .name = "dsi2_byte_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .parent_names = mmcc_pxo_dsi1_dsi2_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .ops = &clk_rcg_bypass2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static struct clk_branch dsi2_byte_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .halt_reg = 0x01cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .enable_reg = 0x00b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .name = "dsi2_byte_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .parent_names = (const char *[]){ "dsi2_byte_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static struct clk_rcg dsi1_esc_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .ns_reg = 0x0011c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .enable_reg = 0x00cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .name = "dsi1_esc_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .parent_names = mmcc_pxo_dsi1_dsi2_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .ops = &clk_rcg_esc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) static struct clk_branch dsi1_esc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .enable_reg = 0x00cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .name = "dsi1_esc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .parent_names = (const char *[]){ "dsi1_esc_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static struct clk_rcg dsi2_esc_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .ns_reg = 0x0150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .enable_reg = 0x013c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .name = "dsi2_esc_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .parent_names = mmcc_pxo_dsi1_dsi2_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .ops = &clk_rcg_esc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static struct clk_branch dsi2_esc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .halt_reg = 0x01e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .enable_reg = 0x013c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .name = "dsi2_esc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .parent_names = (const char *[]){ "dsi2_esc_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) static struct clk_rcg dsi1_pixel_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .ns_reg = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .md_reg = 0x0134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .parent_map = mmcc_pxo_dsi2_dsi1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .enable_reg = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .name = "dsi1_pixel_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .parent_names = mmcc_pxo_dsi2_dsi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .ops = &clk_rcg_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static struct clk_branch dsi1_pixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .halt_reg = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .enable_reg = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .name = "mdp_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .parent_names = (const char *[]){ "dsi1_pixel_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static struct clk_rcg dsi2_pixel_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .ns_reg = 0x00e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .md_reg = 0x00b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .mnctr_en_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .mnctr_mode_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .pre_div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .parent_map = mmcc_pxo_dsi2_dsi1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .enable_reg = 0x0094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .name = "dsi2_pixel_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .parent_names = mmcc_pxo_dsi2_dsi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .ops = &clk_rcg_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) static struct clk_branch dsi2_pixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .halt_reg = 0x01d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .enable_reg = 0x0094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .name = "mdp_pclk2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .parent_names = (const char *[]){ "dsi2_pixel_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static struct clk_branch gfx2d0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .hwcg_bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .name = "gfx2d0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static struct clk_branch gfx2d1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .hwcg_bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .name = "gfx2d1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) static struct clk_branch gfx3d_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .hwcg_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .name = "gfx3d_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static struct clk_branch hdmi_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .hwcg_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .name = "hdmi_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) static struct clk_branch hdmi_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .hwcg_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .name = "hdmi_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) static struct clk_branch ijpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .name = "ijpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static struct clk_branch mmss_imem_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .hwcg_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .name = "mmss_imem_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static struct clk_branch jpegd_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .name = "jpegd_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) static struct clk_branch mdp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .name = "mdp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) static struct clk_branch rot_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .name = "rot_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static struct clk_branch smmu_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .hwcg_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .hwcg_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .name = "smmu_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static struct clk_branch tv_enc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .name = "tv_enc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static struct clk_branch vcap_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .halt_reg = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .enable_reg = 0x0248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .name = "vcap_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) static struct clk_branch vcodec_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .hwcg_reg = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .hwcg_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .name = "vcodec_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) static struct clk_branch vfe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .name = "vfe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static struct clk_branch vpe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .halt_reg = 0x01dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .enable_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .name = "vpe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) static struct clk_regmap *mmcc_msm8960_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) [AMP_AHB_CLK] = &_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) [ROT_AXI_CLK] = &rot_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) [CSI0_SRC] = &csi0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) [CSI0_CLK] = &csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) [CSI1_SRC] = &csi1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) [CSI1_CLK] = &csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) [CSI2_SRC] = &csi2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) [CSI2_CLK] = &csi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) [DSI_SRC] = &dsi1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) [DSI_CLK] = &dsi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) [CSI_PIX_CLK] = &csi_pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) [GFX2D0_SRC] = &gfx2d0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) [GFX2D0_CLK] = &gfx2d0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) [GFX2D1_SRC] = &gfx2d1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) [GFX2D1_CLK] = &gfx2d1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) [GFX3D_SRC] = &gfx3d_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) [GFX3D_CLK] = &gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) [IJPEG_SRC] = &ijpeg_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) [IJPEG_CLK] = &ijpeg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) [JPEGD_SRC] = &jpegd_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) [JPEGD_CLK] = &jpegd_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) [MDP_SRC] = &mdp_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) [MDP_CLK] = &mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) [DSI2_SRC] = &dsi2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) [DSI2_CLK] = &dsi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) [ROT_SRC] = &rot_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) [ROT_CLK] = &rot_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) [TV_ENC_CLK] = &tv_enc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) [TV_DAC_CLK] = &tv_dac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) [MDP_TV_CLK] = &mdp_tv_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) [TV_SRC] = &tv_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) [VCODEC_SRC] = &vcodec_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) [VCODEC_CLK] = &vcodec_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) [VFE_SRC] = &vfe_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) [VFE_CLK] = &vfe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) [VPE_SRC] = &vpe_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) [VPE_CLK] = &vpe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) [CAMCLK0_SRC] = &camclk0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) [CAMCLK0_CLK] = &camclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) [CAMCLK1_SRC] = &camclk1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) [CAMCLK1_CLK] = &camclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) [CAMCLK2_SRC] = &camclk2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) [CAMCLK2_CLK] = &camclk2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) [PLL2] = &pll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) static const struct qcom_reset_map mmcc_msm8960_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) [VPE_AXI_RESET] = { 0x0208, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) [IJPEG_AXI_RESET] = { 0x0208, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) [MPD_AXI_RESET] = { 0x0208, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) [VFE_AXI_RESET] = { 0x0208, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) [SP_AXI_RESET] = { 0x0208, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) [VCODEC_AXI_RESET] = { 0x0208, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) [ROT_AXI_RESET] = { 0x0208, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) [FAB_S3_AXI_RESET] = { 0x0208, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) [FAB_S2_AXI_RESET] = { 0x0208, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) [FAB_S1_AXI_RESET] = { 0x0208, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) [FAB_S0_AXI_RESET] = { 0x0208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) [APU_AHB_RESET] = { 0x020c, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) [CSI_AHB_RESET] = { 0x020c, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) [TV_ENC_AHB_RESET] = { 0x020c, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) [VPE_AHB_RESET] = { 0x020c, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) [FABRIC_AHB_RESET] = { 0x020c, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) [GFX2D0_AHB_RESET] = { 0x020c, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) [GFX2D1_AHB_RESET] = { 0x020c, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) [GFX3D_AHB_RESET] = { 0x020c, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) [HDMI_AHB_RESET] = { 0x020c, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) [IJPEG_AHB_RESET] = { 0x020c, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) [DSI_M_AHB_RESET] = { 0x020c, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) [DSI_S_AHB_RESET] = { 0x020c, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) [JPEGD_AHB_RESET] = { 0x020c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) [MDP_AHB_RESET] = { 0x020c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) [ROT_AHB_RESET] = { 0x020c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) [VCODEC_AHB_RESET] = { 0x020c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) [VFE_AHB_RESET] = { 0x020c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) [DSI2_M_AHB_RESET] = { 0x0210, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) [DSI2_S_AHB_RESET] = { 0x0210, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) [CSIPHY2_RESET] = { 0x0210, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) [CSI_PIX1_RESET] = { 0x0210, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) [CSIPHY0_RESET] = { 0x0210, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) [CSIPHY1_RESET] = { 0x0210, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) [DSI2_RESET] = { 0x0210, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) [VFE_CSI_RESET] = { 0x0210, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) [MDP_RESET] = { 0x0210, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) [AMP_RESET] = { 0x0210, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) [JPEGD_RESET] = { 0x0210, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) [CSI1_RESET] = { 0x0210, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) [VPE_RESET] = { 0x0210, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) [MMSS_FABRIC_RESET] = { 0x0210, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) [VFE_RESET] = { 0x0210, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) [GFX2D0_RESET] = { 0x0210, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) [GFX2D1_RESET] = { 0x0210, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) [GFX3D_RESET] = { 0x0210, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) [HDMI_RESET] = { 0x0210, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) [MMSS_IMEM_RESET] = { 0x0210, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) [IJPEG_RESET] = { 0x0210, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) [CSI0_RESET] = { 0x0210, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) [DSI_RESET] = { 0x0210, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) [VCODEC_RESET] = { 0x0210, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) [MDP_TV_RESET] = { 0x0210, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) [MDP_VSYNC_RESET] = { 0x0210, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) [ROT_RESET] = { 0x0210, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) [TV_HDMI_RESET] = { 0x0210, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) [TV_ENC_RESET] = { 0x0210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) [CSI2_RESET] = { 0x0214, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) [CSI_RDI1_RESET] = { 0x0214, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) [CSI_RDI2_RESET] = { 0x0214 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) static struct clk_regmap *mmcc_apq8064_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [AMP_AHB_CLK] = &_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) [ROT_AXI_CLK] = &rot_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) [CSI0_SRC] = &csi0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) [CSI0_CLK] = &csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) [CSI1_SRC] = &csi1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) [CSI1_CLK] = &csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) [CSI2_SRC] = &csi2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) [CSI2_CLK] = &csi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) [DSI_SRC] = &dsi1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) [DSI_CLK] = &dsi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) [CSI_PIX_CLK] = &csi_pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) [GFX3D_SRC] = &gfx3d_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) [GFX3D_CLK] = &gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) [IJPEG_SRC] = &ijpeg_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) [IJPEG_CLK] = &ijpeg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) [JPEGD_SRC] = &jpegd_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) [JPEGD_CLK] = &jpegd_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) [MDP_SRC] = &mdp_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) [MDP_CLK] = &mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) [DSI2_SRC] = &dsi2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) [DSI2_CLK] = &dsi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) [ROT_SRC] = &rot_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) [ROT_CLK] = &rot_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) [TV_DAC_CLK] = &tv_dac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) [MDP_TV_CLK] = &mdp_tv_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) [TV_SRC] = &tv_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) [VCODEC_SRC] = &vcodec_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) [VCODEC_CLK] = &vcodec_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) [VFE_SRC] = &vfe_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) [VFE_CLK] = &vfe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) [VPE_SRC] = &vpe_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) [VPE_CLK] = &vpe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) [CAMCLK0_SRC] = &camclk0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) [CAMCLK0_CLK] = &camclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) [CAMCLK1_SRC] = &camclk1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) [CAMCLK1_CLK] = &camclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) [CAMCLK2_SRC] = &camclk2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) [CAMCLK2_CLK] = &camclk2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) [PLL2] = &pll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) [RGB_TV_CLK] = &rgb_tv_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) [NPL_TV_CLK] = &npl_tv_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) [VCAP_SRC] = &vcap_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) [VCAP_CLK] = &vcap_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) [PLL15] = &pll15.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) static const struct qcom_reset_map mmcc_apq8064_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) [GFX3D_AXI_RESET] = { 0x0208, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) [VCAP_AXI_RESET] = { 0x0208, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) [VPE_AXI_RESET] = { 0x0208, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) [IJPEG_AXI_RESET] = { 0x0208, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) [MPD_AXI_RESET] = { 0x0208, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) [VFE_AXI_RESET] = { 0x0208, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) [SP_AXI_RESET] = { 0x0208, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) [VCODEC_AXI_RESET] = { 0x0208, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) [ROT_AXI_RESET] = { 0x0208, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) [FAB_S3_AXI_RESET] = { 0x0208, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) [FAB_S2_AXI_RESET] = { 0x0208, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) [FAB_S1_AXI_RESET] = { 0x0208, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) [FAB_S0_AXI_RESET] = { 0x0208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) [APU_AHB_RESET] = { 0x020c, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) [CSI_AHB_RESET] = { 0x020c, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) [TV_ENC_AHB_RESET] = { 0x020c, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) [VPE_AHB_RESET] = { 0x020c, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) [FABRIC_AHB_RESET] = { 0x020c, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) [GFX3D_AHB_RESET] = { 0x020c, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) [HDMI_AHB_RESET] = { 0x020c, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) [IJPEG_AHB_RESET] = { 0x020c, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) [DSI_M_AHB_RESET] = { 0x020c, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) [DSI_S_AHB_RESET] = { 0x020c, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) [JPEGD_AHB_RESET] = { 0x020c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) [MDP_AHB_RESET] = { 0x020c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) [ROT_AHB_RESET] = { 0x020c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) [VCODEC_AHB_RESET] = { 0x020c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) [VFE_AHB_RESET] = { 0x020c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) [VCAP_AHB_RESET] = { 0x0200, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) [DSI2_M_AHB_RESET] = { 0x0200, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) [DSI2_S_AHB_RESET] = { 0x0200, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) [CSIPHY2_RESET] = { 0x0210, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) [CSI_PIX1_RESET] = { 0x0210, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) [CSIPHY0_RESET] = { 0x0210, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) [CSIPHY1_RESET] = { 0x0210, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) [CSI_RDI_RESET] = { 0x0210, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) [CSI_PIX_RESET] = { 0x0210, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) [DSI2_RESET] = { 0x0210, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) [VFE_CSI_RESET] = { 0x0210, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) [MDP_RESET] = { 0x0210, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) [AMP_RESET] = { 0x0210, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) [JPEGD_RESET] = { 0x0210, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) [CSI1_RESET] = { 0x0210, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) [VPE_RESET] = { 0x0210, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) [MMSS_FABRIC_RESET] = { 0x0210, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) [VFE_RESET] = { 0x0210, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) [GFX3D_RESET] = { 0x0210, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) [HDMI_RESET] = { 0x0210, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) [MMSS_IMEM_RESET] = { 0x0210, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) [IJPEG_RESET] = { 0x0210, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) [CSI0_RESET] = { 0x0210, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) [DSI_RESET] = { 0x0210, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) [VCODEC_RESET] = { 0x0210, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) [MDP_TV_RESET] = { 0x0210, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) [MDP_VSYNC_RESET] = { 0x0210, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) [ROT_RESET] = { 0x0210, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) [TV_HDMI_RESET] = { 0x0210, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) [VCAP_NPL_RESET] = { 0x0214, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) [VCAP_RESET] = { 0x0214, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) [CSI2_RESET] = { 0x0214, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) [CSI_RDI1_RESET] = { 0x0214, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) [CSI_RDI2_RESET] = { 0x0214 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) static const struct regmap_config mmcc_msm8960_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .max_register = 0x334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) static const struct regmap_config mmcc_apq8064_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .max_register = 0x350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) static const struct qcom_cc_desc mmcc_msm8960_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .config = &mmcc_msm8960_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .clks = mmcc_msm8960_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .resets = mmcc_msm8960_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static const struct qcom_cc_desc mmcc_apq8064_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .config = &mmcc_apq8064_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .clks = mmcc_apq8064_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .resets = mmcc_apq8064_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) static const struct of_device_id mmcc_msm8960_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) static int mmcc_msm8960_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) bool is_8064;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) match = of_match_device(mmcc_msm8960_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) if (is_8064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) regmap = qcom_cc_map(pdev, match->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) return qcom_cc_really_probe(pdev, match->data, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) static struct platform_driver mmcc_msm8960_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .probe = mmcc_msm8960_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .name = "mmcc-msm8960",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .of_match_table = mmcc_msm8960_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) module_platform_driver(mmcc_msm8960_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) MODULE_ALIAS("platform:mmcc-msm8960");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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