^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/qcom,mmcc-apq8084.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/reset/qcom,mmcc-apq8084.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_MMPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_EDPLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_MMPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_HDMIPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_EDPVCO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_MMPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_DSI0PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_DSI0PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_MMPLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_MMPLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_GPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_DSI1PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_DSI1PLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_MMSLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { P_GPLL0, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { P_HDMIPLL, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { P_DSI0PLL, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { P_DSI1PLL, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "dsi1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { P_MMPLL2, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "mmpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { P_MMPLL3, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { P_EDPLINK, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { P_HDMIPLL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { P_EDPVCO, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { P_DSI0PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { P_DSI1PLL, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char * const mmcc_xo_dsi_hdmi_edp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "edp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "edp_vco_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "dsi1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { P_EDPLINK, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { P_HDMIPLL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { P_DSI0PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { P_DSI1PLL, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "edp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "dsi1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { P_EDPLINK, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { P_HDMIPLL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { P_DSI0PLL_BYTE, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { P_DSI1PLL_BYTE, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "edp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "hdmipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "dsi0pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "dsi1pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { P_MMPLL4, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { P_MMPLL4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { P_GPLL1, 4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { P_MMPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { P_MMPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { P_MMPLL4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { P_GPLL1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { P_MMSLEEP, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct clk_pll mmpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .l_reg = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .m_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .n_reg = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .config_reg = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .mode_reg = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .status_reg = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .name = "mmpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct clk_regmap mmpll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .enable_reg = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "mmpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .parent_names = (const char *[]){ "mmpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct clk_pll mmpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .l_reg = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .m_reg = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .n_reg = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .config_reg = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .mode_reg = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .status_reg = 0x005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "mmpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct clk_regmap mmpll1_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .enable_reg = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "mmpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .parent_names = (const char *[]){ "mmpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct clk_pll mmpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .l_reg = 0x4104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .m_reg = 0x4108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .n_reg = 0x410c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .config_reg = 0x4110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .mode_reg = 0x4100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .status_reg = 0x411c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "mmpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct clk_pll mmpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .l_reg = 0x0084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .m_reg = 0x0088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .n_reg = 0x008c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .config_reg = 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .mode_reg = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .status_reg = 0x009c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "mmpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct clk_pll mmpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .l_reg = 0x00a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .m_reg = 0x00a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .n_reg = 0x00ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .config_reg = 0x00b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .mode_reg = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .status_reg = 0x00bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "mmpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct clk_rcg2 mmss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .cmd_rcgr = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .name = "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct freq_tbl ftbl_mmss_axi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) F(333430000, P_MMPLL1, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) F(466800000, P_MMPLL1, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct clk_rcg2 mmss_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .cmd_rcgr = 0x5040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .freq_tbl = ftbl_mmss_axi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct freq_tbl ftbl_ocmemnoc_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) F(109090000, P_GPLL0, 5.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) F(228570000, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct clk_rcg2 ocmemnoc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .cmd_rcgr = 0x5090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .freq_tbl = ftbl_ocmemnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct clk_rcg2 csi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .cmd_rcgr = 0x3090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct clk_rcg2 csi1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .cmd_rcgr = 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .name = "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct clk_rcg2 csi2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .cmd_rcgr = 0x3160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct clk_rcg2 csi3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .cmd_rcgr = 0x31c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .freq_tbl = ftbl_camss_csi0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .name = "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) F(80000000, P_GPLL0, 7.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) F(109090000, P_GPLL0, 5.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) F(228570000, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) F(465000000, P_MMPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) F(600000000, P_GPLL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct clk_rcg2 vfe0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .cmd_rcgr = 0x3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct clk_rcg2 vfe1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .cmd_rcgr = 0x3620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct freq_tbl ftbl_mdss_mdp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) F(85710000, P_GPLL0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) F(160000000, P_MMPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) F(228570000, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct clk_rcg2 mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .cmd_rcgr = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .freq_tbl = ftbl_mdss_mdp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct clk_rcg2 gfx3d_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .cmd_rcgr = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) F(228570000, P_MMPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct clk_rcg2 jpeg0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .cmd_rcgr = 0x3500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .name = "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct clk_rcg2 jpeg1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .cmd_rcgr = 0x3520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "jpeg1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct clk_rcg2 jpeg2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .cmd_rcgr = 0x3540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .name = "jpeg2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct clk_rcg2 pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .cmd_rcgr = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .name = "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static struct clk_rcg2 pclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .cmd_rcgr = 0x2020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .name = "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) F(465000000, P_MMPLL3, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static struct clk_rcg2 vcodec0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .cmd_rcgr = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .freq_tbl = ftbl_venus0_vcodec0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct freq_tbl ftbl_avsync_vp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static struct clk_rcg2 vp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .cmd_rcgr = 0x2430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .freq_tbl = ftbl_avsync_vp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .name = "vp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static struct clk_rcg2 cci_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .cmd_rcgr = 0x3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .freq_tbl = ftbl_camss_cci_cci_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) F(10000, P_XO, 16, 1, 120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) F(24000, P_XO, 16, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) F(6000000, P_GPLL0, 10, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) F(12000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) F(13000000, P_GPLL0, 4, 13, 150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static struct clk_rcg2 camss_gp0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .cmd_rcgr = 0x3420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .freq_tbl = ftbl_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static struct clk_rcg2 camss_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .cmd_rcgr = 0x3450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .freq_tbl = ftbl_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .name = "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) F(6000000, P_GPLL0, 10, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) F(8000000, P_GPLL0, 15, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) F(16000000, P_MMPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) F(32000000, P_MMPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) F(48000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) F(64000000, P_MMPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static struct clk_rcg2 mclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .cmd_rcgr = 0x3360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .name = "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct clk_rcg2 mclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .cmd_rcgr = 0x3390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .name = "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static struct clk_rcg2 mclk2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .cmd_rcgr = 0x33c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct clk_rcg2 mclk3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .cmd_rcgr = 0x33f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .freq_tbl = ftbl_camss_mclk0_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = "mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static struct clk_rcg2 csi0phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .cmd_rcgr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .name = "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct clk_rcg2 csi1phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .cmd_rcgr = 0x3030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .name = "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct clk_rcg2 csi2phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .cmd_rcgr = 0x3060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .name = "csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) F(372000000, P_MMPLL4, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) F(465000000, P_MMPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) F(600000000, P_GPLL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static struct clk_rcg2 cpp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .cmd_rcgr = 0x3640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .freq_tbl = ftbl_camss_vfe_cpp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .name = "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static struct clk_rcg2 byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .cmd_rcgr = 0x2120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .name = "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static struct clk_rcg2 byte1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .cmd_rcgr = 0x2140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .name = "byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static struct clk_rcg2 edpaux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .cmd_rcgr = 0x20e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .freq_tbl = ftbl_mdss_edpaux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .name = "edpaux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static struct freq_tbl ftbl_mdss_edplink_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) F(135000000, P_EDPLINK, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) F(270000000, P_EDPLINK, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static struct clk_rcg2 edplink_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .cmd_rcgr = 0x20c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .freq_tbl = ftbl_mdss_edplink_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .name = "edplink_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static struct freq_tbl edp_pixel_freq_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) { .src = P_EDPVCO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct clk_rcg2 edppixel_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .cmd_rcgr = 0x20a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .parent_map = mmcc_xo_dsi_hdmi_edp_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .freq_tbl = edp_pixel_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .name = "edppixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .parent_names = mmcc_xo_dsi_hdmi_edp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .ops = &clk_edp_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static struct clk_rcg2 esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .cmd_rcgr = 0x2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .freq_tbl = ftbl_mdss_esc0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .name = "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static struct clk_rcg2 esc1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .cmd_rcgr = 0x2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .freq_tbl = ftbl_mdss_esc0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .name = "esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static struct freq_tbl extpclk_freq_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { .src = P_HDMIPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static struct clk_rcg2 extpclk_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .cmd_rcgr = 0x2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .freq_tbl = extpclk_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .name = "extpclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .ops = &clk_byte_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static struct clk_rcg2 hdmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .cmd_rcgr = 0x2100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .freq_tbl = ftbl_mdss_hdmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .name = "hdmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static struct freq_tbl ftbl_mdss_vsync_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static struct clk_rcg2 vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .cmd_rcgr = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .freq_tbl = ftbl_mdss_vsync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .name = "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static struct clk_rcg2 rbcpr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .cmd_rcgr = 0x4060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .freq_tbl = ftbl_mmss_rbcpr_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .name = "rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static struct clk_rcg2 rbbmtimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .cmd_rcgr = 0x4090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .freq_tbl = ftbl_oxili_rbbmtimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .name = "rbbmtimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static struct freq_tbl ftbl_vpu_maple_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) F(133330000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) F(266670000, P_MMPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) F(465000000, P_MMPLL3, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static struct clk_rcg2 maple_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .cmd_rcgr = 0x1320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .freq_tbl = ftbl_vpu_maple_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .name = "maple_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static struct freq_tbl ftbl_vpu_vdp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) F(200000000, P_MMPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) F(320000000, P_MMPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) F(400000000, P_MMPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static struct clk_rcg2 vdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .cmd_rcgr = 0x1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .freq_tbl = ftbl_vpu_vdp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .name = "vdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static struct freq_tbl ftbl_vpu_bus_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) F(40000000, P_GPLL0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) F(80000000, P_MMPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static struct clk_rcg2 vpu_bus_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .cmd_rcgr = 0x1340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .freq_tbl = ftbl_vpu_bus_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .name = "vpu_bus_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static struct clk_branch mmss_cxo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .halt_reg = 0x5104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .enable_reg = 0x5104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .name = "mmss_cxo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static struct clk_branch mmss_sleepclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .halt_reg = 0x5100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .enable_reg = 0x5100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .name = "mmss_sleepclk_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static struct clk_branch avsync_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .halt_reg = 0x2414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .enable_reg = 0x2414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .name = "avsync_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static struct clk_branch avsync_edppixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .halt_reg = 0x2418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .enable_reg = 0x2418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .name = "avsync_edppixel_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "edppixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static struct clk_branch avsync_extpclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .halt_reg = 0x2410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .enable_reg = 0x2410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .name = "avsync_extpclk_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "extpclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static struct clk_branch avsync_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .halt_reg = 0x241c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .enable_reg = 0x241c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .name = "avsync_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static struct clk_branch avsync_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .halt_reg = 0x2420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .enable_reg = 0x2420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .name = "avsync_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static struct clk_branch avsync_vp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .halt_reg = 0x2404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .enable_reg = 0x2404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .name = "avsync_vp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) "vp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static struct clk_branch camss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .halt_reg = 0x348c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .enable_reg = 0x348c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .name = "camss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct clk_branch camss_cci_cci_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .halt_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .enable_reg = 0x3348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .name = "camss_cci_cci_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static struct clk_branch camss_cci_cci_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .halt_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .enable_reg = 0x3344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .name = "camss_cci_cci_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static struct clk_branch camss_csi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .halt_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .enable_reg = 0x30bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .name = "camss_csi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static struct clk_branch camss_csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .halt_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .enable_reg = 0x30b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .name = "camss_csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static struct clk_branch camss_csi0phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .halt_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .enable_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .name = "camss_csi0phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static struct clk_branch camss_csi0pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .halt_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .enable_reg = 0x30e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .name = "camss_csi0pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static struct clk_branch camss_csi0rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .halt_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .enable_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .name = "camss_csi0rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static struct clk_branch camss_csi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .halt_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enable_reg = 0x3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .name = "camss_csi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static struct clk_branch camss_csi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .halt_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .enable_reg = 0x3124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .name = "camss_csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static struct clk_branch camss_csi1phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .halt_reg = 0x3134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .enable_reg = 0x3134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .name = "camss_csi1phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static struct clk_branch camss_csi1pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .halt_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .enable_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .name = "camss_csi1pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static struct clk_branch camss_csi1rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .halt_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .enable_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .name = "camss_csi1rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static struct clk_branch camss_csi2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .halt_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_reg = 0x3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .name = "camss_csi2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static struct clk_branch camss_csi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .halt_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .enable_reg = 0x3184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .name = "camss_csi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static struct clk_branch camss_csi2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .halt_reg = 0x3194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .enable_reg = 0x3194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .name = "camss_csi2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static struct clk_branch camss_csi2pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .halt_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .enable_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .name = "camss_csi2pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static struct clk_branch camss_csi2rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .halt_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .enable_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .name = "camss_csi2rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) "csi2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static struct clk_branch camss_csi3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .halt_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .enable_reg = 0x31e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .name = "camss_csi3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static struct clk_branch camss_csi3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .halt_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .enable_reg = 0x31e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .name = "camss_csi3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static struct clk_branch camss_csi3phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .halt_reg = 0x31f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .enable_reg = 0x31f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .name = "camss_csi3phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static struct clk_branch camss_csi3pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .halt_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .enable_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .name = "camss_csi3pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static struct clk_branch camss_csi3rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .halt_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .enable_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .name = "camss_csi3rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) "csi3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static struct clk_branch camss_csi_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .halt_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .enable_reg = 0x3704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .name = "camss_csi_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static struct clk_branch camss_csi_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .halt_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .enable_reg = 0x3714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .name = "camss_csi_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static struct clk_branch camss_gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .halt_reg = 0x3444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .enable_reg = 0x3444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .name = "camss_gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) static struct clk_branch camss_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .halt_reg = 0x3474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .enable_reg = 0x3474,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .name = "camss_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static struct clk_branch camss_ispif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .halt_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .enable_reg = 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .name = "camss_ispif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static struct clk_branch camss_jpeg_jpeg0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .halt_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .enable_reg = 0x35a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .name = "camss_jpeg_jpeg0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static struct clk_branch camss_jpeg_jpeg1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .halt_reg = 0x35ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .enable_reg = 0x35ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .name = "camss_jpeg_jpeg1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) "jpeg1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static struct clk_branch camss_jpeg_jpeg2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .halt_reg = 0x35b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .enable_reg = 0x35b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .name = "camss_jpeg_jpeg2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) "jpeg2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .halt_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .enable_reg = 0x35b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .name = "camss_jpeg_jpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static struct clk_branch camss_jpeg_jpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .halt_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .enable_reg = 0x35b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .name = "camss_jpeg_jpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static struct clk_branch camss_mclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .halt_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .enable_reg = 0x3384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .name = "camss_mclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static struct clk_branch camss_mclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .halt_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .enable_reg = 0x33b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .name = "camss_mclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static struct clk_branch camss_mclk2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .halt_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .enable_reg = 0x33e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .name = "camss_mclk2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) "mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static struct clk_branch camss_mclk3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .halt_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .enable_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .name = "camss_mclk3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) "mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static struct clk_branch camss_micro_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .halt_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .enable_reg = 0x3494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .name = "camss_micro_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static struct clk_branch camss_phy0_csi0phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .halt_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .enable_reg = 0x3024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .name = "camss_phy0_csi0phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static struct clk_branch camss_phy1_csi1phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .halt_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .enable_reg = 0x3054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .name = "camss_phy1_csi1phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static struct clk_branch camss_phy2_csi2phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .halt_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .enable_reg = 0x3084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .name = "camss_phy2_csi2phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) "csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static struct clk_branch camss_top_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .halt_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .enable_reg = 0x3484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .name = "camss_top_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static struct clk_branch camss_vfe_cpp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .halt_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .enable_reg = 0x36b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .name = "camss_vfe_cpp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static struct clk_branch camss_vfe_cpp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .halt_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .enable_reg = 0x36b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .name = "camss_vfe_cpp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static struct clk_branch camss_vfe_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .halt_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .enable_reg = 0x36a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .name = "camss_vfe_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) static struct clk_branch camss_vfe_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .halt_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .enable_reg = 0x36ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .name = "camss_vfe_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) "vfe1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static struct clk_branch camss_vfe_vfe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .halt_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .enable_reg = 0x36b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .name = "camss_vfe_vfe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static struct clk_branch camss_vfe_vfe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .halt_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .enable_reg = 0x36bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .name = "camss_vfe_vfe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static struct clk_branch mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .halt_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .enable_reg = 0x2308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .name = "mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static struct clk_branch mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .halt_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .enable_reg = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .name = "mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static struct clk_branch mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .halt_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .enable_reg = 0x233c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .name = "mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static struct clk_branch mdss_byte1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .halt_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .enable_reg = 0x2340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .name = "mdss_byte1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) "byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static struct clk_branch mdss_edpaux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .halt_reg = 0x2334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .enable_reg = 0x2334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .name = "mdss_edpaux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) "edpaux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static struct clk_branch mdss_edplink_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .halt_reg = 0x2330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .enable_reg = 0x2330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .name = "mdss_edplink_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) "edplink_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static struct clk_branch mdss_edppixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .halt_reg = 0x232c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .enable_reg = 0x232c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .name = "mdss_edppixel_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) "edppixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) static struct clk_branch mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .halt_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .enable_reg = 0x2344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .name = "mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static struct clk_branch mdss_esc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .halt_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .enable_reg = 0x2348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .name = "mdss_esc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) "esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) static struct clk_branch mdss_extpclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .halt_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .enable_reg = 0x2324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .name = "mdss_extpclk_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) "extpclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static struct clk_branch mdss_hdmi_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .halt_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .enable_reg = 0x230c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .name = "mdss_hdmi_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) static struct clk_branch mdss_hdmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .halt_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .enable_reg = 0x2338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .name = "mdss_hdmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) "hdmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static struct clk_branch mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .halt_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .enable_reg = 0x231c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .name = "mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static struct clk_branch mdss_mdp_lut_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .halt_reg = 0x2320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .enable_reg = 0x2320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .name = "mdss_mdp_lut_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) static struct clk_branch mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .halt_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .enable_reg = 0x2314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .name = "mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static struct clk_branch mdss_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .halt_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .enable_reg = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .name = "mdss_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static struct clk_branch mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .halt_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .enable_reg = 0x2328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .name = "mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static struct clk_branch mmss_rbcpr_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .halt_reg = 0x4088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .enable_reg = 0x4088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .name = "mmss_rbcpr_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) static struct clk_branch mmss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .halt_reg = 0x4084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .enable_reg = 0x4084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .name = "mmss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) "rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static struct clk_branch mmss_spdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .halt_reg = 0x0230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .enable_reg = 0x0230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .name = "mmss_spdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) "mmss_spdm_ahb_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) static struct clk_branch mmss_spdm_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .halt_reg = 0x0210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .enable_reg = 0x0210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .name = "mmss_spdm_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) "mmss_spdm_axi_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static struct clk_branch mmss_spdm_csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .halt_reg = 0x023c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .enable_reg = 0x023c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .name = "mmss_spdm_csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) "mmss_spdm_csi0_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static struct clk_branch mmss_spdm_gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .halt_reg = 0x022c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .enable_reg = 0x022c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .name = "mmss_spdm_gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) "mmss_spdm_gfx3d_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) static struct clk_branch mmss_spdm_jpeg0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .halt_reg = 0x0204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .enable_reg = 0x0204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .name = "mmss_spdm_jpeg0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) "mmss_spdm_jpeg0_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static struct clk_branch mmss_spdm_jpeg1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .halt_reg = 0x0208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .enable_reg = 0x0208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .name = "mmss_spdm_jpeg1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) "mmss_spdm_jpeg1_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) static struct clk_branch mmss_spdm_jpeg2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .halt_reg = 0x0224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .enable_reg = 0x0224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .name = "mmss_spdm_jpeg2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) "mmss_spdm_jpeg2_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) static struct clk_branch mmss_spdm_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .halt_reg = 0x020c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .enable_reg = 0x020c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .name = "mmss_spdm_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) "mmss_spdm_mdp_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) static struct clk_branch mmss_spdm_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .halt_reg = 0x0234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .enable_reg = 0x0234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .name = "mmss_spdm_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) "mmss_spdm_pclk0_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) static struct clk_branch mmss_spdm_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .halt_reg = 0x0228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .enable_reg = 0x0228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .name = "mmss_spdm_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) "mmss_spdm_pclk1_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) static struct clk_branch mmss_spdm_vcodec0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .halt_reg = 0x0214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .enable_reg = 0x0214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .name = "mmss_spdm_vcodec0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) "mmss_spdm_vcodec0_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) static struct clk_branch mmss_spdm_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .halt_reg = 0x0218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .enable_reg = 0x0218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .name = "mmss_spdm_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) "mmss_spdm_vfe0_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) static struct clk_branch mmss_spdm_vfe1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .halt_reg = 0x021c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .enable_reg = 0x021c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .name = "mmss_spdm_vfe1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) "mmss_spdm_vfe1_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static struct clk_branch mmss_spdm_rm_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .halt_reg = 0x0304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .enable_reg = 0x0304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .name = "mmss_spdm_rm_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .halt_reg = 0x0308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .enable_reg = 0x0308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .name = "mmss_spdm_rm_ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static struct clk_branch mmss_misc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .halt_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .enable_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .name = "mmss_misc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static struct clk_branch mmss_mmssnoc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .halt_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .enable_reg = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .name = "mmss_mmssnoc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .halt_reg = 0x5028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .enable_reg = 0x5028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .name = "mmss_mmssnoc_bto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static struct clk_branch mmss_mmssnoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .halt_reg = 0x506c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .enable_reg = 0x506c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .name = "mmss_mmssnoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static struct clk_branch mmss_s0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .halt_reg = 0x5064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .enable_reg = 0x5064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .name = "mmss_s0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) static struct clk_branch ocmemcx_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .halt_reg = 0x405c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .enable_reg = 0x405c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .name = "ocmemcx_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) static struct clk_branch ocmemcx_ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .halt_reg = 0x4058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .enable_reg = 0x4058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .name = "ocmemcx_ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static struct clk_branch oxili_ocmemgx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .halt_reg = 0x402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .enable_reg = 0x402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .name = "oxili_ocmemgx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static struct clk_branch oxili_gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .halt_reg = 0x4028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .enable_reg = 0x4028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .name = "oxili_gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) static struct clk_branch oxili_rbbmtimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .halt_reg = 0x40b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .enable_reg = 0x40b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .name = "oxili_rbbmtimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) "rbbmtimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) static struct clk_branch oxilicx_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .halt_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .enable_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .name = "oxilicx_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) static struct clk_branch venus0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .halt_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .enable_reg = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .name = "venus0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) static struct clk_branch venus0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .halt_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) .enable_reg = 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .name = "venus0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) static struct clk_branch venus0_core0_vcodec_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .halt_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .enable_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .name = "venus0_core0_vcodec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) static struct clk_branch venus0_core1_vcodec_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .halt_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .enable_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .name = "venus0_core1_vcodec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) static struct clk_branch venus0_ocmemnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .halt_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .enable_reg = 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .name = "venus0_ocmemnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) "ocmemnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) static struct clk_branch venus0_vcodec0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .halt_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) .enable_reg = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .name = "venus0_vcodec0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) static struct clk_branch vpu_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .halt_reg = 0x1430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) .enable_reg = 0x1430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .name = "vpu_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) "mmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) static struct clk_branch vpu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .halt_reg = 0x143c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) .enable_reg = 0x143c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .name = "vpu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) "mmss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) static struct clk_branch vpu_bus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .halt_reg = 0x1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .enable_reg = 0x1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .name = "vpu_bus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) "vpu_bus_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) static struct clk_branch vpu_cxo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .halt_reg = 0x1434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .enable_reg = 0x1434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .name = "vpu_cxo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) static struct clk_branch vpu_maple_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .halt_reg = 0x142c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .enable_reg = 0x142c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .name = "vpu_maple_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) "maple_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) static struct clk_branch vpu_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .halt_reg = 0x1438,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .enable_reg = 0x1438,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .name = "vpu_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) static struct clk_branch vpu_vdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .halt_reg = 0x1428,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .enable_reg = 0x1428,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .name = "vpu_vdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) "vdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) static const struct pll_config mmpll1_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .l = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .m = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) .n = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .vco_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .vco_mask = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .pre_div_mask = 0x7 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .post_div_mask = 0x3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .mn_ena_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) static const struct pll_config mmpll3_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .l = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) .m = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .n = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .vco_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .vco_mask = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .pre_div_mask = 0x7 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .post_div_mask = 0x3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .mn_ena_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .aux_output_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) static struct gdsc venus0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) .gdscr = 0x1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .name = "venus0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) static struct gdsc venus0_core0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) .gdscr = 0x1040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .name = "venus0_core0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) static struct gdsc venus0_core1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) .gdscr = 0x1044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .name = "venus0_core1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .gdscr = 0x2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .cxcs = (unsigned int []){ 0x231c, 0x2320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .cxc_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) .name = "mdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) static struct gdsc camss_jpeg_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) .gdscr = 0x35a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) .name = "camss_jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) static struct gdsc camss_vfe_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) .gdscr = 0x36a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .cxc_count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .name = "camss_vfe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static struct gdsc oxili_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .gdscr = 0x4024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) .cxcs = (unsigned int []){ 0x4028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) .cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .name = "oxili",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) static struct gdsc oxilicx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .gdscr = 0x4034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) .name = "oxilicx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static struct clk_regmap *mmcc_apq8084_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) [MMPLL0] = &mmpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) [MMPLL0_VOTE] = &mmpll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) [MMPLL1] = &mmpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) [MMPLL1_VOTE] = &mmpll1_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) [MMPLL2] = &mmpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) [MMPLL3] = &mmpll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) [MMPLL4] = &mmpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) [MDP_CLK_SRC] = &mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) [VP_CLK_SRC] = &vp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) [CCI_CLK_SRC] = &cci_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) [CPP_CLK_SRC] = &cpp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) [VDP_CLK_SRC] = &vdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) static const struct qcom_reset_map mmcc_apq8084_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) [MMSS_SPDM_RESET] = { 0x0200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) [MMSS_SPDM_RM_RESET] = { 0x0300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) [VENUS0_RESET] = { 0x1020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) [VPU_RESET] = { 0x1400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) [MDSS_RESET] = { 0x2300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) [AVSYNC_RESET] = { 0x2400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) [CAMSS_PHY0_RESET] = { 0x3020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) [CAMSS_PHY1_RESET] = { 0x3050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) [CAMSS_PHY2_RESET] = { 0x3080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) [CAMSS_CSI0_RESET] = { 0x30b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) [CAMSS_CSI1_RESET] = { 0x3120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) [CAMSS_CSI1PHY_RESET] = { 0x3130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) [CAMSS_CSI1RDI_RESET] = { 0x3140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) [CAMSS_CSI1PIX_RESET] = { 0x3150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) [CAMSS_CSI2_RESET] = { 0x3180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) [CAMSS_CSI2PHY_RESET] = { 0x3190 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [CAMSS_CSI3_RESET] = { 0x31e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [CAMSS_CSI3RDI_RESET] = { 0x3200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [CAMSS_CSI3PIX_RESET] = { 0x3210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [CAMSS_ISPIF_RESET] = { 0x3220 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [CAMSS_CCI_RESET] = { 0x3340 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [CAMSS_MCLK0_RESET] = { 0x3380 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [CAMSS_MCLK1_RESET] = { 0x33b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [CAMSS_MCLK2_RESET] = { 0x33e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) [CAMSS_MCLK3_RESET] = { 0x3410 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [CAMSS_GP0_RESET] = { 0x3440 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [CAMSS_GP1_RESET] = { 0x3470 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [CAMSS_TOP_RESET] = { 0x3480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [CAMSS_AHB_RESET] = { 0x3488 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [CAMSS_MICRO_RESET] = { 0x3490 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) [CAMSS_JPEG_RESET] = { 0x35a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [CAMSS_VFE_RESET] = { 0x36a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [OXILI_RESET] = { 0x4020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) [OXILICX_RESET] = { 0x4030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [OCMEMCX_RESET] = { 0x4050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [MMSS_RBCRP_RESET] = { 0x4080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [MMSSNOCAHB_RESET] = { 0x5020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [MMSSNOCAXI_RESET] = { 0x5060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) static struct gdsc *mmcc_apq8084_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [VENUS0_GDSC] = &venus0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [OXILI_GDSC] = &oxili_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [OXILICX_GDSC] = &oxilicx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) static const struct regmap_config mmcc_apq8084_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .max_register = 0x5104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) static const struct qcom_cc_desc mmcc_apq8084_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) .config = &mmcc_apq8084_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) .clks = mmcc_apq8084_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .resets = mmcc_apq8084_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) .gdscs = mmcc_apq8084_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) static const struct of_device_id mmcc_apq8084_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) { .compatible = "qcom,mmcc-apq8084" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static int mmcc_apq8084_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) regmap = dev_get_regmap(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) static struct platform_driver mmcc_apq8084_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) .probe = mmcc_apq8084_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) .name = "mmcc-apq8084",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) .of_match_table = mmcc_apq8084_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) module_platform_driver(mmcc_apq8084_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) MODULE_ALIAS("platform:mmcc-apq8084");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags