^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/qcom,lpass-sdm845.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static struct clk_branch lpass_q6ss_ahbm_aon_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .halt_reg = 0x12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .enable_reg = 0x12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .name = "lpass_q6ss_ahbm_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct clk_branch lpass_q6ss_ahbs_aon_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .halt_reg = 0x1f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .enable_reg = 0x1f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = "lpass_q6ss_ahbs_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct clk_branch lpass_qdsp6ss_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .halt_reg = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* CLK_OFF would not toggle until LPASS is out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .enable_reg = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .name = "lpass_qdsp6ss_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct clk_branch lpass_qdsp6ss_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .halt_reg = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* CLK_OFF would not toggle until LPASS is out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .enable_reg = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "lpass_qdsp6ss_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct clk_branch lpass_qdsp6ss_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .halt_reg = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* CLK_OFF would not toggle until LPASS is out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .enable_reg = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = "lpass_qdsp6ss_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct regmap_config lpass_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct clk_regmap *lpass_cc_sdm845_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct qcom_cc_desc lpass_cc_sdm845_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .config = &lpass_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .clks = lpass_cc_sdm845_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .config = &lpass_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .clks = lpass_qdsp6ss_sdm845_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int lpass_cc_sdm845_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct qcom_cc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) lpass_regmap_config.name = "cc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) desc = &lpass_cc_sdm845_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = qcom_cc_probe_by_index(pdev, 0, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) lpass_regmap_config.name = "qdsp6ss";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) desc = &lpass_qdsp6ss_sdm845_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return qcom_cc_probe_by_index(pdev, 1, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct of_device_id lpass_cc_sdm845_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .compatible = "qcom,sdm845-lpasscc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct platform_driver lpass_cc_sdm845_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .probe = lpass_cc_sdm845_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "sdm845-lpasscc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .of_match_table = lpass_cc_sdm845_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int __init lpass_cc_sdm845_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return platform_driver_register(&lpass_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) subsys_initcall(lpass_cc_sdm845_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void __exit lpass_cc_sdm845_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) platform_driver_unregister(&lpass_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) module_exit(lpass_cc_sdm845_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MODULE_DESCRIPTION("QTI LPASS_CC SDM845 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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