^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/qcom,lcc-msm8960.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-regmap-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct clk_pll pll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .l_reg = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .m_reg = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .n_reg = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .config_reg = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .mode_reg = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .status_reg = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .name = "pll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) P_PXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) P_PLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct parent_map lcc_pxo_pll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { P_PLL4, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char * const lcc_pxo_pll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "pll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct freq_tbl clk_tbl_aif_osr_492[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { 512000, P_PLL4, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 768000, P_PLL4, 4, 1, 160 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 1024000, P_PLL4, 4, 1, 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 1536000, P_PLL4, 4, 1, 80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 2048000, P_PLL4, 4, 1, 60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 3072000, P_PLL4, 4, 1, 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 4096000, P_PLL4, 4, 1, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 6144000, P_PLL4, 4, 1, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 8192000, P_PLL4, 4, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 12288000, P_PLL4, 4, 1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 24576000, P_PLL4, 4, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct freq_tbl clk_tbl_aif_osr_393[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 512000, P_PLL4, 4, 1, 192 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 768000, P_PLL4, 4, 1, 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 1024000, P_PLL4, 4, 1, 96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 1536000, P_PLL4, 4, 1, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 2048000, P_PLL4, 4, 1, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 3072000, P_PLL4, 4, 1, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 4096000, P_PLL4, 4, 1, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 6144000, P_PLL4, 4, 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 8192000, P_PLL4, 4, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 12288000, P_PLL4, 4, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 24576000, P_PLL4, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clk_rcg mi2s_osr_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .ns_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .md_reg = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .parent_map = lcc_pxo_pll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .freq_tbl = clk_tbl_aif_osr_393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "mi2s_osr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .parent_names = lcc_pxo_pll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char * const lcc_mi2s_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "mi2s_osr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct clk_branch mi2s_osr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .halt_reg = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "mi2s_osr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .parent_names = lcc_mi2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct clk_regmap_div mi2s_div_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "mi2s_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .parent_names = lcc_mi2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct clk_branch mi2s_bit_div_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .halt_reg = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .name = "mi2s_bit_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .parent_names = (const char *[]){ "mi2s_div_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct clk_regmap_mux mi2s_bit_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "mi2s_bit_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "mi2s_bit_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "mi2s_codec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct clk_rcg prefix##_osr_src = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .ns_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .md_reg = _md, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .mn = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .mnctr_en_bit = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .mnctr_reset_bit = 7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .mnctr_mode_shift = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .n_val_shift = 24, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .m_val_shift = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .width = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .p = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .pre_div_shift = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pre_div_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .s = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .src_sel_shift = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .parent_map = lcc_pxo_pll4_map, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .freq_tbl = clk_tbl_aif_osr_393, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .enable_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .enable_mask = BIT(9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .name = #prefix "_osr_src", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .parent_names = lcc_pxo_pll4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .num_parents = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .ops = &clk_rcg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .flags = CLK_SET_RATE_GATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const lcc_##prefix##_parents[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #prefix "_osr_src", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct clk_branch prefix##_osr_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .halt_reg = hr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .halt_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .halt_check = BRANCH_HALT_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .enable_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .enable_mask = BIT(21), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = #prefix "_osr_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .parent_names = lcc_##prefix##_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ops = &clk_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .flags = CLK_SET_RATE_PARENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct clk_regmap_div prefix##_div_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .shift = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .width = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = #prefix "_div_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .parent_names = lcc_##prefix##_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .ops = &clk_regmap_div_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct clk_branch prefix##_bit_div_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .halt_reg = hr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .halt_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .halt_check = BRANCH_HALT_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .enable_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .enable_mask = BIT(19), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = #prefix "_bit_div_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .parent_names = (const char *[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #prefix "_div_clk" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .ops = &clk_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .flags = CLK_SET_RATE_PARENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct clk_regmap_mux prefix##_bit_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .shift = 18, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .width = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .name = #prefix "_bit_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .parent_names = (const char *[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #prefix "_bit_div_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #prefix "_codec_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .num_parents = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .ops = &clk_regmap_mux_closest_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .flags = CLK_SET_RATE_PARENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct freq_tbl clk_tbl_pcm_492[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 256000, P_PLL4, 4, 1, 480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 512000, P_PLL4, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 768000, P_PLL4, 4, 1, 160 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 1024000, P_PLL4, 4, 1, 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 1536000, P_PLL4, 4, 1, 80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 2048000, P_PLL4, 4, 1, 60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 3072000, P_PLL4, 4, 1, 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 4096000, P_PLL4, 4, 1, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 6144000, P_PLL4, 4, 1, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 8192000, P_PLL4, 4, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 12288000, P_PLL4, 4, 1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 24576000, P_PLL4, 4, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct freq_tbl clk_tbl_pcm_393[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 256000, P_PLL4, 4, 1, 384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 512000, P_PLL4, 4, 1, 192 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 768000, P_PLL4, 4, 1, 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 1024000, P_PLL4, 4, 1, 96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 1536000, P_PLL4, 4, 1, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 2048000, P_PLL4, 4, 1, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 3072000, P_PLL4, 4, 1, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 4096000, P_PLL4, 4, 1, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 6144000, P_PLL4, 4, 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 8192000, P_PLL4, 4, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 12288000, P_PLL4, 4, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 24576000, P_PLL4, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct clk_rcg pcm_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .ns_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .md_reg = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .parent_map = lcc_pxo_pll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .freq_tbl = clk_tbl_pcm_393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .enable_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "pcm_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .parent_names = lcc_pxo_pll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct clk_branch pcm_clk_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .halt_reg = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .enable_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "pcm_clk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .parent_names = (const char *[]){ "pcm_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct clk_regmap_mux pcm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "pcm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "pcm_clk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "pcm_codec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct clk_rcg slimbus_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .ns_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .md_reg = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .parent_map = lcc_pxo_pll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .freq_tbl = clk_tbl_aif_osr_393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .enable_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .name = "slimbus_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .parent_names = lcc_pxo_pll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const char * const lcc_slimbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "slimbus_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct clk_branch audio_slimbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .halt_reg = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .enable_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = "audio_slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .parent_names = lcc_slimbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct clk_branch sps_slimbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .halt_reg = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .enable_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "sps_slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .parent_names = lcc_slimbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct clk_regmap *lcc_msm8960_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [PLL4] = &pll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [PCM_SRC] = &pcm_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [PCM_CLK_OUT] = &pcm_clk_out.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [PCM_CLK] = &pcm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [SLIMBUS_SRC] = &slimbus_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct regmap_config lcc_msm8960_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .max_register = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct qcom_cc_desc lcc_msm8960_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .config = &lcc_msm8960_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .clks = lcc_msm8960_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .num_clks = ARRAY_SIZE(lcc_msm8960_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct of_device_id lcc_msm8960_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { .compatible = "qcom,lcc-msm8960" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { .compatible = "qcom,lcc-apq8064" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int lcc_msm8960_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Use the correct frequency plan depending on speed of PLL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) regmap_read(regmap, 0x4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (val == 0x12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pcm_src.freq_tbl = clk_tbl_pcm_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Enable PLL4 source on the LPASS Primary PLL Mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regmap_write(regmap, 0xc4, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct platform_driver lcc_msm8960_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .probe = lcc_msm8960_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "lcc-msm8960",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .of_match_table = lcc_msm8960_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) module_platform_driver(lcc_msm8960_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MODULE_ALIAS("platform:lcc-msm8960");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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