^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author : Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/qcom,lcc-mdm9615.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "clk-regmap-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct clk_pll pll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .l_reg = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .m_reg = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .n_reg = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .config_reg = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .mode_reg = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .status_reg = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = "pll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) P_CXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) P_PLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct parent_map lcc_cxo_pll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { P_CXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { P_PLL4, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char * const lcc_cxo_pll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "pll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct freq_tbl clk_tbl_aif_osr_492[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 512000, P_PLL4, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 768000, P_PLL4, 4, 1, 160 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 1024000, P_PLL4, 4, 1, 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 1536000, P_PLL4, 4, 1, 80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 2048000, P_PLL4, 4, 1, 60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 3072000, P_PLL4, 4, 1, 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 4096000, P_PLL4, 4, 1, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 6144000, P_PLL4, 4, 1, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 8192000, P_PLL4, 4, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 12288000, P_PLL4, 4, 1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 24576000, P_PLL4, 4, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 27000000, P_CXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct freq_tbl clk_tbl_aif_osr_393[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 512000, P_PLL4, 4, 1, 192 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 768000, P_PLL4, 4, 1, 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 1024000, P_PLL4, 4, 1, 96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 1536000, P_PLL4, 4, 1, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 2048000, P_PLL4, 4, 1, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 3072000, P_PLL4, 4, 1, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 4096000, P_PLL4, 4, 1, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 6144000, P_PLL4, 4, 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 8192000, P_PLL4, 4, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 12288000, P_PLL4, 4, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 24576000, P_PLL4, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 27000000, P_CXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct clk_rcg mi2s_osr_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .ns_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .md_reg = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .parent_map = lcc_cxo_pll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .freq_tbl = clk_tbl_aif_osr_393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "mi2s_osr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .parent_names = lcc_cxo_pll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const char * const lcc_mi2s_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "mi2s_osr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct clk_branch mi2s_osr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .halt_reg = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = "mi2s_osr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .parent_names = lcc_mi2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct clk_regmap_div mi2s_div_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "mi2s_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .parent_names = lcc_mi2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct clk_branch mi2s_bit_div_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .halt_reg = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .enable_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "mi2s_bit_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .parent_names = (const char *[]){ "mi2s_div_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct clk_regmap_mux mi2s_bit_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "mi2s_bit_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "mi2s_bit_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "mi2s_codec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct clk_rcg prefix##_osr_src = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .ns_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .md_reg = _md, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .mn = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .mnctr_en_bit = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .mnctr_reset_bit = 7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .mnctr_mode_shift = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .n_val_shift = 24, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .m_val_shift = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .width = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .p = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .pre_div_shift = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .pre_div_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .s = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .src_sel_shift = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .parent_map = lcc_cxo_pll4_map, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .freq_tbl = clk_tbl_aif_osr_393, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .enable_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .enable_mask = BIT(9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = #prefix "_osr_src", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .parent_names = lcc_cxo_pll4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .num_parents = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .ops = &clk_rcg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .flags = CLK_SET_RATE_GATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const char * const lcc_##prefix##_parents[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #prefix "_osr_src", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct clk_branch prefix##_osr_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .halt_reg = hr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .halt_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .halt_check = BRANCH_HALT_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .enable_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .enable_mask = BIT(21), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = #prefix "_osr_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .parent_names = lcc_##prefix##_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .ops = &clk_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .flags = CLK_SET_RATE_PARENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct clk_regmap_div prefix##_div_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .shift = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .width = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = #prefix "_div_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .parent_names = lcc_##prefix##_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .ops = &clk_regmap_div_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct clk_branch prefix##_bit_div_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .halt_reg = hr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .halt_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .halt_check = BRANCH_HALT_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .enable_reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .enable_mask = BIT(19), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = #prefix "_bit_div_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .parent_names = (const char *[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #prefix "_div_clk" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .ops = &clk_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .flags = CLK_SET_RATE_PARENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct clk_regmap_mux prefix##_bit_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .reg = _ns, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .shift = 18, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .width = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .clkr = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = #prefix "_bit_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .parent_names = (const char *[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #prefix "_bit_div_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #prefix "_codec_clk", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .num_parents = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .ops = &clk_regmap_mux_closest_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .flags = CLK_SET_RATE_PARENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct freq_tbl clk_tbl_pcm_492[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 256000, P_PLL4, 4, 1, 480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 512000, P_PLL4, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 768000, P_PLL4, 4, 1, 160 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 1024000, P_PLL4, 4, 1, 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 1536000, P_PLL4, 4, 1, 80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 2048000, P_PLL4, 4, 1, 60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 3072000, P_PLL4, 4, 1, 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 4096000, P_PLL4, 4, 1, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 6144000, P_PLL4, 4, 1, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 8192000, P_PLL4, 4, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 12288000, P_PLL4, 4, 1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 24576000, P_PLL4, 4, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 27000000, P_CXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct freq_tbl clk_tbl_pcm_393[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 256000, P_PLL4, 4, 1, 384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 512000, P_PLL4, 4, 1, 192 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 768000, P_PLL4, 4, 1, 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 1024000, P_PLL4, 4, 1, 96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 1536000, P_PLL4, 4, 1, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 2048000, P_PLL4, 4, 1, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 3072000, P_PLL4, 4, 1, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 4096000, P_PLL4, 4, 1, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 6144000, P_PLL4, 4, 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 8192000, P_PLL4, 4, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 12288000, P_PLL4, 4, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 24576000, P_PLL4, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 27000000, P_CXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct clk_rcg pcm_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .ns_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .md_reg = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .parent_map = lcc_cxo_pll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .freq_tbl = clk_tbl_pcm_393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .enable_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .name = "pcm_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .parent_names = lcc_cxo_pll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct clk_branch pcm_clk_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .halt_reg = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .enable_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "pcm_clk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .parent_names = (const char *[]){ "pcm_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct clk_regmap_mux pcm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "pcm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "pcm_clk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "pcm_codec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct clk_rcg slimbus_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .ns_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .md_reg = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .n_val_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .m_val_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .parent_map = lcc_cxo_pll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .freq_tbl = clk_tbl_aif_osr_393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .enable_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .name = "slimbus_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .parent_names = lcc_cxo_pll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const char * const lcc_slimbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "slimbus_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct clk_branch audio_slimbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .halt_reg = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .enable_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .name = "audio_slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .parent_names = lcc_slimbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct clk_branch sps_slimbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .halt_reg = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .halt_check = BRANCH_HALT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .enable_reg = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = "sps_slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .parent_names = lcc_slimbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct clk_regmap *lcc_mdm9615_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [PLL4] = &pll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [PCM_SRC] = &pcm_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [PCM_CLK_OUT] = &pcm_clk_out.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [PCM_CLK] = &pcm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [SLIMBUS_SRC] = &slimbus_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct regmap_config lcc_mdm9615_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .max_register = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct qcom_cc_desc lcc_mdm9615_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .config = &lcc_mdm9615_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .clks = lcc_mdm9615_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_clks = ARRAY_SIZE(lcc_mdm9615_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct of_device_id lcc_mdm9615_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { .compatible = "qcom,lcc-mdm9615" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int lcc_mdm9615_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Use the correct frequency plan depending on speed of PLL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) regmap_read(regmap, 0x4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (val == 0x12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pcm_src.freq_tbl = clk_tbl_pcm_492;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Enable PLL4 source on the LPASS Primary PLL Mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) regmap_write(regmap, 0xc4, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static struct platform_driver lcc_mdm9615_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .probe = lcc_mdm9615_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .name = "lcc-mdm9615",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .of_match_table = lcc_mdm9615_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) module_platform_driver(lcc_mdm9615_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MODULE_ALIAS("platform:lcc-mdm9615");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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