^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-krait.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static unsigned int sec_mux_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static unsigned int pri_mux_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Notifier function for switching the muxes to safe parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * while the hfpll is getting reprogrammed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int krait_notifier_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Switch to safe parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (event == PRE_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mux->reparent = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * By the time POST_RATE_CHANGE notifier is called,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * clk framework itself would have changed the parent for the new rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Only otherwise, put back to the old parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } else if (event == POST_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (!mux->reparent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = krait_mux_clk_ops.set_parent(&mux->hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mux->old_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return notifier_from_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int krait_notifier_register(struct device *dev, struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct krait_mux_clk *mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mux->clk_nb.notifier_call = krait_notifier_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = clk_notifier_register(clk, &mux->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(dev, "failed to register clock notifier: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct krait_div2_clk *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .ops = &krait_div2_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const char *p_names[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) div->width = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) div->shift = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) div->lpl = id >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) div->offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) div->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) init.parent_names = p_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!p_names[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) kfree(init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk = devm_clk_register(dev, &div->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) kfree(p_names[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) kfree(init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return PTR_ERR_OR_ZERO(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) krait_add_sec_mux(struct device *dev, int id, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int offset, bool unique_aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct krait_mux_clk *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char *sec_mux_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "acpu_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "qsb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .parent_names = sec_mux_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .num_parents = ARRAY_SIZE(sec_mux_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .ops = &krait_mux_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mux->offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mux->lpl = id >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mux->mask = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mux->shift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mux->parent_map = sec_mux_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mux->safe_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (unique_aux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!sec_mux_list[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto err_aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk = devm_clk_register(dev, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = krait_notifier_register(dev, clk, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto unique_aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unique_aux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (unique_aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) kfree(sec_mux_list[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) err_aux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) kfree(init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return PTR_ERR_OR_ZERO(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) krait_add_pri_mux(struct device *dev, int id, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct krait_mux_clk *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const char *p_names[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .parent_names = p_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .num_parents = ARRAY_SIZE(p_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .ops = &krait_mux_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mux->mask = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mux->shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mux->offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mux->lpl = id >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mux->parent_map = pri_mux_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mux->safe_sel = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!p_names[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto err_p0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!p_names[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto err_p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!p_names[2]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto err_p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk = devm_clk_register(dev, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = krait_notifier_register(dev, clk, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) goto err_p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) err_p3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) kfree(p_names[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err_p2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) kfree(p_names[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) err_p1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) kfree(p_names[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err_p0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) kfree(init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* id < 0 for L2, otherwise id == physical CPU number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void *p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const char *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (id >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) offset = 0x4501 + (0x1000 * id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) s = p = kasprintf(GFP_KERNEL, "%d", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) offset = 0x500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) s = "_l2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = krait_add_div(dev, id, s, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk = krait_add_pri_mux(dev, id, s, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct clk **clks = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (idx >= 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_err("%s: invalid clock index %d\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return clks[idx] ? : ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct of_device_id krait_cc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { .compatible = "qcom,krait-cc-v1", (void *)1UL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .compatible = "qcom,krait-cc-v2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_DEVICE_TABLE(of, krait_cc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int krait_cc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long cur_rate, aux_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct clk *l2_pri_mux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) id = of_match_device(krait_cc_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!id->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) clk = clk_register_fixed_factor(dev, "acpu_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "gpll0_vote", 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Krait configurations have at most 4 CPUs and one L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clk = krait_add_clks(dev, cpu, id->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clks[cpu] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (IS_ERR(l2_pri_mux_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return PTR_ERR(l2_pri_mux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clks[4] = l2_pri_mux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * We don't want the CPU or L2 clocks to be turned off at late init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * refcount of these clocks. Any cpufreq/hotplug manager can assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * that the clocks have already been prepared and enabled by the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * they take over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) clk_prepare_enable(l2_pri_mux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) WARN(clk_prepare_enable(clks[cpu]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "Unable to turn on CPU%d clock", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Force reinit of HFPLLs and muxes to overwrite any potential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * incorrect configuration of HFPLLs and muxes by the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * While at it, also make sure the cores are running at known rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * and print the current rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * The clocks are set to aux clock rate first to make sure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * secondary mux is not sourcing off of QSB. The rate is then set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * two different rates to force a HFPLL reinit under all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * circumstances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cur_rate = clk_get_rate(l2_pri_mux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) aux_rate = 384000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (cur_rate == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_info("L2 @ QSB rate. Forcing new rate.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cur_rate = aux_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_set_rate(l2_pri_mux_clk, aux_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) clk_set_rate(l2_pri_mux_clk, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clk_set_rate(l2_pri_mux_clk, cur_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) clk = clks[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cur_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (cur_rate == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cur_rate = aux_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) clk_set_rate(clk, aux_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) clk_set_rate(clk, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clk_set_rate(clk, cur_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) of_clk_add_provider(dev->of_node, krait_of_get, clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct platform_driver krait_cc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .probe = krait_cc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "krait-cc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .of_match_table = krait_cc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) module_platform_driver(krait_cc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MODULE_DESCRIPTION("Krait CPU Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_ALIAS("platform:krait-cc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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