^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-hfpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct hfpll_data hdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .mode_reg = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .l_reg = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .m_reg = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .n_reg = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .user_reg = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .config_reg = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .config_val = 0x430405d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .status_reg = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .lock_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .user_val = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .user_vco_mask = 0x100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .low_vco_max_rate = 1248000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .min_rate = 537600000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .max_rate = 2900000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct of_device_id qcom_hfpll_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .compatible = "qcom,hfpll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct regmap_config hfpll_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .max_register = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int qcom_hfpll_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk_hfpll *h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * rather than marking the clock critical and forcing the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * to be always enabled, we make sure that the clock is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * disabled: the firmware remains responsible of enabling this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * clock (for more info check the commit log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_parent_data pdata = { .index = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (of_property_read_string_index(dev->of_node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0, &init.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) init.parent_data = &pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) h->d = &hdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) h->clkr.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) spin_lock_init(&h->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = devm_clk_register_regmap(dev, &h->clkr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_err(dev, "failed to register regmap clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &h->clkr.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct platform_driver qcom_hfpll_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .probe = qcom_hfpll_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "qcom-hfpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .of_match_table = qcom_hfpll_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) module_platform_driver(qcom_hfpll_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_ALIAS("platform:qcom-hfpll");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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