^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CX_GMU_CBCR_SLEEP_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CX_GMU_CBCR_SLEEP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CX_GMU_CBCR_WAKE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CX_GMU_CBCR_WAKE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL0_OUT_MAIN_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPU_CC_PLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPU_CC_PLL1_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct pll_vco lucid_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 249600000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct alpha_pll_config gpu_cc_pll1_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .l = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .alpha = 0xaaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .config_ctl_val = 0x20485699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .config_ctl_hi_val = 0x00002261,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .config_ctl_hi1_val = 0x029a699c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .user_ctl_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .user_ctl_hi_val = 0x00000805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .user_ctl_hi1_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct clk_alpha_pll gpu_cc_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .vco_table = lucid_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .num_vco = ARRAY_SIZE(lucid_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "gpu_cc_pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .ops = &clk_alpha_pll_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct parent_map gpu_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { P_GPU_CC_PLL1_OUT_MAIN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { P_GPLL0_OUT_MAIN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { P_GPLL0_OUT_MAIN_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct clk_parent_data gpu_cc_parent_data_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .hw = &gpu_cc_pll1.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .fw_name = "gcc_gpu_gpll0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clk_rcg2 gpu_cc_gmu_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .cmd_rcgr = 0x1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .parent_map = gpu_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "gpu_cc_gmu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .parent_data = gpu_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct clk_branch gpu_cc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .halt_reg = 0x1078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .enable_reg = 0x1078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "gpu_cc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct clk_branch gpu_cc_crc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .halt_reg = 0x107c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .enable_reg = 0x107c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "gpu_cc_crc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct clk_branch gpu_cc_cx_apb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .halt_reg = 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .enable_reg = 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "gpu_cc_cx_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct clk_branch gpu_cc_cx_gmu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .halt_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .enable_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "gpu_cc_cx_gmu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .hw = &gpu_cc_gmu_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .halt_reg = 0x108c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .enable_reg = 0x108c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "gpu_cc_cx_snoc_dvm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct clk_branch gpu_cc_cxo_aon_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .halt_reg = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .enable_reg = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "gpu_cc_cxo_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct clk_branch gpu_cc_cxo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .halt_reg = 0x109c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .enable_reg = 0x109c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "gpu_cc_cxo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct clk_branch gpu_cc_gx_gmu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .halt_reg = 0x1064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .enable_reg = 0x1064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "gpu_cc_gx_gmu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .hw = &gpu_cc_gmu_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .halt_reg = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .enable_reg = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct gdsc gpu_cx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .gdscr = 0x106c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .gds_hw_ctrl = 0x1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .name = "gpu_cx_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct gdsc gpu_gx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .gdscr = 0x100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .clamp_io_ctrl = 0x1508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .name = "gpu_gx_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .power_on = gdsc_gx_do_nothing_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct clk_regmap *gpu_cc_sm8250_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct qcom_reset_map gpu_cc_sm8250_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct gdsc *gpu_cc_sm8250_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [GPU_CX_GDSC] = &gpu_cx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [GPU_GX_GDSC] = &gpu_gx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct regmap_config gpu_cc_sm8250_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .max_register = 0x8008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct qcom_cc_desc gpu_cc_sm8250_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .config = &gpu_cc_sm8250_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .clks = gpu_cc_sm8250_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .num_clks = ARRAY_SIZE(gpu_cc_sm8250_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .resets = gpu_cc_sm8250_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .num_resets = ARRAY_SIZE(gpu_cc_sm8250_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .gdscs = gpu_cc_sm8250_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .num_gdscs = ARRAY_SIZE(gpu_cc_sm8250_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct of_device_id gpu_cc_sm8250_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { .compatible = "qcom,sm8250-gpucc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DEVICE_TABLE(of, gpu_cc_sm8250_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int gpu_cc_sm8250_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int value, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap = qcom_cc_map(pdev, &gpu_cc_sm8250_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Configure gpu_cc_cx_gmu_clk with recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * wakeup/sleep settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_update_bits(regmap, 0x1098, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return qcom_cc_really_probe(pdev, &gpu_cc_sm8250_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct platform_driver gpu_cc_sm8250_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .probe = gpu_cc_sm8250_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "sm8250-gpucc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .of_match_table = gpu_cc_sm8250_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int __init gpu_cc_sm8250_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return platform_driver_register(&gpu_cc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) subsys_initcall(gpu_cc_sm8250_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __exit gpu_cc_sm8250_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) platform_driver_unregister(&gpu_cc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) module_exit(gpu_cc_sm8250_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_DESCRIPTION("QTI GPU_CC SM8250 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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