Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CX_GMU_CBCR_SLEEP_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CX_GMU_CBCR_SLEEP_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CX_GMU_CBCR_WAKE_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CX_GMU_CBCR_WAKE_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_DIS_WAIT_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_DIS_WAIT_MASK		(0xf << CLK_DIS_WAIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	P_GPLL0_OUT_MAIN_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	P_GPU_CC_PLL1_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	P_GPU_CC_PLL1_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	P_GPU_CC_PLL1_OUT_ODD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static const struct parent_map gpu_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{ P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{ P_GPLL0_OUT_MAIN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ P_GPLL0_OUT_MAIN_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static const char * const gpu_cc_parent_names_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	"bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	"gpu_cc_pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	"gcc_gpu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	"gcc_gpu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	"core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static const struct alpha_pll_config gpu_cc_pll1_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.l = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.alpha = 0xaab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct clk_alpha_pll gpu_cc_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			.name = "gpu_cc_pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			.parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			.ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct clk_rcg2 gpu_cc_gmu_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.cmd_rcgr = 0x1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.parent_map = gpu_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.name = "gpu_cc_gmu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.parent_names = gpu_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static struct clk_branch gpu_cc_cx_gmu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.halt_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.enable_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			.name = "gpu_cc_cx_gmu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			.parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				"gpu_cc_gmu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct clk_branch gpu_cc_cxo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.halt_reg = 0x109c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.enable_reg = 0x109c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			.name = "gpu_cc_cxo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct gdsc gpu_cx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.gdscr = 0x106c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.gds_hw_ctrl = 0x1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.name = "gpu_cx_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct gdsc gpu_gx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.gdscr = 0x100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.clamp_io_ctrl = 0x1508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.name = "gpu_gx_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.power_on = gdsc_gx_do_nothing_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct gdsc *gpu_cc_sdm845_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	[GPU_CX_GDSC] = &gpu_cx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	[GPU_GX_GDSC] = &gpu_gx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct regmap_config gpu_cc_sdm845_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.max_register	= 0x8008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.fast_io	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.config = &gpu_cc_sdm845_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.clks = gpu_cc_sdm845_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.gdscs = gpu_cc_sdm845_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct of_device_id gpu_cc_sdm845_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ .compatible = "qcom,sdm845-gpucc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int gpu_cc_sdm845_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned int value, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * Configure gpu_cc_cx_gmu_clk with recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * wakeup/sleep settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	regmap_update_bits(regmap, 0x1098, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* Configure clk_dis_wait for gpu_cx_gdsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 						8 << CLK_DIS_WAIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct platform_driver gpu_cc_sdm845_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.probe = gpu_cc_sdm845_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.name = "sdm845-gpucc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.of_match_table = gpu_cc_sdm845_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.sync_state = clk_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int __init gpu_cc_sdm845_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return platform_driver_register(&gpu_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) subsys_initcall(gpu_cc_sdm845_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void __exit gpu_cc_sdm845_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	platform_driver_unregister(&gpu_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) module_exit(gpu_cc_sdm845_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_LICENSE("GPL v2");