Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CX_GMU_CBCR_SLEEP_MASK		0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CX_GMU_CBCR_SLEEP_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CX_GMU_CBCR_WAKE_MASK		0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CX_GMU_CBCR_WAKE_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_DIS_WAIT_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_DIS_WAIT_MASK		(0xf << CLK_DIS_WAIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	P_GPLL0_OUT_MAIN_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	P_GPU_CC_PLL1_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	P_GPU_CC_PLL1_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	P_GPU_CC_PLL1_OUT_ODD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static const struct pll_vco fabia_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ 249600000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static struct clk_alpha_pll gpu_cc_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.vco_table = fabia_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.num_vco = ARRAY_SIZE(fabia_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			.name = "gpu_cc_pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			.parent_data =  &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				.fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			.ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const struct parent_map gpu_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ P_GPLL0_OUT_MAIN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ P_GPLL0_OUT_MAIN_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static const struct clk_parent_data gpu_cc_parent_data_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{ .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{ .hw = &gpu_cc_pll1.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ .fw_name = "gcc_gpu_gpll0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static struct clk_rcg2 gpu_cc_gmu_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.cmd_rcgr = 0x1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.parent_map = gpu_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.name = "gpu_cc_gmu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.parent_data = gpu_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static struct clk_branch gpu_cc_crc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.halt_reg = 0x107c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.enable_reg = 0x107c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			.name = "gpu_cc_crc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct clk_branch gpu_cc_cx_gmu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.halt_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.enable_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			.name = "gpu_cc_cx_gmu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			.parent_data =  &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				.hw = &gpu_cc_gmu_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.halt_reg = 0x108c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.enable_reg = 0x108c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			.name = "gpu_cc_cx_snoc_dvm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct clk_branch gpu_cc_cxo_aon_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.halt_reg = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.enable_reg = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			.name = "gpu_cc_cxo_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct clk_branch gpu_cc_cxo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.halt_reg = 0x109c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.enable_reg = 0x109c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			.name = "gpu_cc_cxo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct gdsc cx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.gdscr = 0x106c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.gds_hw_ctrl = 0x1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.name = "cx_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct gdsc gx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.gdscr = 0x100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.clamp_io_ctrl = 0x1508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.name = "gx_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.power_on = gdsc_gx_do_nothing_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.flags = CLAMP_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct gdsc *gpu_cc_sc7180_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	[CX_GDSC] = &cx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	[GX_GDSC] = &gx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct regmap_config gpu_cc_sc7180_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.reg_bits =	32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.reg_stride =	4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.val_bits =	32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.max_register =	0x8008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.fast_io =	true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct qcom_cc_desc gpu_cc_sc7180_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.config = &gpu_cc_sc7180_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.clks = gpu_cc_sc7180_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.gdscs = gpu_cc_sc7180_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct of_device_id gpu_cc_sc7180_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ .compatible = "qcom,sc7180-gpucc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int gpu_cc_sc7180_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct alpha_pll_config gpu_cc_pll_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	unsigned int value, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* 360MHz Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	gpu_cc_pll_config.l = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	gpu_cc_pll_config.alpha = 0xc000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	gpu_cc_pll_config.config_ctl_val = 0x20485699;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	gpu_cc_pll_config.config_ctl_hi_val = 0x00002067;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	gpu_cc_pll_config.user_ctl_val = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	gpu_cc_pll_config.user_ctl_hi_val = 0x00004805;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	gpu_cc_pll_config.test_ctl_hi_val = 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	regmap_update_bits(regmap, 0x1098, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* Configure clk_dis_wait for gpu_cx_gdsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 						8 << CLK_DIS_WAIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct platform_driver gpu_cc_sc7180_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.probe = gpu_cc_sc7180_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.name = "sc7180-gpucc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.of_match_table = gpu_cc_sc7180_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int __init gpu_cc_sc7180_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return platform_driver_register(&gpu_cc_sc7180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) subsys_initcall(gpu_cc_sc7180_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void __exit gpu_cc_sc7180_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	platform_driver_unregister(&gpu_cc_sc7180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) module_exit(gpu_cc_sc7180_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_LICENSE("GPL v2");