Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019, Jeffrey Hugo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	P_GPUPLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* Instead of going directly to the block, XO is routed through this branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static struct clk_branch gpucc_cxo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.halt_reg = 0x1020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.enable_reg = 0x1020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			.name = "gpucc_cxo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			.parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 				.fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				.name = "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			.flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const struct clk_div_table post_div_table_fabia_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ 0x0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ 0x3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ 0x7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct clk_alpha_pll gpupll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.name = "gpupll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static struct clk_alpha_pll_postdiv gpupll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.name = "gpupll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static const struct parent_map gpu_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ P_GPLL0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static const struct clk_parent_data gpu_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ .hw = &gpucc_cxo_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{ .fw_name = "gpll0", .name = "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const struct parent_map gpu_xo_gpupll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ P_GPUPLL0_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct clk_parent_data gpu_xo_gpupll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ .hw = &gpucc_cxo_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ .hw = &gpupll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct clk_rcg2 rbcpr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.cmd_rcgr = 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.parent_map = gpu_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.freq_tbl = ftbl_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.name = "rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.parent_data = gpu_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct clk_rcg2 gfx3d_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.cmd_rcgr = 0x1070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.parent_map = gpu_xo_gpupll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.freq_tbl = ftbl_gfx3d_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.name = "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.parent_data = gpu_xo_gpupll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct clk_rcg2 rbbmtimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.cmd_rcgr = 0x10b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.parent_map = gpu_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.freq_tbl = ftbl_rbbmtimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.name = "rbbmtimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.parent_data = gpu_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct freq_tbl ftbl_gfx3d_isense_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	F(40000000, P_GPLL0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct clk_rcg2 gfx3d_isense_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.cmd_rcgr = 0x1100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.parent_map = gpu_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.freq_tbl = ftbl_gfx3d_isense_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.name = "gfx3d_isense_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.parent_data = gpu_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clk_branch rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.halt_reg = 0x1054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.enable_reg = 0x1054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			.name = "rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			.parent_hws = (const struct clk_hw *[]){ &rbcpr_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct clk_branch gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.halt_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.enable_reg = 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			.name = "gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			.parent_hws = (const struct clk_hw *[]){ &gfx3d_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct clk_branch rbbmtimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.halt_reg = 0x10d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.enable_reg = 0x10d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			.name = "rbbmtimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			.parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			.flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct clk_branch gfx3d_isense_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.halt_reg = 0x1124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.enable_reg = 0x1124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			.name = "gfx3d_isense_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			.parent_hws = (const struct clk_hw *[]){ &gfx3d_isense_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			.ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct gdsc gpu_cx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.gdscr = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.gds_hw_ctrl = 0x1008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.name = "gpu_cx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct gdsc gpu_gx_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.gdscr = 0x1094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.clamp_io_ctrl = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.resets = (unsigned int []){ GPU_GX_BCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.reset_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.cxcs = (unsigned int []){ 0x1098 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.cxc_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.name = "gpu_gx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.parent = &gpu_cx_gdsc.pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.pwrsts = PWRSTS_OFF_ON | PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct clk_regmap *gpucc_msm8998_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	[GPUPLL0] = &gpupll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	[GPUPLL0_OUT_EVEN] = &gpupll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	[GFX3D_ISENSE_CLK_SRC] = &gfx3d_isense_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	[RBCPR_CLK] = &rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	[GFX3D_CLK] = &gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	[RBBMTIMER_CLK] = &rbbmtimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	[GFX3D_ISENSE_CLK] = &gfx3d_isense_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	[GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct gdsc *gpucc_msm8998_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	[GPU_CX_GDSC] = &gpu_cx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	[GPU_GX_GDSC] = &gpu_gx_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct qcom_reset_map gpucc_msm8998_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	[GPU_CX_BCR] = { 0x1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	[RBCPR_BCR] = { 0x1050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	[GPU_GX_BCR] = { 0x1090 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	[GPU_ISENSE_BCR] = { 0x1120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct regmap_config gpucc_msm8998_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.max_register	= 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.fast_io	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct qcom_cc_desc gpucc_msm8998_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.config = &gpucc_msm8998_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.clks = gpucc_msm8998_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.num_clks = ARRAY_SIZE(gpucc_msm8998_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.resets = gpucc_msm8998_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.num_resets = ARRAY_SIZE(gpucc_msm8998_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.gdscs = gpucc_msm8998_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct of_device_id gpucc_msm8998_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ .compatible = "qcom,msm8998-gpucc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int gpucc_msm8998_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* force periph logic on to avoid perf counter corruption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	/* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct platform_driver gpucc_msm8998_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.probe		= gpucc_msm8998_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.name	= "gpucc-msm8998",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.of_match_table = gpucc_msm8998_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) module_platform_driver(gpucc_msm8998_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_DESCRIPTION("QCOM GPUCC MSM8998 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_LICENSE("GPL v2");