^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QCOM_GDSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QCOM_GDSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct reset_controller_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * struct gdsc - Globally Distributed Switch Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @pd: generic power domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @regmap: regmap for MMIO accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @gdscr: gsdc control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @gds_hw_ctrl: gds_hw_ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @cxcs: offsets of branch registers to toggle mem/periph bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @cxc_count: number of @cxcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @pwrsts: Possible powerdomain power states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @en_rest_wait_val: transition delay value for receiving enr ack signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @en_few_wait_val: transition delay value for receiving enf ack signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @clk_dis_wait_val: transition delay value for halting clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @resets: ids of resets associated with this gdsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @reset_count: number of @resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @rcdev: reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct gdsc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct generic_pm_domain pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct generic_pm_domain *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int gdscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int gds_hw_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int clamp_io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int *cxcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int cxc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int en_rest_wait_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int en_few_wait_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int clk_dis_wait_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const u8 pwrsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Powerdomain allowable state bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PWRSTS_OFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PWRSTS_RET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PWRSTS_ON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VOTABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLAMP_IO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HW_CTRL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SW_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AON_RESET BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define POLL_CFG_GDSCR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ALWAYS_ON BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RETAIN_FF_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NO_RET_PERIPH BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct reset_controller_dev *rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int *resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int reset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const char *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct regulator *rsupply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct gdsc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct gdsc **scs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) size_t num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_QCOM_GDSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regmap *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void gdsc_unregister(struct gdsc_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline int gdsc_register(struct gdsc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct regmap *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline void gdsc_unregister(struct gdsc_desc *desc) {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif /* CONFIG_QCOM_GDSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif /* __QCOM_GDSC_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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