^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/qcom,gcc-sm8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_AUD_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_GPLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL4_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL9_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct clk_alpha_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .enable_reg = 0x52018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .ops = &clk_alpha_pll_fixed_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct clk_div_table post_div_table_gpll0_out_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct clk_alpha_pll_postdiv gpll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .post_div_table = post_div_table_gpll0_out_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .ops = &clk_alpha_pll_postdiv_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct clk_alpha_pll gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .offset = 0x76000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .enable_reg = 0x52018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .ops = &clk_alpha_pll_fixed_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct clk_alpha_pll gpll9 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .offset = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .enable_reg = 0x52018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "gpll9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ops = &clk_alpha_pll_fixed_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct parent_map gcc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct clk_parent_data gcc_parent_data_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct clk_parent_data gcc_parent_data_0_ao[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { .fw_name = "bi_tcxo_ao" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct parent_map gcc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct clk_parent_data gcc_parent_data_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .fw_name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct parent_map gcc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct clk_parent_data gcc_parent_data_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .fw_name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct parent_map gcc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct clk_parent_data gcc_parent_data_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct parent_map gcc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { P_GPLL9_OUT_MAIN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { P_GPLL4_OUT_MAIN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct clk_parent_data gcc_parent_data_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .hw = &gpll9.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct parent_map gcc_parent_map_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { P_AUD_REF_CLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct clk_parent_data gcc_parent_data_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .fw_name = "aud_ref_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .cmd_rcgr = 0x48010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "gcc_cpuss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .parent_data = gcc_parent_data_0_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct clk_rcg2 gcc_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cmd_rcgr = 0x64004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .name = "gcc_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct clk_rcg2 gcc_gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .cmd_rcgr = 0x65004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .name = "gcc_gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct clk_rcg2 gcc_gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .cmd_rcgr = 0x66004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .name = "gcc_gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .cmd_rcgr = 0x6b038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = "gcc_pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .parent_data = gcc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .cmd_rcgr = 0x8d038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .name = "gcc_pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .parent_data = gcc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .cmd_rcgr = 0x6038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = "gcc_pcie_2_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .parent_data = gcc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .cmd_rcgr = 0x6f014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "gcc_pcie_phy_refgen_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .parent_data = gcc_parent_data_0_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct clk_rcg2 gcc_pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .cmd_rcgr = 0x33010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .freq_tbl = ftbl_gcc_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "gcc_pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .name = "gcc_qupv3_wrap0_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .cmd_rcgr = 0x17010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .name = "gcc_qupv3_wrap0_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .cmd_rcgr = 0x17140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "gcc_qupv3_wrap0_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .cmd_rcgr = 0x17270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .name = "gcc_qupv3_wrap0_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .cmd_rcgr = 0x173a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .name = "gcc_qupv3_wrap0_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .cmd_rcgr = 0x174d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .name = "gcc_qupv3_wrap0_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .cmd_rcgr = 0x17600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = "gcc_qupv3_wrap0_s6_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .cmd_rcgr = 0x17730,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .name = "gcc_qupv3_wrap0_s7_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .cmd_rcgr = 0x17860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .name = "gcc_qupv3_wrap1_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .cmd_rcgr = 0x18010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .name = "gcc_qupv3_wrap1_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .cmd_rcgr = 0x18140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "gcc_qupv3_wrap1_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .cmd_rcgr = 0x18270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .name = "gcc_qupv3_wrap1_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .cmd_rcgr = 0x183a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .name = "gcc_qupv3_wrap1_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .cmd_rcgr = 0x184d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = "gcc_qupv3_wrap1_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .cmd_rcgr = 0x18600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "gcc_qupv3_wrap2_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .cmd_rcgr = 0x1e010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .name = "gcc_qupv3_wrap2_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .cmd_rcgr = 0x1e140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .name = "gcc_qupv3_wrap2_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .cmd_rcgr = 0x1e270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .name = "gcc_qupv3_wrap2_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .cmd_rcgr = 0x1e3a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .name = "gcc_qupv3_wrap2_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .cmd_rcgr = 0x1e4d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .name = "gcc_qupv3_wrap2_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .cmd_rcgr = 0x1e600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .cmd_rcgr = 0x1400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .name = "gcc_sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .parent_data = gcc_parent_data_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .cmd_rcgr = 0x1600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .name = "gcc_sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) F(105495, P_BI_TCXO, 2, 1, 91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct clk_rcg2 gcc_tsif_ref_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .cmd_rcgr = 0x36010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .parent_map = gcc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .name = "gcc_tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .parent_data = gcc_parent_data_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .cmd_rcgr = 0x75024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .name = "gcc_ufs_card_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .cmd_rcgr = 0x7506c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .name = "gcc_ufs_card_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .cmd_rcgr = 0x750a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .name = "gcc_ufs_card_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .parent_data = gcc_parent_data_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .cmd_rcgr = 0x75084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .name = "gcc_ufs_card_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .cmd_rcgr = 0x77024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .name = "gcc_ufs_phy_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .cmd_rcgr = 0x7706c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .name = "gcc_ufs_phy_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .cmd_rcgr = 0x770a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .name = "gcc_ufs_phy_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .parent_data = gcc_parent_data_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .cmd_rcgr = 0x77084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .name = "gcc_ufs_phy_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .cmd_rcgr = 0xf020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .name = "gcc_usb30_prim_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .cmd_rcgr = 0xf038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .name = "gcc_usb30_prim_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .cmd_rcgr = 0x10020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .name = "gcc_usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .cmd_rcgr = 0x10038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .name = "gcc_usb30_sec_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .cmd_rcgr = 0xf064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .name = "gcc_usb3_prim_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .parent_data = gcc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .cmd_rcgr = 0x10064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .name = "gcc_usb3_sec_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .parent_data = gcc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .reg = 0x48028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .name = "gcc_cpuss_ahb_postdiv_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .reg = 0xf050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .reg = 0x10050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .halt_reg = 0x9000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .enable_reg = 0x9000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .name = "gcc_aggre_noc_pcie_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .halt_reg = 0x750cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .hwcg_reg = 0x750cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .enable_reg = 0x750cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .name = "gcc_aggre_ufs_card_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .halt_reg = 0x770cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .hwcg_reg = 0x770cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .enable_reg = 0x770cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .name = "gcc_aggre_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .halt_reg = 0xf080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .enable_reg = 0xf080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .name = "gcc_aggre_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .halt_reg = 0x10080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .enable_reg = 0x10080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .name = "gcc_aggre_usb3_sec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .halt_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .hwcg_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static struct clk_branch gcc_camera_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .halt_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .enable_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .name = "gcc_camera_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static struct clk_branch gcc_camera_sf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .halt_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .enable_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .name = "gcc_camera_sf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static struct clk_branch gcc_camera_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .halt_reg = 0xb040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .enable_reg = 0xb040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .name = "gcc_camera_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .halt_reg = 0xf07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .enable_reg = 0xf07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .name = "gcc_cfg_noc_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .halt_reg = 0x1007c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .enable_reg = 0x1007c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .name = "gcc_cfg_noc_usb3_sec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static struct clk_branch gcc_cpuss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .halt_reg = 0x48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .name = "gcc_cpuss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static struct clk_branch gcc_cpuss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .halt_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .enable_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .name = "gcc_cpuss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static struct clk_branch gcc_ddrss_gpu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .halt_reg = 0x71154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .enable_reg = 0x71154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .name = "gcc_ddrss_gpu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .halt_reg = 0x8d058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .enable_reg = 0x8d058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .name = "gcc_ddrss_pcie_sf_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static struct clk_branch gcc_disp_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .halt_reg = 0xb034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .enable_reg = 0xb034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .name = "gcc_disp_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static struct clk_branch gcc_disp_sf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .halt_reg = 0xb038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .enable_reg = 0xb038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .name = "gcc_disp_sf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static struct clk_branch gcc_disp_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .halt_reg = 0xb044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .enable_reg = 0xb044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .name = "gcc_disp_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .halt_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .enable_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .hw = &gcc_gp1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .halt_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .enable_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .hw = &gcc_gp2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .halt_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .enable_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .hw = &gcc_gp3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static struct clk_branch gcc_gpu_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .name = "gcc_gpu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .name = "gcc_gpu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .hw = &gpll0_out_even.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static struct clk_branch gcc_gpu_iref_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .halt_reg = 0x8c014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .enable_reg = 0x8c014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .name = "gcc_gpu_iref_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .halt_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .enable_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .name = "gcc_gpu_memnoc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .halt_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .enable_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .name = "gcc_gpu_snoc_dvm_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static struct clk_branch gcc_npu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .halt_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .enable_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .name = "gcc_npu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static struct clk_branch gcc_npu_bwmon_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .halt_reg = 0x73008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .enable_reg = 0x73008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .name = "gcc_npu_bwmon_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .halt_reg = 0x73004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .enable_reg = 0x73004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .name = "gcc_npu_bwmon_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static struct clk_branch gcc_npu_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .halt_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .hwcg_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .enable_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .name = "gcc_npu_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static struct clk_branch gcc_npu_dma_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .halt_reg = 0x4d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .enable_reg = 0x4d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .name = "gcc_npu_dma_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static struct clk_branch gcc_npu_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .name = "gcc_npu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static struct clk_branch gcc_npu_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .name = "gcc_npu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .hw = &gpll0_out_even.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static struct clk_branch gcc_pcie0_phy_refgen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .halt_reg = 0x6f02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .enable_reg = 0x6f02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .name = "gcc_pcie0_phy_refgen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static struct clk_branch gcc_pcie1_phy_refgen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .halt_reg = 0x6f030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .enable_reg = 0x6f030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .name = "gcc_pcie1_phy_refgen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static struct clk_branch gcc_pcie2_phy_refgen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .halt_reg = 0x6f034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .enable_reg = 0x6f034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .name = "gcc_pcie2_phy_refgen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static struct clk_branch gcc_pcie_0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .halt_reg = 0x6b028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .name = "gcc_pcie_0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .halt_reg = 0x6b024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .hwcg_reg = 0x6b024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .name = "gcc_pcie_0_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .halt_reg = 0x6b01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .name = "gcc_pcie_0_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static struct clk_branch gcc_pcie_0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .halt_reg = 0x6b02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .name = "gcc_pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static struct clk_branch gcc_pcie_0_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .halt_reg = 0x6b014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .hwcg_reg = 0x6b014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .name = "gcc_pcie_0_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .halt_reg = 0x6b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .name = "gcc_pcie_0_slv_q2a_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static struct clk_branch gcc_pcie_1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .halt_reg = 0x8d028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .enable_mask = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .name = "gcc_pcie_1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .halt_reg = 0x8d024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .hwcg_reg = 0x8d024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .enable_mask = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .name = "gcc_pcie_1_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .halt_reg = 0x8d01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .name = "gcc_pcie_1_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static struct clk_branch gcc_pcie_1_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .halt_reg = 0x8d02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .enable_mask = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .name = "gcc_pcie_1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static struct clk_branch gcc_pcie_1_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .halt_reg = 0x8d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .hwcg_reg = 0x8d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .name = "gcc_pcie_1_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .halt_reg = 0x8d010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .name = "gcc_pcie_1_slv_q2a_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static struct clk_branch gcc_pcie_2_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .halt_reg = 0x6028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .name = "gcc_pcie_2_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .hw = &gcc_pcie_2_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .halt_reg = 0x6024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .hwcg_reg = 0x6024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .name = "gcc_pcie_2_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .halt_reg = 0x601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .name = "gcc_pcie_2_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static struct clk_branch gcc_pcie_2_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .halt_reg = 0x602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .name = "gcc_pcie_2_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static struct clk_branch gcc_pcie_2_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .halt_reg = 0x6014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .hwcg_reg = 0x6014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .name = "gcc_pcie_2_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .halt_reg = 0x6010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .name = "gcc_pcie_2_slv_q2a_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static struct clk_branch gcc_pcie_mdm_clkref_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .halt_reg = 0x8c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .enable_reg = 0x8c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .name = "gcc_pcie_mdm_clkref_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static struct clk_branch gcc_pcie_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .halt_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .enable_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .name = "gcc_pcie_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static struct clk_branch gcc_pcie_wifi_clkref_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .halt_reg = 0x8c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .enable_reg = 0x8c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .name = "gcc_pcie_wifi_clkref_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static struct clk_branch gcc_pcie_wigig_clkref_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .halt_reg = 0x8c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .enable_reg = 0x8c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .name = "gcc_pcie_wigig_clkref_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .halt_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .enable_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .hw = &gcc_pdm2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .halt_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .hwcg_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .enable_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static struct clk_branch gcc_pdm_xo4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .halt_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .enable_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .name = "gcc_pdm_xo4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .halt_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .halt_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .hwcg_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .enable_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .name = "gcc_qmip_camera_nrt_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .halt_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .hwcg_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .enable_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .name = "gcc_qmip_camera_rt_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static struct clk_branch gcc_qmip_disp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .halt_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .hwcg_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .enable_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .name = "gcc_qmip_disp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .halt_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .hwcg_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .enable_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .name = "gcc_qmip_video_cvp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .halt_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .hwcg_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .enable_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .name = "gcc_qmip_video_vcodec_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .halt_reg = 0x23008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .name = "gcc_qupv3_wrap0_core_2x_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static struct clk_branch gcc_qupv3_wrap0_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .halt_reg = 0x23000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .name = "gcc_qupv3_wrap0_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .halt_reg = 0x1700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .name = "gcc_qupv3_wrap0_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .halt_reg = 0x1713c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .name = "gcc_qupv3_wrap0_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .halt_reg = 0x1726c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .name = "gcc_qupv3_wrap0_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .halt_reg = 0x1739c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .name = "gcc_qupv3_wrap0_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .halt_reg = 0x174cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .name = "gcc_qupv3_wrap0_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .halt_reg = 0x175fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .name = "gcc_qupv3_wrap0_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .halt_reg = 0x1772c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .name = "gcc_qupv3_wrap0_s6_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .halt_reg = 0x1785c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .name = "gcc_qupv3_wrap0_s7_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .halt_reg = 0x23140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .name = "gcc_qupv3_wrap1_core_2x_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static struct clk_branch gcc_qupv3_wrap1_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .halt_reg = 0x23138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .name = "gcc_qupv3_wrap1_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .halt_reg = 0x1800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .name = "gcc_qupv3_wrap1_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .halt_reg = 0x1813c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .enable_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .name = "gcc_qupv3_wrap1_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .halt_reg = 0x1826c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .enable_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .name = "gcc_qupv3_wrap1_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .halt_reg = 0x1839c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .name = "gcc_qupv3_wrap1_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .halt_reg = 0x184cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .name = "gcc_qupv3_wrap1_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .halt_reg = 0x185fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .name = "gcc_qupv3_wrap1_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .halt_reg = 0x23278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .name = "gcc_qupv3_wrap2_core_2x_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static struct clk_branch gcc_qupv3_wrap2_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .halt_reg = 0x23270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .name = "gcc_qupv3_wrap2_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .halt_reg = 0x1e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .name = "gcc_qupv3_wrap2_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .halt_reg = 0x1e13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .name = "gcc_qupv3_wrap2_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .halt_reg = 0x1e26c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .name = "gcc_qupv3_wrap2_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .halt_reg = 0x1e39c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .name = "gcc_qupv3_wrap2_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .halt_reg = 0x1e4cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .name = "gcc_qupv3_wrap2_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .halt_reg = 0x1e5fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .name = "gcc_qupv3_wrap2_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .halt_reg = 0x17004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .name = "gcc_qupv3_wrap_0_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .halt_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .hwcg_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .name = "gcc_qupv3_wrap_0_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .halt_reg = 0x18004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .enable_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .name = "gcc_qupv3_wrap_1_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .halt_reg = 0x18008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .hwcg_reg = 0x18008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .name = "gcc_qupv3_wrap_1_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .halt_reg = 0x1e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .name = "gcc_qupv3_wrap_2_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .halt_reg = 0x1e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .hwcg_reg = 0x1e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .name = "gcc_qupv3_wrap_2_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .halt_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .enable_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .halt_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .enable_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static struct clk_branch gcc_sdcc4_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .halt_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .enable_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .name = "gcc_sdcc4_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static struct clk_branch gcc_sdcc4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .halt_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .enable_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .name = "gcc_sdcc4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static struct clk_branch gcc_tsif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .halt_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .enable_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .name = "gcc_tsif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) static struct clk_branch gcc_tsif_inactivity_timers_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .halt_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .enable_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .name = "gcc_tsif_inactivity_timers_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static struct clk_branch gcc_tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .halt_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .enable_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .name = "gcc_tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .hw = &gcc_tsif_ref_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static struct clk_branch gcc_ufs_1x_clkref_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .halt_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .enable_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .name = "gcc_ufs_1x_clkref_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static struct clk_branch gcc_ufs_card_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .halt_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .hwcg_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .enable_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .name = "gcc_ufs_card_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static struct clk_branch gcc_ufs_card_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .hwcg_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .name = "gcc_ufs_card_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) static struct clk_branch gcc_ufs_card_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .halt_reg = 0x75064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .hwcg_reg = 0x75064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .enable_reg = 0x75064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .name = "gcc_ufs_card_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) static struct clk_branch gcc_ufs_card_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .halt_reg = 0x7509c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .hwcg_reg = 0x7509c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .enable_reg = 0x7509c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .name = "gcc_ufs_card_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .halt_reg = 0x75020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .enable_reg = 0x75020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .name = "gcc_ufs_card_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .halt_reg = 0x750b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .enable_reg = 0x750b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .name = "gcc_ufs_card_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .halt_reg = 0x7501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .enable_reg = 0x7501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .name = "gcc_ufs_card_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) static struct clk_branch gcc_ufs_card_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .halt_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .hwcg_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .enable_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .name = "gcc_ufs_card_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) static struct clk_branch gcc_ufs_phy_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .halt_reg = 0x77018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .hwcg_reg = 0x77018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .enable_reg = 0x77018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .name = "gcc_ufs_phy_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) static struct clk_branch gcc_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .halt_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .hwcg_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .enable_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .name = "gcc_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) static struct clk_branch gcc_ufs_phy_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .halt_reg = 0x77064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .hwcg_reg = 0x77064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .enable_reg = 0x77064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .name = "gcc_ufs_phy_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .halt_reg = 0x7709c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .hwcg_reg = 0x7709c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .enable_reg = 0x7709c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .name = "gcc_ufs_phy_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .halt_reg = 0x77020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .enable_reg = 0x77020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .name = "gcc_ufs_phy_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) .halt_reg = 0x770b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .enable_reg = 0x770b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .name = "gcc_ufs_phy_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .halt_reg = 0x7701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) .enable_reg = 0x7701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .name = "gcc_ufs_phy_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .halt_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .hwcg_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .enable_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .name = "gcc_ufs_phy_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) static struct clk_branch gcc_usb30_prim_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .halt_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .enable_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .name = "gcc_usb30_prim_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .halt_reg = 0xf01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .enable_reg = 0xf01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .name = "gcc_usb30_prim_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .hw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) static struct clk_branch gcc_usb30_prim_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .halt_reg = 0xf018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .enable_reg = 0xf018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .name = "gcc_usb30_prim_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) static struct clk_branch gcc_usb30_sec_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .halt_reg = 0x10010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .enable_reg = 0x10010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .name = "gcc_usb30_sec_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .halt_reg = 0x1001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .enable_reg = 0x1001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .name = "gcc_usb30_sec_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .hw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) static struct clk_branch gcc_usb30_sec_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .halt_reg = 0x10018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .enable_reg = 0x10018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .name = "gcc_usb30_sec_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) .halt_reg = 0xf054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .enable_reg = 0xf054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .name = "gcc_usb3_prim_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) .halt_reg = 0xf058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) .enable_reg = 0xf058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) .name = "gcc_usb3_prim_phy_com_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .halt_reg = 0xf05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .enable_reg = 0xf05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .name = "gcc_usb3_prim_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) static struct clk_branch gcc_usb3_sec_clkref_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) .halt_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) .enable_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) .name = "gcc_usb3_sec_clkref_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) .halt_reg = 0x10054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .enable_reg = 0x10054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) .name = "gcc_usb3_sec_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) .halt_reg = 0x10058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .enable_reg = 0x10058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) .name = "gcc_usb3_sec_phy_com_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .halt_reg = 0x1005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) .enable_reg = 0x1005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) .name = "gcc_usb3_sec_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static struct clk_branch gcc_video_axi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .halt_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .enable_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) .name = "gcc_video_axi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) static struct clk_branch gcc_video_axi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) .halt_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) .enable_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .name = "gcc_video_axi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) static struct clk_branch gcc_video_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) .halt_reg = 0xb03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .enable_reg = 0xb03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) .name = "gcc_video_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) static struct gdsc pcie_0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) .gdscr = 0x6b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) .name = "pcie_0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) static struct gdsc pcie_1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .gdscr = 0x8d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) .name = "pcie_1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) static struct gdsc pcie_2_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) .gdscr = 0x6004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) .name = "pcie_2_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) static struct gdsc ufs_card_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) .gdscr = 0x75004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) .name = "ufs_card_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) static struct gdsc ufs_phy_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) .gdscr = 0x77004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .name = "ufs_phy_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) static struct gdsc usb30_prim_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .gdscr = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) .name = "usb30_prim_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) static struct gdsc usb30_sec_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .gdscr = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .name = "usb30_sec_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .gdscr = 0x7d050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) .gdscr = 0x7d058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) .gdscr = 0x7d054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) .gdscr = 0x7d06c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) static struct clk_regmap *gcc_sm8250_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [GCC_NPU_BWMON_CFG_AHB_CLK] = &gcc_npu_bwmon_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) [GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) [GCC_PCIE_MDM_CLKREF_EN] = &gcc_pcie_mdm_clkref_en.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) [GCC_PCIE_WIFI_CLKREF_EN] = &gcc_pcie_wifi_clkref_en.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) [GCC_PCIE_WIGIG_CLKREF_EN] = &gcc_pcie_wigig_clkref_en.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) [GCC_UFS_1X_CLKREF_EN] = &gcc_ufs_1x_clkref_en.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) &gcc_ufs_card_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) &gcc_ufs_phy_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) &gcc_usb30_prim_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) &gcc_usb30_sec_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) [GPLL9] = &gpll9.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) static struct gdsc *gcc_sm8250_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) [PCIE_0_GDSC] = &pcie_0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) [PCIE_1_GDSC] = &pcie_1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) [PCIE_2_GDSC] = &pcie_2_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) [UFS_CARD_GDSC] = &ufs_card_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) [UFS_PHY_GDSC] = &ufs_phy_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) [USB30_SEC_GDSC] = &usb30_sec_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) static const struct qcom_reset_map gcc_sm8250_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) [GCC_GPU_BCR] = { 0x71000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) [GCC_MMSS_BCR] = { 0xb000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) [GCC_NPU_BWMON_BCR] = { 0x73000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) [GCC_NPU_BCR] = { 0x4d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) [GCC_PCIE_0_BCR] = { 0x6b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) [GCC_PCIE_1_BCR] = { 0x8d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) [GCC_PCIE_2_BCR] = { 0x6000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) [GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) [GCC_PCIE_PHY_BCR] = { 0x6f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) [GCC_PDM_BCR] = { 0x33000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) [GCC_PRNG_BCR] = { 0x34000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) [GCC_SDCC2_BCR] = { 0x14000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) [GCC_SDCC4_BCR] = { 0x16000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) [GCC_TSIF_BCR] = { 0x36000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) [GCC_UFS_CARD_BCR] = { 0x75000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) [GCC_UFS_PHY_BCR] = { 0x77000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) [GCC_USB30_PRIM_BCR] = { 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) [GCC_USB30_SEC_BCR] = { 0x10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) static const struct regmap_config gcc_sm8250_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) .max_register = 0x9c100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) static const struct qcom_cc_desc gcc_sm8250_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) .config = &gcc_sm8250_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) .clks = gcc_sm8250_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) .num_clks = ARRAY_SIZE(gcc_sm8250_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) .resets = gcc_sm8250_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) .num_resets = ARRAY_SIZE(gcc_sm8250_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) .gdscs = gcc_sm8250_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) .num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) static const struct of_device_id gcc_sm8250_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) { .compatible = "qcom,gcc-sm8250" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) static int gcc_sm8250_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) regmap = qcom_cc_map(pdev, &gcc_sm8250_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) * Disable the GPLL0 active input to NPU and GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) * via MISC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) * Keep the clocks always-ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) * GCC_SYS_NOC_CPUSS_AHB_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) ARRAY_SIZE(gcc_dfs_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) static struct platform_driver gcc_sm8250_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) .probe = gcc_sm8250_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) .name = "gcc-sm8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) .of_match_table = gcc_sm8250_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) static int __init gcc_sm8250_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) return platform_driver_register(&gcc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) subsys_initcall(gcc_sm8250_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) static void __exit gcc_sm8250_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) platform_driver_unregister(&gcc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) module_exit(gcc_sm8250_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) MODULE_DESCRIPTION("QTI GCC SM8250 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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