^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/qcom,gcc-sm8150.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_AUD_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL7_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL9_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct clk_alpha_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .ops = &clk_alpha_pll_fixed_trion_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct clk_div_table post_div_table_trion_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 0x0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { 0x3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 0x7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct clk_alpha_pll_postdiv gpll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .post_div_table = post_div_table_trion_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .name = "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .ops = &clk_alpha_pll_postdiv_trion_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct clk_alpha_pll gpll7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .offset = 0x1a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "gpll7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .ops = &clk_alpha_pll_fixed_trion_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct clk_alpha_pll gpll9 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .offset = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "gpll9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .ops = &clk_alpha_pll_fixed_trion_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct parent_map gcc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct clk_parent_data gcc_parents_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .fw_name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct parent_map gcc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct clk_parent_data gcc_parents_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .fw_name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct parent_map gcc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct clk_parent_data gcc_parents_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .fw_name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct parent_map gcc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct clk_parent_data gcc_parents_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .fw_name = "core_bi_pll_test_se"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct parent_map gcc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct clk_parent_data gcc_parents_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .fw_name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct parent_map gcc_parent_map_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { P_GPLL7_OUT_MAIN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct clk_parent_data gcc_parents_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .hw = &gpll7.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .fw_name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct parent_map gcc_parent_map_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { P_GPLL9_OUT_MAIN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct clk_parent_data gcc_parents_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .hw = &gpll9.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .fw_name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct parent_map gcc_parent_map_7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { P_AUD_REF_CLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct clk_parent_data gcc_parents_7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { .fw_name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .cmd_rcgr = 0x48014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "gcc_cpuss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct clk_rcg2 gcc_emac_ptp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .cmd_rcgr = 0x6038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .parent_map = gcc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "gcc_emac_ptp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .parent_data = gcc_parents_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) F(2500000, P_BI_TCXO, 1, 25, 192),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) F(5000000, P_BI_TCXO, 1, 25, 96),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .cmd_rcgr = 0x601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .parent_map = gcc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "gcc_emac_rgmii_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .parent_data = gcc_parents_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct clk_rcg2 gcc_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .cmd_rcgr = 0x64004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .name = "gcc_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .parent_data = gcc_parents_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct clk_rcg2 gcc_gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .cmd_rcgr = 0x65004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "gcc_gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .parent_data = gcc_parents_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct clk_rcg2 gcc_gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .cmd_rcgr = 0x66004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "gcc_gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .parent_data = gcc_parents_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .cmd_rcgr = 0x6b02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "gcc_pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .parent_data = gcc_parents_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .cmd_rcgr = 0x8d02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = "gcc_pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .parent_data = gcc_parents_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .cmd_rcgr = 0x6f014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "gcc_pcie_phy_refgen_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct clk_rcg2 gcc_pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .cmd_rcgr = 0x33010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .freq_tbl = ftbl_gcc_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "gcc_pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct clk_rcg2 gcc_qspi_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .cmd_rcgr = 0x4b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .freq_tbl = ftbl_gcc_qspi_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "gcc_qspi_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .cmd_rcgr = 0x17148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .name = "gcc_qupv3_wrap0_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .cmd_rcgr = 0x17278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .name = "gcc_qupv3_wrap0_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .cmd_rcgr = 0x173a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "gcc_qupv3_wrap0_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .cmd_rcgr = 0x174d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = "gcc_qupv3_wrap0_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .cmd_rcgr = 0x17608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "gcc_qupv3_wrap0_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .cmd_rcgr = 0x17738,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "gcc_qupv3_wrap0_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .cmd_rcgr = 0x17868,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .name = "gcc_qupv3_wrap0_s6_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .cmd_rcgr = 0x17998,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "gcc_qupv3_wrap0_s7_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .cmd_rcgr = 0x18148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .name = "gcc_qupv3_wrap1_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .cmd_rcgr = 0x18278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .name = "gcc_qupv3_wrap1_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .cmd_rcgr = 0x183a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "gcc_qupv3_wrap1_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .cmd_rcgr = 0x184d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .name = "gcc_qupv3_wrap1_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .cmd_rcgr = 0x18608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .name = "gcc_qupv3_wrap1_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .cmd_rcgr = 0x18738,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .name = "gcc_qupv3_wrap1_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .cmd_rcgr = 0x1e148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .name = "gcc_qupv3_wrap2_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .cmd_rcgr = 0x1e278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .name = "gcc_qupv3_wrap2_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .cmd_rcgr = 0x1e3a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "gcc_qupv3_wrap2_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .cmd_rcgr = 0x1e4d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .name = "gcc_qupv3_wrap2_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .cmd_rcgr = 0x1e608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .name = "gcc_qupv3_wrap2_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .cmd_rcgr = 0x1e738,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .name = "gcc_qupv3_wrap2_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .cmd_rcgr = 0x1400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .parent_map = gcc_parent_map_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .name = "gcc_sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .parent_data = gcc_parents_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .cmd_rcgr = 0x1600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .name = "gcc_sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .parent_data = gcc_parents_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) F(105495, P_BI_TCXO, 2, 1, 91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static struct clk_rcg2 gcc_tsif_ref_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .cmd_rcgr = 0x36010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .parent_map = gcc_parent_map_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .name = "gcc_tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .parent_data = gcc_parents_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .cmd_rcgr = 0x75020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .name = "gcc_ufs_card_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .cmd_rcgr = 0x75060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .name = "gcc_ufs_card_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .cmd_rcgr = 0x75094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .name = "gcc_ufs_card_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .parent_data = gcc_parents_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .cmd_rcgr = 0x75078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .name = "gcc_ufs_card_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .cmd_rcgr = 0x77020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .name = "gcc_ufs_phy_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .cmd_rcgr = 0x77060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .name = "gcc_ufs_phy_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .cmd_rcgr = 0x77094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .name = "gcc_ufs_phy_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .parent_data = gcc_parents_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .cmd_rcgr = 0x77078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .name = "gcc_ufs_phy_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .cmd_rcgr = 0xf01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .name = "gcc_usb30_prim_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .cmd_rcgr = 0xf034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .name = "gcc_usb30_prim_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .cmd_rcgr = 0x1001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .name = "gcc_usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .cmd_rcgr = 0x10034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .name = "gcc_usb30_sec_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .parent_data = gcc_parents_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .cmd_rcgr = 0xf060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .name = "gcc_usb3_prim_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .parent_data = gcc_parents_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .cmd_rcgr = 0x10060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .name = "gcc_usb3_sec_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .parent_data = gcc_parents_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .halt_reg = 0x90018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .enable_reg = 0x90018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .name = "gcc_aggre_noc_pcie_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .halt_reg = 0x750c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .hwcg_reg = 0x750c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .enable_reg = 0x750c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .name = "gcc_aggre_ufs_card_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) &gcc_ufs_card_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .halt_reg = 0x750c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .hwcg_reg = 0x750c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .enable_reg = 0x750c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) &gcc_aggre_ufs_card_axi_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .halt_reg = 0x770c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .hwcg_reg = 0x770c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .enable_reg = 0x770c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .name = "gcc_aggre_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) &gcc_ufs_phy_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .halt_reg = 0x770c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .hwcg_reg = 0x770c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .enable_reg = 0x770c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .halt_reg = 0xf07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .enable_reg = 0xf07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .name = "gcc_aggre_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) &gcc_usb30_prim_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .halt_reg = 0x1007c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .enable_reg = 0x1007c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .name = "gcc_aggre_usb3_sec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) &gcc_usb30_sec_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .halt_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .hwcg_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * Clock ON depends on external parent 'config noc', so cant poll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * delay and also mark as crtitical for camss boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct clk_branch gcc_camera_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .halt_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .hwcg_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .enable_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .name = "gcc_camera_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static struct clk_branch gcc_camera_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .halt_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .enable_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .name = "gcc_camera_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static struct clk_branch gcc_camera_sf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .halt_reg = 0xb034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .enable_reg = 0xb034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .name = "gcc_camera_sf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* XO critical input to camss, so no need to poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static struct clk_branch gcc_camera_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .halt_reg = 0xb044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .enable_reg = 0xb044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .name = "gcc_camera_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .halt_reg = 0xf078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .enable_reg = 0xf078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .name = "gcc_cfg_noc_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) &gcc_usb30_prim_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .halt_reg = 0x10078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .enable_reg = 0x10078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .name = "gcc_cfg_noc_usb3_sec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) &gcc_usb30_sec_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static struct clk_branch gcc_cpuss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .halt_reg = 0x48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .name = "gcc_cpuss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) &gcc_cpuss_ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* required for cpuss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static struct clk_branch gcc_cpuss_dvm_bus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .halt_reg = 0x48190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .enable_reg = 0x48190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .name = "gcc_cpuss_dvm_bus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* required for cpuss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static struct clk_branch gcc_cpuss_gnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .halt_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .hwcg_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .name = "gcc_cpuss_gnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* required for cpuss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static struct clk_branch gcc_cpuss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .halt_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .enable_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .name = "gcc_cpuss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static struct clk_branch gcc_ddrss_gpu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .halt_reg = 0x71154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .enable_reg = 0x71154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .name = "gcc_ddrss_gpu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * Clock ON depends on external parent 'config noc', so cant poll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * delay and also mark as crtitical for disp boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static struct clk_branch gcc_disp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .halt_reg = 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .hwcg_reg = 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .enable_reg = 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .name = "gcc_disp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static struct clk_branch gcc_disp_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .halt_reg = 0xb038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .enable_reg = 0xb038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .name = "gcc_disp_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static struct clk_branch gcc_disp_sf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .halt_reg = 0xb03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .enable_reg = 0xb03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .name = "gcc_disp_sf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* XO critical input to disp, so no need to poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static struct clk_branch gcc_disp_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .halt_reg = 0xb048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .enable_reg = 0xb048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .name = "gcc_disp_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static struct clk_branch gcc_emac_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .halt_reg = 0x6010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .enable_reg = 0x6010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .name = "gcc_emac_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static struct clk_branch gcc_emac_ptp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .halt_reg = 0x6034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .enable_reg = 0x6034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .name = "gcc_emac_ptp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) &gcc_emac_ptp_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static struct clk_branch gcc_emac_rgmii_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .halt_reg = 0x6018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_reg = 0x6018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .name = "gcc_emac_rgmii_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) &gcc_emac_rgmii_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct clk_branch gcc_emac_slv_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .halt_reg = 0x6014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .hwcg_reg = 0x6014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .enable_reg = 0x6014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .name = "gcc_emac_slv_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .halt_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .enable_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) &gcc_gp1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .halt_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .enable_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) &gcc_gp2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .halt_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .enable_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) &gcc_gp3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static struct clk_branch gcc_gpu_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .halt_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .hwcg_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .enable_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .name = "gcc_gpu_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* required for gpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static struct clk_branch gcc_gpu_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .name = "gcc_gpu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .name = "gcc_gpu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static struct clk_branch gcc_gpu_iref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .halt_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .enable_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .name = "gcc_gpu_iref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .halt_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .enable_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .name = "gcc_gpu_memnoc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .halt_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .enable_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .name = "gcc_gpu_snoc_dvm_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static struct clk_branch gcc_npu_at_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .halt_reg = 0x4d010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .enable_reg = 0x4d010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .name = "gcc_npu_at_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static struct clk_branch gcc_npu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .halt_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .enable_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .name = "gcc_npu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static struct clk_branch gcc_npu_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .halt_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .hwcg_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .enable_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .name = "gcc_npu_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) /* required for npu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static struct clk_branch gcc_npu_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .name = "gcc_npu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static struct clk_branch gcc_npu_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .name = "gcc_npu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static struct clk_branch gcc_npu_trig_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .halt_reg = 0x4d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .enable_reg = 0x4d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .name = "gcc_npu_trig_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static struct clk_branch gcc_pcie0_phy_refgen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .halt_reg = 0x6f02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .enable_reg = 0x6f02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .name = "gcc_pcie0_phy_refgen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) &gcc_pcie_phy_refgen_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static struct clk_branch gcc_pcie1_phy_refgen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .halt_reg = 0x6f030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .enable_reg = 0x6f030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .name = "gcc_pcie1_phy_refgen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) &gcc_pcie_phy_refgen_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static struct clk_branch gcc_pcie_0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .halt_reg = 0x6b020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .name = "gcc_pcie_0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) &gcc_pcie_0_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .halt_reg = 0x6b01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .hwcg_reg = 0x6b01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .name = "gcc_pcie_0_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static struct clk_branch gcc_pcie_0_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .halt_reg = 0x8c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .enable_reg = 0x8c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .name = "gcc_pcie_0_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .halt_reg = 0x6b018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .name = "gcc_pcie_0_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static struct clk_branch gcc_pcie_0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .halt_reg = 0x6b024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .name = "gcc_pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) static struct clk_branch gcc_pcie_0_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .halt_reg = 0x6b014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .hwcg_reg = 0x6b014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .name = "gcc_pcie_0_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .halt_reg = 0x6b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .name = "gcc_pcie_0_slv_q2a_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static struct clk_branch gcc_pcie_1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .halt_reg = 0x8d020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .enable_mask = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .name = "gcc_pcie_1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) &gcc_pcie_1_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .halt_reg = 0x8d01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .hwcg_reg = 0x8d01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .enable_mask = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .name = "gcc_pcie_1_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct clk_branch gcc_pcie_1_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .halt_reg = 0x8c02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .enable_reg = 0x8c02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .name = "gcc_pcie_1_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .halt_reg = 0x8d018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .name = "gcc_pcie_1_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static struct clk_branch gcc_pcie_1_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .halt_reg = 0x8d024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .enable_mask = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .name = "gcc_pcie_1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static struct clk_branch gcc_pcie_1_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .halt_reg = 0x8d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .hwcg_reg = 0x8d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .name = "gcc_pcie_1_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .halt_reg = 0x8d010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .name = "gcc_pcie_1_slv_q2a_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static struct clk_branch gcc_pcie_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .halt_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .enable_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .name = "gcc_pcie_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) &gcc_pcie_0_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .halt_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .enable_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) &gcc_pdm2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .halt_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .hwcg_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .enable_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static struct clk_branch gcc_pdm_xo4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .halt_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .enable_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .name = "gcc_pdm_xo4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .halt_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .halt_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .hwcg_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .enable_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .name = "gcc_qmip_camera_nrt_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .halt_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .hwcg_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .enable_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .name = "gcc_qmip_camera_rt_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static struct clk_branch gcc_qmip_disp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .halt_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .hwcg_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .enable_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .name = "gcc_qmip_disp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .halt_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .hwcg_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .enable_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .name = "gcc_qmip_video_cvp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .halt_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .hwcg_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .enable_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .name = "gcc_qmip_video_vcodec_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .halt_reg = 0x4b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .enable_reg = 0x4b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .name = "gcc_qspi_cnoc_periph_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static struct clk_branch gcc_qspi_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .halt_reg = 0x4b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .enable_reg = 0x4b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .name = "gcc_qspi_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) &gcc_qspi_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .halt_reg = 0x17144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .name = "gcc_qupv3_wrap0_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .halt_reg = 0x17274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .name = "gcc_qupv3_wrap0_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .halt_reg = 0x173a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .name = "gcc_qupv3_wrap0_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .halt_reg = 0x174d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .name = "gcc_qupv3_wrap0_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .halt_reg = 0x17604,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .name = "gcc_qupv3_wrap0_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .halt_reg = 0x17734,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .name = "gcc_qupv3_wrap0_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .halt_reg = 0x17864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .name = "gcc_qupv3_wrap0_s6_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .halt_reg = 0x17994,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .name = "gcc_qupv3_wrap0_s7_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .halt_reg = 0x18144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .name = "gcc_qupv3_wrap1_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .halt_reg = 0x18274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .enable_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .name = "gcc_qupv3_wrap1_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .halt_reg = 0x183a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .enable_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .name = "gcc_qupv3_wrap1_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .halt_reg = 0x184d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .name = "gcc_qupv3_wrap1_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .halt_reg = 0x18604,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .name = "gcc_qupv3_wrap1_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .halt_reg = 0x18734,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .name = "gcc_qupv3_wrap1_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .halt_reg = 0x1e144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .name = "gcc_qupv3_wrap2_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .halt_reg = 0x1e274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .name = "gcc_qupv3_wrap2_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .halt_reg = 0x1e3a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .name = "gcc_qupv3_wrap2_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .halt_reg = 0x1e4d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .name = "gcc_qupv3_wrap2_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .halt_reg = 0x1e604,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .name = "gcc_qupv3_wrap2_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .halt_reg = 0x1e734,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .name = "gcc_qupv3_wrap2_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .halt_reg = 0x17004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .name = "gcc_qupv3_wrap_0_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .halt_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .hwcg_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .name = "gcc_qupv3_wrap_0_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .halt_reg = 0x18004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .enable_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .name = "gcc_qupv3_wrap_1_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .halt_reg = 0x18008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .hwcg_reg = 0x18008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .name = "gcc_qupv3_wrap_1_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .halt_reg = 0x1e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .name = "gcc_qupv3_wrap_2_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .halt_reg = 0x1e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .hwcg_reg = 0x1e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .enable_reg = 0x52014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .name = "gcc_qupv3_wrap_2_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .halt_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .enable_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .halt_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .enable_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) &gcc_sdcc2_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) static struct clk_branch gcc_sdcc4_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .halt_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .enable_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .name = "gcc_sdcc4_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static struct clk_branch gcc_sdcc4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .halt_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .enable_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .name = "gcc_sdcc4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) &gcc_sdcc4_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .halt_reg = 0x4819c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .name = "gcc_sys_noc_cpuss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) &gcc_cpuss_ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) /* required for cpuss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static struct clk_branch gcc_tsif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .halt_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .enable_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .name = "gcc_tsif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static struct clk_branch gcc_tsif_inactivity_timers_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .halt_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .enable_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .name = "gcc_tsif_inactivity_timers_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) static struct clk_branch gcc_tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .halt_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .enable_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .name = "gcc_tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) &gcc_tsif_ref_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static struct clk_branch gcc_ufs_card_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .halt_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .hwcg_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .enable_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .name = "gcc_ufs_card_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) static struct clk_branch gcc_ufs_card_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .hwcg_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .name = "gcc_ufs_card_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) &gcc_ufs_card_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .hwcg_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .name = "gcc_ufs_card_axi_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) &gcc_ufs_card_axi_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) static struct clk_branch gcc_ufs_card_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .halt_reg = 0x8c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .enable_reg = 0x8c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .name = "gcc_ufs_card_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) static struct clk_branch gcc_ufs_card_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .halt_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .hwcg_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .enable_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .name = "gcc_ufs_card_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) &gcc_ufs_card_ice_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .halt_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .hwcg_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .enable_reg = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) &gcc_ufs_card_ice_core_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) static struct clk_branch gcc_ufs_card_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .halt_reg = 0x75090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .hwcg_reg = 0x75090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .enable_reg = 0x75090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .name = "gcc_ufs_card_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .halt_reg = 0x75090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .hwcg_reg = 0x75090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .enable_reg = 0x75090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) &gcc_ufs_card_phy_aux_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) /* external clocks so add BRANCH_HALT_SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .enable_reg = 0x7501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .name = "gcc_ufs_card_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) /* external clocks so add BRANCH_HALT_SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .enable_reg = 0x750ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .name = "gcc_ufs_card_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) /* external clocks so add BRANCH_HALT_SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .enable_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .name = "gcc_ufs_card_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) static struct clk_branch gcc_ufs_card_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .halt_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) .hwcg_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) .enable_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .name = "gcc_ufs_card_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) .halt_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) .hwcg_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .enable_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) &gcc_ufs_card_unipro_core_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static struct clk_branch gcc_ufs_mem_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) .halt_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .enable_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .name = "gcc_ufs_mem_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) static struct clk_branch gcc_ufs_phy_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .halt_reg = 0x77014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .hwcg_reg = 0x77014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .enable_reg = 0x77014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .name = "gcc_ufs_phy_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) static struct clk_branch gcc_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .halt_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .hwcg_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .enable_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .name = "gcc_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) &gcc_ufs_phy_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .halt_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .hwcg_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) .enable_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .name = "gcc_ufs_phy_axi_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) &gcc_ufs_phy_axi_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) static struct clk_branch gcc_ufs_phy_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .halt_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .hwcg_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .enable_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .name = "gcc_ufs_phy_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .halt_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .hwcg_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .enable_reg = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) &gcc_ufs_phy_ice_core_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .halt_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .hwcg_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .enable_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .name = "gcc_ufs_phy_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .halt_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .hwcg_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) .enable_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) &gcc_ufs_phy_phy_aux_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /* external clocks so add BRANCH_HALT_SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) .enable_reg = 0x7701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) .name = "gcc_ufs_phy_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) /* external clocks so add BRANCH_HALT_SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .enable_reg = 0x770ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) .name = "gcc_ufs_phy_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) /* external clocks so add BRANCH_HALT_SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .enable_reg = 0x77018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .name = "gcc_ufs_phy_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) .halt_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) .hwcg_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) .enable_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) .name = "gcc_ufs_phy_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .halt_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) .hwcg_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) .enable_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) &gcc_ufs_phy_unipro_core_clk.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) static struct clk_branch gcc_usb30_prim_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) .halt_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) .enable_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) .name = "gcc_usb30_prim_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) &gcc_usb30_prim_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) .halt_reg = 0xf018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) .enable_reg = 0xf018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .name = "gcc_usb30_prim_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) static struct clk_branch gcc_usb30_prim_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .halt_reg = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) .enable_reg = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .name = "gcc_usb30_prim_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) static struct clk_branch gcc_usb30_sec_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) .halt_reg = 0x10010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .enable_reg = 0x10010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) .name = "gcc_usb30_sec_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) &gcc_usb30_sec_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) .halt_reg = 0x10018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) .enable_reg = 0x10018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) .name = "gcc_usb30_sec_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) static struct clk_branch gcc_usb30_sec_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) .halt_reg = 0x10014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) .enable_reg = 0x10014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) .name = "gcc_usb30_sec_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) static struct clk_branch gcc_usb3_prim_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) .halt_reg = 0x8c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .enable_reg = 0x8c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .name = "gcc_usb3_prim_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) .halt_reg = 0xf050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .enable_reg = 0xf050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) .name = "gcc_usb3_prim_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) .halt_reg = 0xf054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) .enable_reg = 0xf054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) .name = "gcc_usb3_prim_phy_com_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) .enable_reg = 0xf058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) .name = "gcc_usb3_prim_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) static struct clk_branch gcc_usb3_sec_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) .halt_reg = 0x8c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) .enable_reg = 0x8c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) .name = "gcc_usb3_sec_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) .halt_reg = 0x10050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .enable_reg = 0x10050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) .name = "gcc_usb3_sec_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) .halt_reg = 0x10054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) .enable_reg = 0x10054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) .name = "gcc_usb3_sec_phy_com_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .enable_reg = 0x10058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) .name = "gcc_usb3_sec_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) * Clock ON depends on external parent 'config noc', so cant poll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) * delay and also mark as crtitical for video boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) static struct clk_branch gcc_video_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) .halt_reg = 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) .hwcg_reg = 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) .enable_reg = 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) .name = "gcc_video_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) static struct clk_branch gcc_video_axi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) .halt_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) .enable_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) .name = "gcc_video_axi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) static struct clk_branch gcc_video_axi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) .halt_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) .enable_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) .name = "gcc_video_axi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) static struct clk_branch gcc_video_axic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) .halt_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) .enable_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) .name = "gcc_video_axic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) /* XO critical input to video, so no need to poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) static struct clk_branch gcc_video_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) .halt_reg = 0xb040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) .enable_reg = 0xb040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) .name = "gcc_video_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) static struct gdsc usb30_prim_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) .gdscr = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) .name = "usb30_prim_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) static struct gdsc usb30_sec_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) .gdscr = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) .name = "usb30_sec_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) static struct clk_regmap *gcc_sm8150_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) &gcc_ufs_card_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) &gcc_ufs_phy_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) &gcc_usb30_prim_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) &gcc_usb30_sec_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) [GPLL7] = &gpll7.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) [GPLL9] = &gpll9.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) static const struct qcom_reset_map gcc_sm8150_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) [GCC_EMAC_BCR] = { 0x6000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) [GCC_GPU_BCR] = { 0x71000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) [GCC_MMSS_BCR] = { 0xb000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) [GCC_NPU_BCR] = { 0x4d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) [GCC_PCIE_0_BCR] = { 0x6b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) [GCC_PCIE_1_BCR] = { 0x8d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) [GCC_PCIE_PHY_BCR] = { 0x6f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) [GCC_PDM_BCR] = { 0x33000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) [GCC_PRNG_BCR] = { 0x34000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) [GCC_QSPI_BCR] = { 0x24008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) [GCC_SDCC2_BCR] = { 0x14000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) [GCC_SDCC4_BCR] = { 0x16000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) [GCC_TSIF_BCR] = { 0x36000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) [GCC_UFS_CARD_BCR] = { 0x75000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) [GCC_UFS_PHY_BCR] = { 0x77000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) [GCC_USB30_PRIM_BCR] = { 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) [GCC_USB30_SEC_BCR] = { 0x10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) static struct gdsc *gcc_sm8150_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) [USB30_SEC_GDSC] = &usb30_sec_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) static const struct regmap_config gcc_sm8150_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) .max_register = 0x9c040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) static const struct qcom_cc_desc gcc_sm8150_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) .config = &gcc_sm8150_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) .clks = gcc_sm8150_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) .resets = gcc_sm8150_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) .gdscs = gcc_sm8150_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) static const struct of_device_id gcc_sm8150_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) { .compatible = "qcom,gcc-sm8150" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) static int gcc_sm8150_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) static struct platform_driver gcc_sm8150_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) .probe = gcc_sm8150_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) .name = "gcc-sm8150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) .of_match_table = gcc_sm8150_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) static int __init gcc_sm8150_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) return platform_driver_register(&gcc_sm8150_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) subsys_initcall(gcc_sm8150_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) static void __exit gcc_sm8150_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) platform_driver_unregister(&gcc_sm8150_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) module_exit(gcc_sm8150_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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