^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-sdm845.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_AUD_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_GPLL4_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct parent_map gcc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const char * const gcc_parent_names_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct parent_map gcc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const char * const gcc_parent_names_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "core_pi_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct parent_map gcc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char * const gcc_parent_names_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "core_pi_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct parent_map gcc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const gcc_parent_names_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct parent_map gcc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char * const gcc_parent_names_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct parent_map gcc_parent_map_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { P_AUD_REF_CLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char * const gcc_parent_names_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "aud_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const gcc_parent_names_7_ao[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "bi_tcxo_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char * const gcc_parent_names_8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char * const gcc_parent_names_8_ao[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "bi_tcxo_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct parent_map gcc_parent_map_10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { P_GPLL4_OUT_MAIN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const char * const gcc_parent_names_10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clk_alpha_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk_alpha_pll gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .offset = 0x76000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct clk_div_table post_div_table_fabia_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0x7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct clk_alpha_pll_postdiv gpll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .cmd_rcgr = 0x48014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "gcc_cpuss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .parent_names = gcc_parent_names_7_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .cmd_rcgr = 0x4815c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .name = "gcc_cpuss_rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .parent_names = gcc_parent_names_8_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct clk_rcg2 gcc_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .cmd_rcgr = 0x64004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "gcc_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct clk_rcg2 gcc_gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .cmd_rcgr = 0x65004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "gcc_gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct clk_rcg2 gcc_gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .cmd_rcgr = 0x66004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .name = "gcc_gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .cmd_rcgr = 0x6b028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "gcc_pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .cmd_rcgr = 0x8d028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .name = "gcc_pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .cmd_rcgr = 0x6f014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "gcc_pcie_phy_refgen_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct clk_rcg2 gcc_qspi_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .cmd_rcgr = 0x4b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .freq_tbl = ftbl_gcc_qspi_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "gcc_qspi_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct clk_rcg2 gcc_pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .cmd_rcgr = 0x33010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .freq_tbl = ftbl_gcc_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "gcc_pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "gcc_qupv3_wrap0_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .cmd_rcgr = 0x17034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "gcc_qupv3_wrap0_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .cmd_rcgr = 0x17164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = "gcc_qupv3_wrap0_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .cmd_rcgr = 0x17294,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "gcc_qupv3_wrap0_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .cmd_rcgr = 0x173c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "gcc_qupv3_wrap0_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .cmd_rcgr = 0x174f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "gcc_qupv3_wrap0_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .cmd_rcgr = 0x17624,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = "gcc_qupv3_wrap0_s6_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .cmd_rcgr = 0x17754,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .name = "gcc_qupv3_wrap0_s7_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .cmd_rcgr = 0x17884,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .name = "gcc_qupv3_wrap1_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .cmd_rcgr = 0x18018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "gcc_qupv3_wrap1_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .cmd_rcgr = 0x18148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .name = "gcc_qupv3_wrap1_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .cmd_rcgr = 0x18278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .name = "gcc_qupv3_wrap1_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .cmd_rcgr = 0x183a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "gcc_qupv3_wrap1_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .cmd_rcgr = 0x184d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = "gcc_qupv3_wrap1_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .cmd_rcgr = 0x18608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .name = "gcc_qupv3_wrap1_s6_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .cmd_rcgr = 0x18738,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .name = "gcc_qupv3_wrap1_s7_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .cmd_rcgr = 0x18868,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .cmd_rcgr = 0x1400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .parent_map = gcc_parent_map_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .name = "gcc_sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .parent_names = gcc_parent_names_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .cmd_rcgr = 0x1600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "gcc_sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) F(105495, P_BI_TCXO, 2, 1, 91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct clk_rcg2 gcc_tsif_ref_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .cmd_rcgr = 0x36010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .parent_map = gcc_parent_map_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .name = "gcc_tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .parent_names = gcc_parent_names_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .cmd_rcgr = 0x7501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .name = "gcc_ufs_card_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .cmd_rcgr = 0x7505c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .name = "gcc_ufs_card_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .cmd_rcgr = 0x75090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .name = "gcc_ufs_card_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .parent_names = gcc_parent_names_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .cmd_rcgr = 0x75074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .name = "gcc_ufs_card_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .cmd_rcgr = 0x7701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .name = "gcc_ufs_phy_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .cmd_rcgr = 0x7705c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .name = "gcc_ufs_phy_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .cmd_rcgr = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .name = "gcc_ufs_phy_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .parent_names = gcc_parent_names_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .cmd_rcgr = 0x77074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .name = "gcc_ufs_phy_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .cmd_rcgr = 0xf018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .name = "gcc_usb30_prim_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .cmd_rcgr = 0xf030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .name = "gcc_usb30_prim_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .cmd_rcgr = 0x10018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .name = "gcc_usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .cmd_rcgr = 0x10030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .name = "gcc_usb30_sec_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .cmd_rcgr = 0xf05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .name = "gcc_usb3_prim_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .cmd_rcgr = 0x1005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .name = "gcc_usb3_sec_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .cmd_rcgr = 0x7a030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .name = "gcc_vs_ctrl_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .parent_names = gcc_parent_names_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static struct clk_rcg2 gcc_vsensor_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .cmd_rcgr = 0x7a018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .freq_tbl = ftbl_gcc_vsensor_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .name = "gcc_vsensor_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .parent_names = gcc_parent_names_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .halt_reg = 0x90014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .enable_reg = 0x90014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .name = "gcc_aggre_noc_pcie_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .halt_reg = 0x82028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .hwcg_reg = 0x82028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .enable_reg = 0x82028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .name = "gcc_aggre_ufs_card_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) "gcc_ufs_card_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .halt_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .hwcg_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .enable_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .name = "gcc_aggre_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "gcc_ufs_phy_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .halt_reg = 0x8201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .enable_reg = 0x8201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .name = "gcc_aggre_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "gcc_usb30_prim_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .halt_reg = 0x82020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .enable_reg = 0x82020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .name = "gcc_aggre_usb3_sec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "gcc_usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static struct clk_branch gcc_apc_vs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .halt_reg = 0x7a050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .enable_reg = 0x7a050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .name = "gcc_apc_vs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "gcc_vsensor_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .halt_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .hwcg_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static struct clk_branch gcc_camera_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .halt_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .hwcg_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .enable_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .name = "gcc_camera_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static struct clk_branch gcc_camera_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .halt_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .enable_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .name = "gcc_camera_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static struct clk_branch gcc_camera_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .halt_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .enable_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .name = "gcc_camera_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static struct clk_branch gcc_ce1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .halt_reg = 0x4100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .hwcg_reg = 0x4100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .name = "gcc_ce1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static struct clk_branch gcc_ce1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .halt_reg = 0x41008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .name = "gcc_ce1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static struct clk_branch gcc_ce1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .halt_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .name = "gcc_ce1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .halt_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .enable_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .name = "gcc_cfg_noc_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) "gcc_usb30_prim_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .halt_reg = 0x5030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .enable_reg = 0x5030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .name = "gcc_cfg_noc_usb3_sec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "gcc_usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static struct clk_branch gcc_cpuss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .halt_reg = 0x48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .name = "gcc_cpuss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) "gcc_cpuss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static struct clk_branch gcc_cpuss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .halt_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .enable_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .name = "gcc_cpuss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) "gcc_cpuss_rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static struct clk_branch gcc_ddrss_gpu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .halt_reg = 0x44038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .enable_reg = 0x44038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .name = "gcc_ddrss_gpu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static struct clk_branch gcc_disp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .halt_reg = 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .hwcg_reg = 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .enable_reg = 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .name = "gcc_disp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static struct clk_branch gcc_disp_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .halt_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .enable_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .name = "gcc_disp_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static struct clk_branch gcc_disp_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .name = "gcc_disp_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .ops = &clk_branch2_aon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static struct clk_branch gcc_disp_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .name = "gcc_disp_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static struct clk_branch gcc_disp_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .halt_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .enable_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .name = "gcc_disp_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .halt_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .enable_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) "gcc_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .halt_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .enable_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) "gcc_gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .halt_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .enable_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "gcc_gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static struct clk_branch gcc_gpu_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .halt_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .hwcg_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .enable_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .name = "gcc_gpu_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static struct clk_branch gcc_gpu_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .name = "gcc_gpu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .name = "gcc_gpu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static struct clk_branch gcc_gpu_iref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .halt_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .enable_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .name = "gcc_gpu_iref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .halt_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .enable_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .name = "gcc_gpu_memnoc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .halt_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .enable_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .name = "gcc_gpu_snoc_dvm_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static struct clk_branch gcc_gpu_vs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .halt_reg = 0x7a04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .enable_reg = 0x7a04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .name = "gcc_gpu_vs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) "gcc_vsensor_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static struct clk_branch gcc_mss_axis2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .halt_reg = 0x8a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .enable_reg = 0x8a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .name = "gcc_mss_axis2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static struct clk_branch gcc_mss_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .halt_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .hwcg_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .enable_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .name = "gcc_mss_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static struct clk_branch gcc_mss_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .name = "gcc_mss_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static struct clk_branch gcc_mss_mfab_axis_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .halt_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .hwcg_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .enable_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .name = "gcc_mss_mfab_axis_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .halt_reg = 0x8a154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .enable_reg = 0x8a154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .name = "gcc_mss_q6_memnoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static struct clk_branch gcc_mss_snoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .halt_reg = 0x8a150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .enable_reg = 0x8a150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .name = "gcc_mss_snoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static struct clk_branch gcc_mss_vs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .halt_reg = 0x7a048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .enable_reg = 0x7a048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .name = "gcc_mss_vs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) "gcc_vsensor_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static struct clk_branch gcc_pcie_0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .halt_reg = 0x6b01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .name = "gcc_pcie_0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) "gcc_pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .halt_reg = 0x6b018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .hwcg_reg = 0x6b018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .name = "gcc_pcie_0_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static struct clk_branch gcc_pcie_0_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .halt_reg = 0x8c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .enable_reg = 0x8c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .name = "gcc_pcie_0_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .halt_reg = 0x6b014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .name = "gcc_pcie_0_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static struct clk_branch gcc_pcie_0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .name = "gcc_pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .parent_names = (const char *[]){ "pcie_0_pipe_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static struct clk_branch gcc_pcie_0_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .halt_reg = 0x6b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .hwcg_reg = 0x6b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .name = "gcc_pcie_0_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .halt_reg = 0x6b00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .name = "gcc_pcie_0_slv_q2a_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) static struct clk_branch gcc_pcie_1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .halt_reg = 0x8d01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .enable_mask = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .name = "gcc_pcie_1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) "gcc_pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .halt_reg = 0x8d018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .hwcg_reg = 0x8d018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .enable_mask = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .name = "gcc_pcie_1_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static struct clk_branch gcc_pcie_1_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .halt_reg = 0x8c02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .enable_reg = 0x8c02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .name = "gcc_pcie_1_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .halt_reg = 0x8d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .name = "gcc_pcie_1_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static struct clk_branch gcc_pcie_1_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .enable_mask = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .name = "gcc_pcie_1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .parent_names = (const char *[]){ "pcie_1_pipe_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) static struct clk_branch gcc_pcie_1_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .halt_reg = 0x8d010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .hwcg_reg = 0x8d010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .name = "gcc_pcie_1_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .halt_reg = 0x8d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .name = "gcc_pcie_1_slv_q2a_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static struct clk_branch gcc_pcie_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .halt_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .enable_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .name = "gcc_pcie_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) "gcc_pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static struct clk_branch gcc_pcie_phy_refgen_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .halt_reg = 0x6f02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .enable_reg = 0x6f02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .name = "gcc_pcie_phy_refgen_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) "gcc_pcie_phy_refgen_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .halt_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .enable_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "gcc_pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .halt_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .hwcg_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .enable_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static struct clk_branch gcc_pdm_xo4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .halt_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .enable_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .name = "gcc_pdm_xo4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .halt_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .hwcg_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static struct clk_branch gcc_qmip_camera_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .halt_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .hwcg_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .enable_reg = 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .name = "gcc_qmip_camera_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static struct clk_branch gcc_qmip_disp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .halt_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .hwcg_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .enable_reg = 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .name = "gcc_qmip_disp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static struct clk_branch gcc_qmip_video_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .halt_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .hwcg_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .enable_reg = 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .name = "gcc_qmip_video_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .halt_reg = 0x4b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .enable_reg = 0x4b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .name = "gcc_qspi_cnoc_periph_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static struct clk_branch gcc_qspi_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .halt_reg = 0x4b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .enable_reg = 0x4b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .name = "gcc_qspi_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) "gcc_qspi_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .halt_reg = 0x17030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .name = "gcc_qupv3_wrap0_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) "gcc_qupv3_wrap0_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .halt_reg = 0x17160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .name = "gcc_qupv3_wrap0_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) "gcc_qupv3_wrap0_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .halt_reg = 0x17290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .name = "gcc_qupv3_wrap0_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) "gcc_qupv3_wrap0_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .halt_reg = 0x173c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .name = "gcc_qupv3_wrap0_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) "gcc_qupv3_wrap0_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .halt_reg = 0x174f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .name = "gcc_qupv3_wrap0_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) "gcc_qupv3_wrap0_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .halt_reg = 0x17620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .name = "gcc_qupv3_wrap0_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) "gcc_qupv3_wrap0_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .halt_reg = 0x17750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .name = "gcc_qupv3_wrap0_s6_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) "gcc_qupv3_wrap0_s6_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .halt_reg = 0x17880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .name = "gcc_qupv3_wrap0_s7_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) "gcc_qupv3_wrap0_s7_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .halt_reg = 0x18014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .name = "gcc_qupv3_wrap1_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) "gcc_qupv3_wrap1_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .halt_reg = 0x18144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .enable_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .name = "gcc_qupv3_wrap1_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) "gcc_qupv3_wrap1_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .halt_reg = 0x18274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .enable_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .name = "gcc_qupv3_wrap1_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) "gcc_qupv3_wrap1_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .halt_reg = 0x183a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .name = "gcc_qupv3_wrap1_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) "gcc_qupv3_wrap1_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .halt_reg = 0x184d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .name = "gcc_qupv3_wrap1_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) "gcc_qupv3_wrap1_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .halt_reg = 0x18604,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .name = "gcc_qupv3_wrap1_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) "gcc_qupv3_wrap1_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .halt_reg = 0x18734,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .enable_mask = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .name = "gcc_qupv3_wrap1_s6_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) "gcc_qupv3_wrap1_s6_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .halt_reg = 0x18864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .enable_mask = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .name = "gcc_qupv3_wrap1_s7_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) "gcc_qupv3_wrap1_s7_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .halt_reg = 0x17004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .name = "gcc_qupv3_wrap_0_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .halt_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .hwcg_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .name = "gcc_qupv3_wrap_0_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .halt_reg = 0x1800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .enable_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .name = "gcc_qupv3_wrap_1_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .halt_reg = 0x18010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .hwcg_reg = 0x18010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .name = "gcc_qupv3_wrap_1_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .halt_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .enable_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .halt_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .enable_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) "gcc_sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) static struct clk_branch gcc_sdcc4_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .halt_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .enable_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .name = "gcc_sdcc4_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static struct clk_branch gcc_sdcc4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .halt_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .enable_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .name = "gcc_sdcc4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) "gcc_sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .halt_reg = 0x414c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .name = "gcc_sys_noc_cpuss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) "gcc_cpuss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static struct clk_branch gcc_tsif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .halt_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .enable_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .name = "gcc_tsif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static struct clk_branch gcc_tsif_inactivity_timers_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .halt_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .enable_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .name = "gcc_tsif_inactivity_timers_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static struct clk_branch gcc_tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .halt_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .enable_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .name = "gcc_tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) "gcc_tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static struct clk_branch gcc_ufs_card_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .hwcg_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .name = "gcc_ufs_card_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) static struct clk_branch gcc_ufs_card_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .halt_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .hwcg_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .enable_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .name = "gcc_ufs_card_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) "gcc_ufs_card_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) static struct clk_branch gcc_ufs_card_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .halt_reg = 0x8c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .enable_reg = 0x8c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .name = "gcc_ufs_card_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static struct clk_branch gcc_ufs_card_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .halt_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .hwcg_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .enable_reg = 0x75058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .name = "gcc_ufs_card_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) "gcc_ufs_card_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) static struct clk_branch gcc_ufs_card_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .halt_reg = 0x7508c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .hwcg_reg = 0x7508c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .enable_reg = 0x7508c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .name = "gcc_ufs_card_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) "gcc_ufs_card_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .enable_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .name = "gcc_ufs_card_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .enable_reg = 0x750a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .name = "gcc_ufs_card_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .enable_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .name = "gcc_ufs_card_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static struct clk_branch gcc_ufs_card_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .halt_reg = 0x75054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .hwcg_reg = 0x75054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .enable_reg = 0x75054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .name = "gcc_ufs_card_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) "gcc_ufs_card_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) static struct clk_branch gcc_ufs_mem_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .halt_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .enable_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .name = "gcc_ufs_mem_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static struct clk_branch gcc_ufs_phy_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .halt_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .hwcg_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .enable_reg = 0x77010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .name = "gcc_ufs_phy_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static struct clk_branch gcc_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .halt_reg = 0x7700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .hwcg_reg = 0x7700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .enable_reg = 0x7700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .name = "gcc_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) "gcc_ufs_phy_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) static struct clk_branch gcc_ufs_phy_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .halt_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .hwcg_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .enable_reg = 0x77058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .name = "gcc_ufs_phy_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) "gcc_ufs_phy_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .halt_reg = 0x7708c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .hwcg_reg = 0x7708c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .enable_reg = 0x7708c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .name = "gcc_ufs_phy_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) "gcc_ufs_phy_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .enable_reg = 0x77018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .name = "gcc_ufs_phy_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .enable_reg = 0x770a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .name = "gcc_ufs_phy_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .enable_reg = 0x77014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .name = "gcc_ufs_phy_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .halt_reg = 0x77054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .hwcg_reg = 0x77054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .enable_reg = 0x77054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .name = "gcc_ufs_phy_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) "gcc_ufs_phy_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) static struct clk_branch gcc_usb30_prim_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .halt_reg = 0xf00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .enable_reg = 0xf00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .name = "gcc_usb30_prim_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) "gcc_usb30_prim_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .halt_reg = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .enable_reg = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .name = "gcc_usb30_prim_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) "gcc_usb30_prim_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static struct clk_branch gcc_usb30_prim_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .halt_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .enable_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .name = "gcc_usb30_prim_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static struct clk_branch gcc_usb30_sec_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .halt_reg = 0x1000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .enable_reg = 0x1000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .name = "gcc_usb30_sec_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) "gcc_usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .halt_reg = 0x10014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .enable_reg = 0x10014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .name = "gcc_usb30_sec_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) "gcc_usb30_sec_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) static struct clk_branch gcc_usb30_sec_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .halt_reg = 0x10010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .enable_reg = 0x10010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .name = "gcc_usb30_sec_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static struct clk_branch gcc_usb3_prim_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .halt_reg = 0x8c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .enable_reg = 0x8c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .name = "gcc_usb3_prim_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .halt_reg = 0xf04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .enable_reg = 0xf04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .name = "gcc_usb3_prim_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) "gcc_usb3_prim_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .halt_reg = 0xf050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .enable_reg = 0xf050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .name = "gcc_usb3_prim_phy_com_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) "gcc_usb3_prim_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .enable_reg = 0xf054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .name = "gcc_usb3_prim_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) static struct clk_branch gcc_usb3_sec_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .halt_reg = 0x8c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .enable_reg = 0x8c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .name = "gcc_usb3_sec_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) .halt_reg = 0x1004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .enable_reg = 0x1004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .name = "gcc_usb3_sec_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) "gcc_usb3_sec_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .halt_reg = 0x10050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .enable_reg = 0x10050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .name = "gcc_usb3_sec_phy_com_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) "gcc_usb3_sec_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .enable_reg = 0x10054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .name = "gcc_usb3_sec_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .halt_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .hwcg_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .enable_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .name = "gcc_usb_phy_cfg_ahb2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static struct clk_branch gcc_vdda_vs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .halt_reg = 0x7a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .enable_reg = 0x7a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .name = "gcc_vdda_vs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) "gcc_vsensor_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) static struct clk_branch gcc_vddcx_vs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .halt_reg = 0x7a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .enable_reg = 0x7a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .name = "gcc_vddcx_vs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) "gcc_vsensor_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) static struct clk_branch gcc_vddmx_vs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) .halt_reg = 0x7a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .enable_reg = 0x7a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .name = "gcc_vddmx_vs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) "gcc_vsensor_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) static struct clk_branch gcc_video_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .halt_reg = 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .hwcg_reg = 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .enable_reg = 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .name = "gcc_video_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) static struct clk_branch gcc_video_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .halt_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) .enable_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .name = "gcc_video_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static struct clk_branch gcc_video_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) .halt_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) .enable_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) .name = "gcc_video_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) static struct clk_branch gcc_vs_ctrl_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .halt_reg = 0x7a014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) .hwcg_reg = 0x7a014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .enable_reg = 0x7a014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .name = "gcc_vs_ctrl_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) static struct clk_branch gcc_vs_ctrl_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .halt_reg = 0x7a010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) .enable_reg = 0x7a010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) .name = "gcc_vs_ctrl_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) "gcc_vs_ctrl_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) static struct clk_branch gcc_cpuss_dvm_bus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) .halt_reg = 0x48190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) .enable_reg = 0x48190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .name = "gcc_cpuss_dvm_bus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) static struct clk_branch gcc_cpuss_gnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) .halt_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) .hwcg_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .name = "gcc_cpuss_gnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) /* TODO: Remove after DTS updated to protect these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) #ifdef CONFIG_SDM_LPASSCC_845
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) static struct clk_branch gcc_lpass_q6_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) .halt_reg = 0x47000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) .enable_reg = 0x47000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .name = "gcc_lpass_q6_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) static struct clk_branch gcc_lpass_sway_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) .halt_reg = 0x47008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) .enable_reg = 0x47008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .name = "gcc_lpass_sway_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) static struct gdsc pcie_0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .gdscr = 0x6b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) .name = "pcie_0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) static struct gdsc pcie_1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .gdscr = 0x8d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .name = "pcie_1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) static struct gdsc ufs_card_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .gdscr = 0x75004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) .name = "ufs_card_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) static struct gdsc ufs_phy_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) .gdscr = 0x77004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) .name = "ufs_phy_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) static struct gdsc usb30_prim_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .gdscr = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) .name = "usb30_prim_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) static struct gdsc usb30_sec_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) .gdscr = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) .name = "usb30_sec_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) .gdscr = 0x7d030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .gdscr = 0x7d03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) .gdscr = 0x7d034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) .gdscr = 0x7d038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) .gdscr = 0x7d040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) .gdscr = 0x7d048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) .gdscr = 0x7d044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) static struct clk_regmap *gcc_sdm845_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) &gcc_tsif_inactivity_timers_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) &gcc_ufs_card_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) &gcc_ufs_phy_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) &gcc_usb30_prim_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) &gcc_usb30_sec_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) #ifdef CONFIG_SDM_LPASSCC_845
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) static const struct qcom_reset_map gcc_sdm845_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) [GCC_MMSS_BCR] = { 0xb000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) [GCC_PCIE_0_BCR] = { 0x6b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) [GCC_PCIE_1_BCR] = { 0x8d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) [GCC_PCIE_PHY_BCR] = { 0x6f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) [GCC_PDM_BCR] = { 0x33000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) [GCC_PRNG_BCR] = { 0x34000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) [GCC_SDCC2_BCR] = { 0x14000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) [GCC_SDCC4_BCR] = { 0x16000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) [GCC_TSIF_BCR] = { 0x36000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) [GCC_UFS_CARD_BCR] = { 0x75000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) [GCC_UFS_PHY_BCR] = { 0x77000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) [GCC_USB30_PRIM_BCR] = { 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) [GCC_USB30_SEC_BCR] = { 0x10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) static struct gdsc *gcc_sdm845_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) [PCIE_0_GDSC] = &pcie_0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) [PCIE_1_GDSC] = &pcie_1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) [UFS_CARD_GDSC] = &ufs_card_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) [UFS_PHY_GDSC] = &ufs_phy_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) [USB30_SEC_GDSC] = &usb30_sec_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) static const struct regmap_config gcc_sdm845_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) .max_register = 0x182090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) static const struct qcom_cc_desc gcc_sdm845_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) .config = &gcc_sdm845_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) .clks = gcc_sdm845_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) .resets = gcc_sdm845_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) .gdscs = gcc_sdm845_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) static const struct of_device_id gcc_sdm845_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) { .compatible = "qcom,gcc-sdm845" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) static int gcc_sdm845_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) ARRAY_SIZE(gcc_dfs_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) static struct platform_driver gcc_sdm845_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) .probe = gcc_sdm845_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) .name = "gcc-sdm845",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) .of_match_table = gcc_sdm845_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) .sync_state = clk_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) static int __init gcc_sdm845_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) return platform_driver_register(&gcc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) core_initcall(gcc_sdm845_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) static void __exit gcc_sdm845_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) platform_driver_unregister(&gcc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) module_exit(gcc_sdm845_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) MODULE_ALIAS("platform:gcc-sdm845");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags