^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2018, Craig Tatlor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/qcom,gcc-sdm660.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_GPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_GPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_GPLL0_EARLY_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_GPLL1_EARLY_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { P_GPLL0_EARLY_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct parent_map gcc_parent_map_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const char * const gcc_parent_names_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { P_GPLL0_EARLY_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const char * const gcc_parent_names_xo_sleep_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct parent_map gcc_parent_map_xo_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { P_GPLL4, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const char * const gcc_parent_names_xo_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { P_GPLL0_EARLY_DIV, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { P_GPLL1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { P_GPLL4, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { P_GPLL1_EARLY_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "gpll1_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { P_GPLL4, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { P_GPLL0_EARLY_DIV, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { P_GPLL0_EARLY_DIV, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { P_GPLL4, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct clk_fixed_factor xo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .parent_names = (const char *[]){ "xo_board" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clk_alpha_pll gpll0_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "gpll0_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk_fixed_factor gpll0_early_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .parent_names = (const char *[]){ "gpll0_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct clk_alpha_pll_postdiv gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .offset = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .parent_names = (const char *[]){ "gpll0_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct clk_alpha_pll gpll1_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "gpll1_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct clk_fixed_factor gpll1_early_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "gpll1_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .parent_names = (const char *[]){ "gpll1_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct clk_alpha_pll_postdiv gpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .parent_names = (const char *[]){ "gpll1_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct clk_alpha_pll gpll4_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .offset = 0x77000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "gpll4_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct clk_alpha_pll_postdiv gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .offset = 0x77000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .parent_names = (const char *[]) { "gpll4_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .cmd_rcgr = 0x19020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) F(15000000, P_GPLL0, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .cmd_rcgr = 0x1900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .cmd_rcgr = 0x1b020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .cmd_rcgr = 0x1b00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .cmd_rcgr = 0x1d020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .cmd_rcgr = 0x1d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .cmd_rcgr = 0x1f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .cmd_rcgr = 0x1f00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) F(3686400, P_GPLL0, 1, 96, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) F(7372800, P_GPLL0, 1, 192, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) F(14745600, P_GPLL0, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) F(16000000, P_GPLL0, 5, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) F(32000000, P_GPLL0, 1, 4, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) F(40000000, P_GPLL0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) F(46400000, P_GPLL0, 1, 29, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) F(48000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) F(51200000, P_GPLL0, 1, 32, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) F(56000000, P_GPLL0, 1, 7, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) F(58982400, P_GPLL0, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) F(63157895, P_GPLL0, 9.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .cmd_rcgr = 0x1a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .cmd_rcgr = 0x1c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .cmd_rcgr = 0x26020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .name = "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .cmd_rcgr = 0x2600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .name = "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .cmd_rcgr = 0x28020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .name = "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .cmd_rcgr = 0x2800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .cmd_rcgr = 0x2a020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .name = "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .cmd_rcgr = 0x2a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .name = "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .cmd_rcgr = 0x2c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .name = "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .cmd_rcgr = 0x2c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .name = "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .cmd_rcgr = 0x2700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .name = "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .cmd_rcgr = 0x2900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const struct freq_tbl ftbl_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .cmd_rcgr = 0x64004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .cmd_rcgr = 0x65004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .cmd_rcgr = 0x66004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) F(600000000, P_GPLL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static struct clk_rcg2 hmss_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .cmd_rcgr = 0x4805c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .freq_tbl = ftbl_hmss_gpll0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .name = "hmss_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) F(384000000, P_GPLL4, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) F(768000000, P_GPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) F(1536000000, P_GPLL4, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct clk_rcg2 hmss_gpll4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .cmd_rcgr = 0x48074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .parent_map = gcc_parent_map_xo_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .freq_tbl = ftbl_hmss_gpll4_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .name = "hmss_gpll4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .parent_names = gcc_parent_names_xo_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static struct clk_rcg2 hmss_rbcpr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .cmd_rcgr = 0x48044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .parent_map = gcc_parent_map_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .freq_tbl = ftbl_hmss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = "hmss_rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .parent_names = gcc_parent_names_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct freq_tbl ftbl_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .cmd_rcgr = 0x33010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .freq_tbl = ftbl_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) F(160400000, P_GPLL1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) F(267333333, P_GPLL1, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static struct clk_rcg2 qspi_ser_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .cmd_rcgr = 0x4d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .freq_tbl = ftbl_qspi_ser_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .name = "qspi_ser_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) F(192000000, P_GPLL4, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) F(384000000, P_GPLL4, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .cmd_rcgr = 0x1602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .freq_tbl = ftbl_sdcc1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct clk_rcg2 sdcc1_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .cmd_rcgr = 0x16010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .name = "sdcc1_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) F(192000000, P_GPLL4, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .cmd_rcgr = 0x14010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .freq_tbl = ftbl_sdcc2_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) F(240000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static struct clk_rcg2 ufs_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .cmd_rcgr = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .freq_tbl = ftbl_ufs_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .name = "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) F(300000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct clk_rcg2 ufs_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .cmd_rcgr = 0x76010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .freq_tbl = ftbl_ufs_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .name = "ufs_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static struct clk_rcg2 ufs_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .cmd_rcgr = 0x76044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .parent_map = gcc_parent_map_xo_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .freq_tbl = ftbl_hmss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .name = "ufs_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .parent_names = gcc_parent_names_xo_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static struct clk_rcg2 ufs_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .cmd_rcgr = 0x76028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .freq_tbl = ftbl_ufs_unipro_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .name = "ufs_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) F(120000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static struct clk_rcg2 usb20_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .cmd_rcgr = 0x2f010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .freq_tbl = ftbl_usb20_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .name = "usb20_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct clk_rcg2 usb20_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .cmd_rcgr = 0x2f024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .name = "usb20_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) F(120000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) F(133333333, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) F(240000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct clk_rcg2 usb30_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .cmd_rcgr = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .freq_tbl = ftbl_usb30_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .name = "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static struct clk_rcg2 usb30_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .cmd_rcgr = 0xf028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .name = "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) F(1200000, P_XO, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static struct clk_rcg2 usb3_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .cmd_rcgr = 0x5000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .parent_map = gcc_parent_map_xo_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .freq_tbl = ftbl_usb3_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .name = "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .parent_names = gcc_parent_names_xo_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static struct clk_branch gcc_aggre2_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .halt_reg = 0x75034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .enable_reg = 0x75034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .name = "gcc_aggre2_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static struct clk_branch gcc_aggre2_usb3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .halt_reg = 0xf03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .enable_reg = 0xf03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .name = "gcc_aggre2_usb3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static struct clk_branch gcc_bimc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .halt_reg = 0x7106c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .enable_reg = 0x7106c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .name = "gcc_bimc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static struct clk_branch gcc_bimc_hmss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .halt_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .name = "gcc_bimc_hmss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .halt_reg = 0x4401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .enable_reg = 0x4401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .name = "gcc_bimc_mss_q6_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .halt_reg = 0x17004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .halt_reg = 0x19008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .enable_reg = 0x19008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .halt_reg = 0x19004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .enable_reg = 0x19004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .halt_reg = 0x1b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .enable_reg = 0x1b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .halt_reg = 0x1b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .enable_reg = 0x1b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .halt_reg = 0x1d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .enable_reg = 0x1d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .halt_reg = 0x1d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .enable_reg = 0x1d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .halt_reg = 0x1f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .enable_reg = 0x1f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .halt_reg = 0x1f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .enable_reg = 0x1f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .halt_reg = 0x1a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .enable_reg = 0x1a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .halt_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .enable_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static struct clk_branch gcc_blsp2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .halt_reg = 0x25004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .name = "gcc_blsp2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .halt_reg = 0x26008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .enable_reg = 0x26008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .name = "gcc_blsp2_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .halt_reg = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .enable_reg = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .name = "gcc_blsp2_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .halt_reg = 0x28008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enable_reg = 0x28008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .name = "gcc_blsp2_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .halt_reg = 0x28004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .enable_reg = 0x28004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .name = "gcc_blsp2_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .halt_reg = 0x2a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .enable_reg = 0x2a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .name = "gcc_blsp2_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .halt_reg = 0x2a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .enable_reg = 0x2a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .name = "gcc_blsp2_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .halt_reg = 0x2c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enable_reg = 0x2c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .name = "gcc_blsp2_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .halt_reg = 0x2c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .enable_reg = 0x2c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .name = "gcc_blsp2_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static struct clk_branch gcc_blsp2_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .halt_reg = 0x27004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .enable_reg = 0x27004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .name = "gcc_blsp2_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static struct clk_branch gcc_blsp2_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .halt_reg = 0x29004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .enable_reg = 0x29004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .name = "gcc_blsp2_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .halt_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .halt_reg = 0x5058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_reg = 0x5058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .name = "gcc_cfg_noc_usb2_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) "usb20_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .halt_reg = 0x5018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .enable_reg = 0x5018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .name = "gcc_cfg_noc_usb3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static struct clk_branch gcc_dcc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .halt_reg = 0x84004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .enable_reg = 0x84004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .name = "gcc_dcc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .halt_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .enable_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .halt_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .enable_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .halt_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .enable_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static struct clk_branch gcc_gpu_bimc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .halt_reg = 0x71010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .enable_reg = 0x71010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .name = "gcc_gpu_bimc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static struct clk_branch gcc_gpu_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .halt_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .enable_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .name = "gcc_gpu_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static struct clk_branch gcc_gpu_gpll0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .halt_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .name = "gcc_gpu_gpll0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static struct clk_branch gcc_gpu_gpll0_div_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .halt_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .name = "gcc_gpu_gpll0_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static struct clk_branch gcc_hmss_dvm_bus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .halt_reg = 0x4808c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .enable_reg = 0x4808c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .name = "gcc_hmss_dvm_bus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static struct clk_branch gcc_hmss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .halt_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .enable_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .name = "gcc_hmss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) "hmss_rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static struct clk_branch gcc_mmss_gpll0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .halt_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .name = "gcc_mmss_gpll0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static struct clk_branch gcc_mmss_gpll0_div_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .halt_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .name = "gcc_mmss_gpll0_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) "gpll0_early_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .halt_reg = 0x9004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .enable_reg = 0x9004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .name = "gcc_mmss_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .halt_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .enable_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .name = "gcc_mmss_sys_noc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static struct clk_branch gcc_mss_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .halt_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .enable_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .name = "gcc_mss_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .halt_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .hwcg_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .enable_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .name = "gcc_mss_mnoc_bimc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .halt_reg = 0x8a040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .enable_reg = 0x8a040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .name = "gcc_mss_q6_bimc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static struct clk_branch gcc_mss_snoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .halt_reg = 0x8a03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .enable_reg = 0x8a03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .name = "gcc_mss_snoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .halt_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .enable_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .halt_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .enable_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .halt_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static struct clk_branch gcc_qspi_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .halt_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .enable_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .name = "gcc_qspi_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static struct clk_branch gcc_qspi_ser_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .halt_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .enable_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .name = "gcc_qspi_ser_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) "qspi_ser_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) static struct clk_branch gcc_rx0_usb2_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .halt_reg = 0x88018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .enable_reg = 0x88018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .name = "gcc_rx0_usb2_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static struct clk_branch gcc_rx1_usb2_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .halt_reg = 0x88014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .enable_reg = 0x88014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .name = "gcc_rx1_usb2_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .halt_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .enable_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .halt_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .enable_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static struct clk_branch gcc_sdcc1_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .halt_reg = 0x1600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .enable_reg = 0x1600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .name = "gcc_sdcc1_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) "sdcc1_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .halt_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .enable_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .halt_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .enable_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static struct clk_branch gcc_ufs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .halt_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .enable_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .name = "gcc_ufs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static struct clk_branch gcc_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .halt_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .enable_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .name = "gcc_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static struct clk_branch gcc_ufs_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .halt_reg = 0x88008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .enable_reg = 0x88008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .name = "gcc_ufs_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static struct clk_branch gcc_ufs_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .halt_reg = 0x7600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .enable_reg = 0x7600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .name = "gcc_ufs_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) "ufs_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static struct clk_branch gcc_ufs_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .halt_reg = 0x76040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .enable_reg = 0x76040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .name = "gcc_ufs_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) "ufs_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .halt_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .enable_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .name = "gcc_ufs_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .halt_reg = 0x7605c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .enable_reg = 0x7605c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .name = "gcc_ufs_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .name = "gcc_ufs_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static struct clk_branch gcc_ufs_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .halt_reg = 0x76008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .enable_reg = 0x76008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .name = "gcc_ufs_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) "ufs_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) static struct clk_branch gcc_usb20_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .halt_reg = 0x2f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .enable_reg = 0x2f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .name = "gcc_usb20_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) "usb20_master_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static struct clk_branch gcc_usb20_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .halt_reg = 0x2f00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .enable_reg = 0x2f00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .name = "gcc_usb20_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) "usb20_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static struct clk_branch gcc_usb20_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .halt_reg = 0x2f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .enable_reg = 0x2f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .name = "gcc_usb20_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) static struct clk_branch gcc_usb30_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .halt_reg = 0xf008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .enable_reg = 0xf008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .name = "gcc_usb30_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) static struct clk_branch gcc_usb30_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .halt_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .enable_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .name = "gcc_usb30_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static struct clk_branch gcc_usb30_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .halt_reg = 0xf00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .enable_reg = 0xf00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .name = "gcc_usb30_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static struct clk_branch gcc_usb3_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .halt_reg = 0x8800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .enable_reg = 0x8800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .name = "gcc_usb3_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static struct clk_branch gcc_usb3_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .halt_reg = 0x50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .enable_reg = 0x50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .name = "gcc_usb3_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static struct clk_branch gcc_usb3_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .halt_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .enable_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .name = "gcc_usb3_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .halt_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .enable_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .name = "gcc_usb_phy_cfg_ahb2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static struct gdsc ufs_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .gdscr = 0x75004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .gds_hw_ctrl = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .name = "ufs_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static struct gdsc usb_30_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .gdscr = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .gds_hw_ctrl = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .name = "usb_30_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static struct gdsc pcie_0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .gdscr = 0x6b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .gds_hw_ctrl = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .name = "pcie_0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static struct clk_hw *gcc_sdm660_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) &xo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) &gpll0_early_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) &gpll1_early_div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static struct clk_regmap *gcc_sdm660_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) [GPLL0_EARLY] = &gpll0_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) [GPLL1] = &gpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) [GPLL1_EARLY] = &gpll1_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) [GPLL4_EARLY] = &gpll4_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static struct gdsc *gcc_sdm660_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) [UFS_GDSC] = &ufs_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) [USB_30_GDSC] = &usb_30_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) [PCIE_0_GDSC] = &pcie_0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) static const struct qcom_reset_map gcc_sdm660_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) [GCC_UFS_BCR] = { 0x75000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) [GCC_USB3_PHY_BCR] = { 0x50020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) [GCC_USB_20_BCR] = { 0x2f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) [GCC_USB_30_BCR] = { 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) [GCC_MSS_RESTART] = { 0x79000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static const struct regmap_config gcc_sdm660_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .max_register = 0x94000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static const struct qcom_cc_desc gcc_sdm660_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .config = &gcc_sdm660_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .clks = gcc_sdm660_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .num_clks = ARRAY_SIZE(gcc_sdm660_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .resets = gcc_sdm660_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .num_resets = ARRAY_SIZE(gcc_sdm660_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .gdscs = gcc_sdm660_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .clk_hws = gcc_sdm660_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .num_clk_hws = ARRAY_SIZE(gcc_sdm660_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) static const struct of_device_id gcc_sdm660_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) { .compatible = "qcom,gcc-sdm630" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) { .compatible = "qcom,gcc-sdm660" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static int gcc_sdm660_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) * turned off by hardware during certain apps low power modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) static struct platform_driver gcc_sdm660_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .probe = gcc_sdm660_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .name = "gcc-sdm660",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .of_match_table = gcc_sdm660_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static int __init gcc_sdm660_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) return platform_driver_register(&gcc_sdm660_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) core_initcall_sync(gcc_sdm660_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static void __exit gcc_sdm660_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) platform_driver_unregister(&gcc_sdm660_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) module_exit(gcc_sdm660_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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