^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/qcom,gcc-sc7180.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_GPLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_GPLL1_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL4_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL6_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL7_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct clk_alpha_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct clk_div_table post_div_table_gpll0_out_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct clk_alpha_pll_postdiv gpll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .post_div_table = post_div_table_gpll0_out_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "gcc_pll0_main_div_cdiv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clk_alpha_pll gpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .offset = 0x01000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct clk_alpha_pll gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .offset = 0x76000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct clk_alpha_pll gpll6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .offset = 0x13000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct clk_alpha_pll gpll7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .offset = 0x27000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .enable_reg = 0x52010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "gpll7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct parent_map gcc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct clk_parent_data gcc_parent_data_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct clk_parent_data gcc_parent_data_0_ao[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct parent_map gcc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { P_GPLL6_OUT_MAIN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct clk_parent_data gcc_parent_data_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct parent_map gcc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { P_GPLL1_OUT_MAIN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { P_GPLL4_OUT_MAIN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct clk_parent_data gcc_parent_data_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { .hw = &gpll1.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct parent_map gcc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct clk_parent_data gcc_parent_data_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct parent_map gcc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct clk_parent_data gcc_parent_data_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct parent_map gcc_parent_map_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { P_GPLL7_OUT_MAIN, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { P_GPLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct clk_parent_data gcc_parent_data_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .hw = &gpll7.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .hw = &gpll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct parent_map gcc_parent_map_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct clk_parent_data gcc_parent_data_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .cmd_rcgr = 0x48014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "gcc_cpuss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .parent_data = gcc_parent_data_0_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct clk_rcg2 gcc_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .cmd_rcgr = 0x64004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "gcc_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .parent_data = gcc_parent_data_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct clk_rcg2 gcc_gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .cmd_rcgr = 0x65004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "gcc_gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .parent_data = gcc_parent_data_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct clk_rcg2 gcc_gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .cmd_rcgr = 0x66004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .freq_tbl = ftbl_gcc_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .name = "gcc_gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .parent_data = gcc_parent_data_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct clk_rcg2 gcc_pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .cmd_rcgr = 0x33010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .freq_tbl = ftbl_gcc_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .name = "gcc_pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct clk_rcg2 gcc_qspi_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .cmd_rcgr = 0x4b00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .freq_tbl = ftbl_gcc_qspi_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .name = "gcc_qspi_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .parent_data = gcc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .name = "gcc_qupv3_wrap0_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .cmd_rcgr = 0x17034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "gcc_qupv3_wrap0_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .cmd_rcgr = 0x17164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = "gcc_qupv3_wrap0_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .cmd_rcgr = 0x17294,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "gcc_qupv3_wrap0_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .cmd_rcgr = 0x173c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .name = "gcc_qupv3_wrap0_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .cmd_rcgr = 0x174f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .name = "gcc_qupv3_wrap0_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .cmd_rcgr = 0x17624,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .name = "gcc_qupv3_wrap1_s0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .cmd_rcgr = 0x18018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .name = "gcc_qupv3_wrap1_s1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .cmd_rcgr = 0x18148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "gcc_qupv3_wrap1_s2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .cmd_rcgr = 0x18278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .name = "gcc_qupv3_wrap1_s3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .cmd_rcgr = 0x183a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .name = "gcc_qupv3_wrap1_s4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .cmd_rcgr = 0x184d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .name = "gcc_qupv3_wrap1_s5_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .num_parents = ARRAY_SIZE(gcc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .cmd_rcgr = 0x18608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) F(144000, P_BI_TCXO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .cmd_rcgr = 0x12028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = "gcc_sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .parent_data = gcc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .cmd_rcgr = 0x12010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .name = "gcc_sdcc1_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) F(400000, P_BI_TCXO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .cmd_rcgr = 0x1400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .parent_map = gcc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .name = "gcc_sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .parent_data = gcc_parent_data_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .cmd_rcgr = 0x77020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = "gcc_ufs_phy_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .cmd_rcgr = 0x77048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .name = "gcc_ufs_phy_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) F(9600000, P_BI_TCXO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .cmd_rcgr = 0x77098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .name = "gcc_ufs_phy_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .parent_data = gcc_parent_data_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .cmd_rcgr = 0x77060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .name = "gcc_ufs_phy_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .cmd_rcgr = 0xf01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .name = "gcc_usb30_prim_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .cmd_rcgr = 0xf034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .name = "gcc_usb30_prim_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .parent_data = gcc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .cmd_rcgr = 0xf060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .parent_map = gcc_parent_map_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .name = "gcc_usb3_prim_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .parent_data = gcc_parent_data_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) F(4800000, P_BI_TCXO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .cmd_rcgr = 0x3d030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "gcc_sec_ctrl_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .parent_data = gcc_parent_data_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .num_parents = ARRAY_SIZE(gcc_parent_data_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .halt_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .hwcg_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .enable_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .name = "gcc_aggre_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .halt_reg = 0x8201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .enable_reg = 0x8201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .name = "gcc_aggre_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .halt_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .hwcg_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct clk_branch gcc_camera_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .halt_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .hwcg_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .enable_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "gcc_camera_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static struct clk_branch gcc_camera_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .halt_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .enable_reg = 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .name = "gcc_camera_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .halt_reg = 0xb080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .hwcg_reg = 0xb080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .enable_reg = 0xb080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .name = "gcc_camera_throttle_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static struct clk_branch gcc_camera_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .halt_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .enable_reg = 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .name = "gcc_camera_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static struct clk_branch gcc_ce1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .halt_reg = 0x4100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .hwcg_reg = 0x4100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .name = "gcc_ce1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct clk_branch gcc_ce1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .halt_reg = 0x41008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = "gcc_ce1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static struct clk_branch gcc_ce1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .halt_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .name = "gcc_ce1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .halt_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .enable_reg = 0x502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .name = "gcc_cfg_noc_usb3_prim_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* For CPUSS functionality the AHB clock needs to be left enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static struct clk_branch gcc_cpuss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .halt_reg = 0x48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .name = "gcc_cpuss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static struct clk_branch gcc_cpuss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .halt_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .enable_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .name = "gcc_cpuss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static struct clk_branch gcc_ddrss_gpu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .halt_reg = 0x4452c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .enable_reg = 0x4452c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .name = "gcc_ddrss_gpu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static struct clk_branch gcc_disp_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .name = "gcc_disp_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .ops = &clk_branch2_aon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static struct clk_branch gcc_disp_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .name = "gcc_disp_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .hw = &gcc_pll0_main_div_cdiv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static struct clk_branch gcc_disp_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .halt_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .enable_reg = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .name = "gcc_disp_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .halt_reg = 0xb084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .hwcg_reg = 0xb084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .enable_reg = 0xb084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .name = "gcc_disp_throttle_hf_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static struct clk_branch gcc_disp_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .halt_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .enable_reg = 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .name = "gcc_disp_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .halt_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .enable_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .hw = &gcc_gp1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .halt_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .enable_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .hw = &gcc_gp2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .halt_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .enable_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .hw = &gcc_gp3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static struct clk_branch gcc_gpu_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .name = "gcc_gpu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .name = "gcc_gpu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .hw = &gcc_pll0_main_div_cdiv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .halt_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .enable_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .name = "gcc_gpu_memnoc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .halt_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .enable_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .name = "gcc_gpu_snoc_dvm_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static struct clk_branch gcc_npu_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .enable_reg = 0x4d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .name = "gcc_npu_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct clk_branch gcc_npu_bwmon_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .halt_reg = 0x73008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .enable_reg = 0x73008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .name = "gcc_npu_bwmon_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .halt_reg = 0x73018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .enable_reg = 0x73018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .halt_reg = 0x7301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .enable_reg = 0x7301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static struct clk_branch gcc_npu_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .halt_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .hwcg_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .enable_reg = 0x4d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .name = "gcc_npu_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static struct clk_branch gcc_npu_dma_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .halt_reg = 0x4d1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .hwcg_reg = 0x4d1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .enable_reg = 0x4d1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .name = "gcc_npu_dma_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static struct clk_branch gcc_npu_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .name = "gcc_npu_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static struct clk_branch gcc_npu_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .name = "gcc_npu_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .hw = &gcc_pll0_main_div_cdiv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .halt_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .enable_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .hw = &gcc_pdm2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .halt_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .hwcg_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .enable_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static struct clk_branch gcc_pdm_xo4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .halt_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .enable_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .name = "gcc_pdm_xo4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .halt_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .hwcg_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .halt_reg = 0x4b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .hwcg_reg = 0x4b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .enable_reg = 0x4b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .name = "gcc_qspi_cnoc_periph_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static struct clk_branch gcc_qspi_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .halt_reg = 0x4b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .enable_reg = 0x4b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .name = "gcc_qspi_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .hw = &gcc_qspi_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .halt_reg = 0x17014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .name = "gcc_qupv3_wrap0_core_2x_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static struct clk_branch gcc_qupv3_wrap0_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .halt_reg = 0x1700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .name = "gcc_qupv3_wrap0_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .halt_reg = 0x17030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .name = "gcc_qupv3_wrap0_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .halt_reg = 0x17160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .name = "gcc_qupv3_wrap0_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .halt_reg = 0x17290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .name = "gcc_qupv3_wrap0_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .halt_reg = 0x173c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .name = "gcc_qupv3_wrap0_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .halt_reg = 0x174f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .name = "gcc_qupv3_wrap0_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .halt_reg = 0x17620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .name = "gcc_qupv3_wrap0_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .halt_reg = 0x18004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .name = "gcc_qupv3_wrap1_core_2x_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static struct clk_branch gcc_qupv3_wrap1_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .halt_reg = 0x18008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .enable_mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .name = "gcc_qupv3_wrap1_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .halt_reg = 0x18014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .name = "gcc_qupv3_wrap1_s0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .halt_reg = 0x18144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .enable_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .name = "gcc_qupv3_wrap1_s1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .halt_reg = 0x18274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .enable_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .name = "gcc_qupv3_wrap1_s2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .halt_reg = 0x183a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .enable_mask = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .name = "gcc_qupv3_wrap1_s3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .halt_reg = 0x184d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .name = "gcc_qupv3_wrap1_s4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .halt_reg = 0x18604,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .name = "gcc_qupv3_wrap1_s5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .halt_reg = 0x17004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .name = "gcc_qupv3_wrap_0_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .halt_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .hwcg_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .name = "gcc_qupv3_wrap_0_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .halt_reg = 0x1800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .enable_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .name = "gcc_qupv3_wrap_1_m_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .halt_reg = 0x18010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .hwcg_reg = 0x18010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .enable_reg = 0x52008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .name = "gcc_qupv3_wrap_1_s_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .halt_reg = 0x12008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .enable_reg = 0x12008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .halt_reg = 0x1200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .enable_reg = 0x1200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static struct clk_branch gcc_sdcc1_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .halt_reg = 0x12040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .enable_reg = 0x12040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .name = "gcc_sdcc1_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .halt_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .enable_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .halt_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .enable_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .halt_reg = 0x4144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .name = "gcc_sys_noc_cpuss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static struct clk_branch gcc_ufs_mem_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .halt_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .enable_reg = 0x8c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .name = "gcc_ufs_mem_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static struct clk_branch gcc_ufs_phy_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .halt_reg = 0x77014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .hwcg_reg = 0x77014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .enable_reg = 0x77014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .name = "gcc_ufs_phy_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static struct clk_branch gcc_ufs_phy_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .halt_reg = 0x77038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .hwcg_reg = 0x77038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .enable_reg = 0x77038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .name = "gcc_ufs_phy_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static struct clk_branch gcc_ufs_phy_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .halt_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .hwcg_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .enable_reg = 0x77090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .name = "gcc_ufs_phy_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .halt_reg = 0x77094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .hwcg_reg = 0x77094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .enable_reg = 0x77094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .name = "gcc_ufs_phy_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .halt_reg = 0x7701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .enable_reg = 0x7701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .name = "gcc_ufs_phy_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .halt_reg = 0x77018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .enable_reg = 0x77018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .name = "gcc_ufs_phy_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .halt_reg = 0x7708c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .hwcg_reg = 0x7708c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .enable_reg = 0x7708c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .name = "gcc_ufs_phy_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static struct clk_branch gcc_usb30_prim_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .halt_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .enable_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .name = "gcc_usb30_prim_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .halt_reg = 0xf018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .enable_reg = 0xf018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .name = "gcc_usb30_prim_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .hw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static struct clk_branch gcc_usb30_prim_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .halt_reg = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .enable_reg = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .name = "gcc_usb30_prim_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) static struct clk_branch gcc_usb3_prim_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .halt_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .enable_reg = 0x8c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .name = "gcc_usb3_prim_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .halt_reg = 0xf050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .enable_reg = 0xf050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .name = "gcc_usb3_prim_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .halt_reg = 0xf054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .enable_reg = 0xf054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .name = "gcc_usb3_prim_phy_com_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .halt_reg = 0xf058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .enable_reg = 0xf058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .name = "gcc_usb3_prim_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .halt_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .hwcg_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .enable_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .name = "gcc_usb_phy_cfg_ahb2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static struct clk_branch gcc_video_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .halt_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .enable_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .name = "gcc_video_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) static struct clk_branch gcc_video_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .enable_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .name = "gcc_video_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .hw = &gcc_pll0_main_div_cdiv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static struct clk_branch gcc_video_throttle_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .halt_reg = 0xb07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .hwcg_reg = 0xb07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .enable_reg = 0xb07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .name = "gcc_video_throttle_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static struct clk_branch gcc_video_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .halt_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .enable_reg = 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .name = "gcc_video_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static struct clk_branch gcc_mss_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .halt_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .enable_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .name = "gcc_mss_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static struct clk_branch gcc_mss_mfab_axis_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .halt_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .enable_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .name = "gcc_mss_mfab_axis_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static struct clk_branch gcc_mss_nav_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .halt_reg = 0x8a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .enable_reg = 0x8a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .name = "gcc_mss_nav_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static struct clk_branch gcc_mss_snoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .halt_reg = 0x8a150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .enable_reg = 0x8a150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .name = "gcc_mss_snoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .halt_reg = 0x8a154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .enable_reg = 0x8a154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .name = "gcc_mss_q6_memnoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .halt_reg = 0x47018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .enable_reg = 0x47018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .name = "gcc_lpass_cfg_noc_sway_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static struct gdsc ufs_phy_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .gdscr = 0x77004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .name = "ufs_phy_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) static struct gdsc usb30_prim_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .gdscr = 0x0f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .name = "usb30_prim_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .gdscr = 0x7d040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .gdscr = 0x7d044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) static struct gdsc *gcc_sc7180_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) [UFS_PHY_GDSC] = &ufs_phy_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static struct clk_hw *gcc_sc7180_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static struct clk_regmap *gcc_sc7180_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) &gcc_ufs_phy_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) &gcc_usb30_prim_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) [GPLL6] = &gpll6.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) [GPLL7] = &gpll7.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) [GPLL1] = &gpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static const struct qcom_reset_map gcc_sc7180_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) [GCC_UFS_PHY_BCR] = { 0x77000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) [GCC_USB30_PRIM_BCR] = { 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static const struct regmap_config gcc_sc7180_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .max_register = 0x18208c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const struct qcom_cc_desc gcc_sc7180_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .config = &gcc_sc7180_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .clk_hws = gcc_sc7180_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .clks = gcc_sc7180_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .resets = gcc_sc7180_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .gdscs = gcc_sc7180_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static const struct of_device_id gcc_sc7180_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) { .compatible = "qcom,gcc-sc7180" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) static int gcc_sc7180_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) * Disable the GPLL0 active input to MM blocks, NPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) * and GPU via MISC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) * Keep the clocks always-ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_DISP_AHB_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) * GCC_GPU_CFG_AHB_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) ARRAY_SIZE(gcc_dfs_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) static struct platform_driver gcc_sc7180_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .probe = gcc_sc7180_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .name = "gcc-sc7180",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .of_match_table = gcc_sc7180_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) static int __init gcc_sc7180_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) return platform_driver_register(&gcc_sc7180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) core_initcall(gcc_sc7180_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) static void __exit gcc_sc7180_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) platform_driver_unregister(&gcc_sc7180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) module_exit(gcc_sc7180_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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