^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/qcom,gcc-qcs404.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_DSI0_PHY_PLL_OUT_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_DSI0_PHY_PLL_OUT_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_GPLL0_OUT_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL1_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL3_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL4_OUT_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL4_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_GPLL6_OUT_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_HDMI_PHY_PLL_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_PCIE_0_PIPE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct parent_map gcc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char * const gcc_parent_names_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const char * const gcc_parent_names_ao_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "gpll0_ao_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct parent_map gcc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const char * const gcc_parent_names_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct parent_map gcc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { P_GPLL6_OUT_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { P_SLEEP_CLK, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char * const gcc_parent_names_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "gpll6_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct parent_map gcc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { P_GPLL6_OUT_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char * const gcc_parent_names_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "gpll6_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct parent_map gcc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { P_GPLL1_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char * const gcc_parent_names_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "gpll1_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct parent_map gcc_parent_map_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { P_GPLL0_OUT_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char * const gcc_parent_names_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "dsi0pll_byteclk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "gpll0_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct parent_map gcc_parent_map_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { P_GPLL0_OUT_AUX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char * const gcc_parent_names_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "dsi0_phy_pll_out_byteclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "gpll0_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct parent_map gcc_parent_map_7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { P_GPLL3_OUT_MAIN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { P_GPLL6_OUT_AUX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { P_GPLL4_OUT_AUX, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char * const gcc_parent_names_7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "gpll3_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "gpll6_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "gpll4_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct parent_map gcc_parent_map_8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { P_HDMI_PHY_PLL_CLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char * const gcc_parent_names_8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "hdmi_phy_pll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct parent_map gcc_parent_map_9[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { P_GPLL6_OUT_AUX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const char * const gcc_parent_names_9[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "dsi0_phy_pll_out_dsiclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "gpll6_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct parent_map gcc_parent_map_10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { P_SLEEP_CLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const char * const gcc_parent_names_10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct parent_map gcc_parent_map_11[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { P_PCIE_0_PIPE_CLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const gcc_parent_names_11[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct parent_map gcc_parent_map_12[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { P_GPLL0_OUT_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const char * const gcc_parent_names_12[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "dsi0pll_pclk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "gpll0_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct parent_map gcc_parent_map_13[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { P_GPLL4_OUT_MAIN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { P_GPLL6_OUT_AUX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const char * const gcc_parent_names_13[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "gpll4_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "gpll6_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct parent_map gcc_parent_map_14[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { P_GPLL4_OUT_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const char * const gcc_parent_names_14[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "gpll4_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct parent_map gcc_parent_map_15[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { P_GPLL0_OUT_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const char * const gcc_parent_names_15[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "gpll0_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct parent_map gcc_parent_map_16[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { P_GPLL0_OUT_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char * const gcc_parent_names_16[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "gpll0_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct clk_fixed_factor cxo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .parent_names = (const char *[]){ "xo-board" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct clk_alpha_pll gpll0_sleep_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .offset = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .enable_reg = 0x45008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .enable_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .enable_is_inverted = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "gpll0_sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct clk_alpha_pll gpll0_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .offset = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .flags = SUPPORTS_FSM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .parent_names = (const char *[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct clk_alpha_pll gpll0_ao_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .offset = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .flags = SUPPORTS_FSM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .name = "gpll0_ao_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .ops = &clk_alpha_pll_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct clk_alpha_pll gpll1_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .offset = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "gpll1_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* 930MHz configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct alpha_pll_config gpll3_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .l = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .alpha = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .alpha_en_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .post_div_mask = 0xf << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .post_div_val = 0x1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .vco_mask = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .main_output_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .config_ctl_val = 0x4001055b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct pll_vco gpll3_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 700000000, 1400000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct clk_alpha_pll gpll3_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .offset = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .vco_table = gpll3_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .num_vco = ARRAY_SIZE(gpll3_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "gpll3_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct clk_alpha_pll gpll4_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .offset = 0x24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .name = "gpll4_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static struct clk_pll gpll6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .l_reg = 0x37004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .m_reg = 0x37008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .n_reg = 0x3700C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .config_reg = 0x37014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .mode_reg = 0x37000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .status_reg = 0x3701C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .name = "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clk_regmap gpll6_out_aux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = "gpll6_out_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .parent_names = (const char *[]){ "gpll6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct clk_rcg2 apss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .cmd_rcgr = 0x46000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .freq_tbl = ftbl_apss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "apss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .parent_names = gcc_parent_names_ao_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .cmd_rcgr = 0x602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .name = "blsp1_qup0_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .cmd_rcgr = 0x6034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .name = "blsp1_qup0_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .cmd_rcgr = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .cmd_rcgr = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .cmd_rcgr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) F(15000000, P_GPLL0_OUT_MAIN, 1, 3, 160),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) F(30000000, P_GPLL0_OUT_MAIN, 1, 3, 80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .cmd_rcgr = 0x3014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .cmd_rcgr = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .cmd_rcgr = 0x4024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .cmd_rcgr = 0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .cmd_rcgr = 0x5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .cmd_rcgr = 0x600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .name = "blsp1_uart0_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .cmd_rcgr = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .cmd_rcgr = 0x3034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .cmd_rcgr = 0x4014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .cfg_off = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .name = "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .cmd_rcgr = 0xc00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .name = "blsp2_qup0_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .cmd_rcgr = 0xc024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = "blsp2_qup0_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .cmd_rcgr = 0xc044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .name = "blsp2_uart0_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static struct clk_rcg2 byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .cmd_rcgr = 0x4d044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .parent_map = gcc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .name = "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .parent_names = gcc_parent_names_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct freq_tbl ftbl_emac_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) F(5000000, P_GPLL1_OUT_MAIN, 2, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static struct clk_rcg2 emac_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .cmd_rcgr = 0x4e01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .freq_tbl = ftbl_emac_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .name = "emac_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .parent_names = gcc_parent_names_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static struct clk_rcg2 emac_ptp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .cmd_rcgr = 0x4e014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .freq_tbl = ftbl_emac_ptp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .name = "emac_ptp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .parent_names = gcc_parent_names_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const struct freq_tbl ftbl_esc0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static struct clk_rcg2 esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .cmd_rcgr = 0x4d05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .parent_map = gcc_parent_map_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .freq_tbl = ftbl_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .name = "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .parent_names = gcc_parent_names_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static struct clk_rcg2 gfx3d_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .cmd_rcgr = 0x59000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .parent_map = gcc_parent_map_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .freq_tbl = ftbl_gfx3d_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .name = "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .parent_names = gcc_parent_names_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const struct freq_tbl ftbl_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .cmd_rcgr = 0x8004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .cmd_rcgr = 0x9004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .cmd_rcgr = 0xa004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static struct clk_rcg2 hdmi_app_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .cmd_rcgr = 0x4d0e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .freq_tbl = ftbl_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .name = "hdmi_app_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct clk_rcg2 hdmi_pclk_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .cmd_rcgr = 0x4d0dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .parent_map = gcc_parent_map_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .freq_tbl = ftbl_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .name = "hdmi_pclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .parent_names = gcc_parent_names_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const struct freq_tbl ftbl_mdp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static struct clk_rcg2 mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .cmd_rcgr = 0x4d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .parent_map = gcc_parent_map_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .freq_tbl = ftbl_mdp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .name = "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .parent_names = gcc_parent_names_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) F(1200000, P_XO, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static struct clk_rcg2 pcie_0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .cmd_rcgr = 0x3e024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .parent_map = gcc_parent_map_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .freq_tbl = ftbl_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .name = "pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .parent_names = gcc_parent_names_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static struct clk_rcg2 pcie_0_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .cmd_rcgr = 0x3e01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .parent_map = gcc_parent_map_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .freq_tbl = ftbl_pcie_0_pipe_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .name = "pcie_0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .parent_names = gcc_parent_names_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static struct clk_rcg2 pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .cmd_rcgr = 0x4d000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .parent_map = gcc_parent_map_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .name = "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .parent_names = gcc_parent_names_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const struct freq_tbl ftbl_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .cmd_rcgr = 0x44010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .freq_tbl = ftbl_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .cmd_rcgr = 0x42004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .parent_map = gcc_parent_map_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .freq_tbl = ftbl_sdcc1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .parent_names = gcc_parent_names_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static struct clk_rcg2 sdcc1_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .cmd_rcgr = 0x5d000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .name = "sdcc1_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .parent_names = gcc_parent_names_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .cmd_rcgr = 0x43004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .parent_map = gcc_parent_map_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .freq_tbl = ftbl_sdcc2_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .parent_names = gcc_parent_names_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static struct clk_rcg2 usb20_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .cmd_rcgr = 0x41048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .freq_tbl = ftbl_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .name = "usb20_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static struct clk_rcg2 usb30_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .cmd_rcgr = 0x39028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .freq_tbl = ftbl_usb30_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .name = "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static struct clk_rcg2 usb30_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .cmd_rcgr = 0x3901c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .freq_tbl = ftbl_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .name = "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static struct clk_rcg2 usb3_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .cmd_rcgr = 0x3903c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .freq_tbl = ftbl_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .name = "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static struct clk_rcg2 usb_hs_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .cmd_rcgr = 0x41010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .freq_tbl = ftbl_usb_hs_system_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .name = "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .parent_names = gcc_parent_names_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static struct clk_rcg2 vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .cmd_rcgr = 0x4d02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .parent_map = gcc_parent_map_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .freq_tbl = ftbl_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .name = "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .parent_names = gcc_parent_names_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static struct clk_rcg2 cdsp_bimc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .cmd_rcgr = 0x5e010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .parent_map = gcc_parent_map_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .freq_tbl = ftbl_cdsp_bimc_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .name = "cdsp_bimc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .parent_names = gcc_parent_names_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static struct clk_branch gcc_apss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .halt_reg = 0x4601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .name = "gcc_apss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) "apss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct clk_branch gcc_apss_tcu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .halt_reg = 0x5b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .name = "gcc_apss_tcu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static struct clk_branch gcc_bimc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .halt_reg = 0x59034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .enable_reg = 0x59034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .name = "gcc_bimc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "gcc_apss_tcu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static struct clk_branch gcc_bimc_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .halt_reg = 0x59030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .enable_reg = 0x59030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .name = "gcc_bimc_gpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static struct clk_branch gcc_bimc_cdsp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .halt_reg = 0x31030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .enable_reg = 0x31030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .name = "gcc_bimc_cdsp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "cdsp_bimc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static struct clk_branch gcc_bimc_mdss_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .halt_reg = 0x31038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .enable_reg = 0x31038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .name = "gcc_bimc_mdss_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .halt_reg = 0x1008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static struct clk_branch gcc_dcc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .halt_reg = 0x77004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .enable_reg = 0x77004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .name = "gcc_dcc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static struct clk_branch gcc_dcc_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .halt_reg = 0x77008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .enable_reg = 0x77008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .name = "gcc_dcc_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .halt_reg = 0x6028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .enable_reg = 0x6028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .name = "gcc_blsp1_qup0_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "blsp1_qup0_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .halt_reg = 0x6024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .enable_reg = 0x6024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .name = "gcc_blsp1_qup0_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) "blsp1_qup0_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .halt_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .enable_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .halt_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .enable_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .halt_reg = 0x3010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .enable_reg = 0x3010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .halt_reg = 0x300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .enable_reg = 0x300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .halt_reg = 0x4020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .enable_reg = 0x4020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .halt_reg = 0x401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .enable_reg = 0x401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .halt_reg = 0x5020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .enable_reg = 0x5020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .halt_reg = 0x501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .enable_reg = 0x501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static struct clk_branch gcc_blsp1_uart0_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .halt_reg = 0x6004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .enable_reg = 0x6004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .name = "gcc_blsp1_uart0_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) "blsp1_uart0_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .halt_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .enable_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .halt_reg = 0x302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .enable_reg = 0x302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static struct clk_branch gcc_blsp1_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .halt_reg = 0x400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .enable_reg = 0x400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .name = "gcc_blsp1_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static struct clk_branch gcc_blsp2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .halt_reg = 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .enable_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .name = "gcc_blsp2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .halt_reg = 0xc008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .enable_reg = 0xc008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .name = "gcc_blsp2_qup0_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) "blsp2_qup0_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .halt_reg = 0xc004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .enable_reg = 0xc004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .name = "gcc_blsp2_qup0_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) "blsp2_qup0_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static struct clk_branch gcc_blsp2_uart0_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .halt_reg = 0xc03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .enable_reg = 0xc03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .name = "gcc_blsp2_uart0_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) "blsp2_uart0_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .halt_reg = 0x1300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static struct clk_branch gcc_crypto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .halt_reg = 0x16024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .name = "gcc_crypto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static struct clk_branch gcc_crypto_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .halt_reg = 0x16020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .name = "gcc_crypto_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static struct clk_branch gcc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .halt_reg = 0x1601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .name = "gcc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static struct clk_branch gcc_eth_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .halt_reg = 0x4e010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .enable_reg = 0x4e010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .name = "gcc_eth_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static struct clk_branch gcc_eth_ptp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .halt_reg = 0x4e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .enable_reg = 0x4e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .name = "gcc_eth_ptp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) "emac_ptp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static struct clk_branch gcc_eth_rgmii_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .halt_reg = 0x4e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .enable_reg = 0x4e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .name = "gcc_eth_rgmii_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) "emac_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static struct clk_branch gcc_eth_slave_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .halt_reg = 0x4e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .enable_reg = 0x4e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .name = "gcc_eth_slave_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static struct clk_branch gcc_geni_ir_s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .halt_reg = 0xf008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .enable_reg = 0xf008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .name = "gcc_geni_ir_s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static struct clk_branch gcc_geni_ir_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .halt_reg = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .enable_reg = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .name = "gcc_geni_ir_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static struct clk_branch gcc_gfx_tcu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .halt_reg = 0x12020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .enable_reg = 0x4500C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .name = "gcc_gfx_tcu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static struct clk_branch gcc_gfx_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .halt_reg = 0x12010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .enable_reg = 0x4500C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .name = "gcc_gfx_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static struct clk_branch gcc_cdsp_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .halt_reg = 0x1203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .enable_reg = 0x13020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .name = "gcc_cdsp_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) "cdsp_bimc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .halt_reg = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .enable_reg = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .halt_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .enable_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .halt_reg = 0xa000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .enable_reg = 0xa000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static struct clk_branch gcc_gtcu_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .halt_reg = 0x12044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .name = "gcc_gtcu_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct clk_branch gcc_mdp_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .halt_reg = 0x1201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .name = "gcc_mdp_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static struct clk_branch gcc_mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .halt_reg = 0x4d07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .enable_reg = 0x4d07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .name = "gcc_mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static struct clk_branch gcc_mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .halt_reg = 0x4d080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .enable_reg = 0x4d080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .name = "gcc_mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static struct clk_branch gcc_mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .halt_reg = 0x4d094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .enable_reg = 0x4d094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .name = "gcc_mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static struct clk_branch gcc_mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .halt_reg = 0x4d098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .enable_reg = 0x4d098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .name = "gcc_mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static struct clk_branch gcc_mdss_hdmi_app_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .halt_reg = 0x4d0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .enable_reg = 0x4d0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .name = "gcc_mdss_hdmi_app_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) "hdmi_app_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .halt_reg = 0x4d0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .enable_reg = 0x4d0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .name = "gcc_mdss_hdmi_pclk_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) "hdmi_pclk_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static struct clk_branch gcc_mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .halt_reg = 0x4d088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .enable_reg = 0x4d088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .name = "gcc_mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static struct clk_branch gcc_mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .halt_reg = 0x4d084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .enable_reg = 0x4d084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .name = "gcc_mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) static struct clk_branch gcc_mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .halt_reg = 0x4d090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .enable_reg = 0x4d090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .name = "gcc_mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static struct clk_branch gcc_oxili_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .halt_reg = 0x59028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .enable_reg = 0x59028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .name = "gcc_oxili_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static struct clk_branch gcc_oxili_gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .halt_reg = 0x59020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .enable_reg = 0x59020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .name = "gcc_oxili_gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static struct clk_branch gcc_pcie_0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .halt_reg = 0x3e014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .enable_mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .name = "gcc_pcie_0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) "pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .halt_reg = 0x3e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .name = "gcc_pcie_0_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .halt_reg = 0x3e018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .enable_mask = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .name = "gcc_pcie_0_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static struct clk_branch gcc_pcie_0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .halt_reg = 0x3e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .enable_mask = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .name = "gcc_pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) "pcie_0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) static struct clk_branch gcc_pcie_0_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .halt_reg = 0x3e010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .name = "gcc_pcie_0_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static struct clk_branch gcc_pcnoc_usb2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .halt_reg = 0x27008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .enable_reg = 0x27008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .name = "gcc_pcnoc_usb2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static struct clk_branch gcc_pcnoc_usb3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .halt_reg = 0x2700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .enable_reg = 0x2700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .name = "gcc_pcnoc_usb3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .halt_reg = 0x4400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .enable_reg = 0x4400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .halt_reg = 0x44004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .enable_reg = 0x44004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .halt_reg = 0x13004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) /* PWM clks do not have XO as parent as src clk is a balance root */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static struct clk_branch gcc_pwm0_xo512_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .halt_reg = 0x44018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .enable_reg = 0x44018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .name = "gcc_pwm0_xo512_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static struct clk_branch gcc_pwm1_xo512_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .halt_reg = 0x49004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .enable_reg = 0x49004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .name = "gcc_pwm1_xo512_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) static struct clk_branch gcc_pwm2_xo512_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .halt_reg = 0x4a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .enable_reg = 0x4a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .name = "gcc_pwm2_xo512_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static struct clk_branch gcc_qdss_dap_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .halt_reg = 0x29084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .name = "gcc_qdss_dap_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .halt_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .enable_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .halt_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .enable_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) static struct clk_branch gcc_sdcc1_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .halt_reg = 0x5d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .enable_reg = 0x5d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .name = "gcc_sdcc1_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) "sdcc1_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .halt_reg = 0x5e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .enable_reg = 0x5e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .name = "gcc_cdsp_cfg_ahb_cbcr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .halt_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enable_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .halt_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .enable_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) static struct clk_branch gcc_smmu_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .halt_reg = 0x12038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .enable_reg = 0x3600C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .name = "gcc_smmu_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) static struct clk_branch gcc_sys_noc_usb3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .halt_reg = 0x26014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .enable_reg = 0x26014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .name = "gcc_sys_noc_usb3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .halt_reg = 0x4100C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .enable_reg = 0x4100C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .name = "gcc_usb_hs_inactivity_timers_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static struct clk_branch gcc_usb20_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .halt_reg = 0x41044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .enable_reg = 0x41044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .name = "gcc_usb20_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) "usb20_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static struct clk_branch gcc_usb2a_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .halt_reg = 0x4102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .enable_reg = 0x4102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .name = "gcc_usb2a_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) static struct clk_branch gcc_usb30_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .halt_reg = 0x3900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .enable_reg = 0x3900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .name = "gcc_usb30_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static struct clk_branch gcc_usb30_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .halt_reg = 0x39014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .enable_reg = 0x39014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .name = "gcc_usb30_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static struct clk_branch gcc_usb30_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .halt_reg = 0x39010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .enable_reg = 0x39010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .name = "gcc_usb30_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) static struct clk_branch gcc_usb3_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .halt_reg = 0x39044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .enable_reg = 0x39044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .name = "gcc_usb3_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) static struct clk_branch gcc_usb3_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .enable_reg = 0x39018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .name = "gcc_usb3_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .halt_reg = 0x41030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .enable_reg = 0x41030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .name = "gcc_usb_hs_phy_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static struct clk_branch gcc_usb_hs_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .halt_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .enable_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .name = "gcc_usb_hs_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .halt_reg = 0x1e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .enable_reg = 0x1e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .name = "gcc_wdsp_q6ss_ahbs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .halt_reg = 0x1e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .enable_reg = 0x1e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .name = "gcc_wdsp_q6ss_axim_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static struct clk_hw *gcc_qcs404_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) &cxo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static struct clk_regmap *gcc_qcs404_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) [GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) [GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) [GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) [GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) [GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) [GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) [GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) [GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) [GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) [GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) [GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) [GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) [GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) [GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) [GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) [GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) [GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) [GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) [GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) [GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) [GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) [GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) [GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) [GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) [GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) [GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) [GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) [GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) [GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) [GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) [GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) [GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) [GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) [GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) [GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) [GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) [GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) [GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) [GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) [GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) [GCC_GPLL6] = &gpll6.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) [GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) [GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) [GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) [GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) [GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) [GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) [GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) [GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) [GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) [GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) [GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) [GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) [GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) [GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) [GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) [GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) [GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) [GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) [GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) &gcc_usb_hs_inactivity_timers_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) [GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) [GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static const struct qcom_reset_map gcc_qcs404_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) [GCC_GENI_IR_BCR] = { 0x0F000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) [GCC_CDSP_RESTART] = { 0x18000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) [GCC_USB_HS_BCR] = { 0x41000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) [GCC_QUSB2_PHY_BCR] = { 0x4103c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) [GCC_USB3_PHY_BCR] = { 0x39004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) [GCC_USB_30_BCR] = { 0x39000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) [GCC_PCIE_0_BCR] = { 0x3e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) [GCC_EMAC_BCR] = { 0x4e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) [GCC_WDSP_RESTART] = {0x19000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) static const struct regmap_config gcc_qcs404_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .max_register = 0x7f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) static const struct qcom_cc_desc gcc_qcs404_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .config = &gcc_qcs404_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .clks = gcc_qcs404_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .resets = gcc_qcs404_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .num_resets = ARRAY_SIZE(gcc_qcs404_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .clk_hws = gcc_qcs404_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) static const struct of_device_id gcc_qcs404_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) { .compatible = "qcom,gcc-qcs404" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) static int gcc_qcs404_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) static struct platform_driver gcc_qcs404_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .probe = gcc_qcs404_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .name = "gcc-qcs404",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .of_match_table = gcc_qcs404_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) static int __init gcc_qcs404_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) return platform_driver_register(&gcc_qcs404_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) core_initcall(gcc_qcs404_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) static void __exit gcc_qcs404_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) platform_driver_unregister(&gcc_qcs404_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) module_exit(gcc_qcs404_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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