^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-msm8998.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_AUD_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL4_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_PLL0_EARLY_DIV_CLK_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct parent_map gcc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const char * const gcc_parent_names_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct parent_map gcc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char * const gcc_parent_names_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct parent_map gcc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char * const gcc_parent_names_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "core_pi_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct parent_map gcc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { P_SLEEP_CLK, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const gcc_parent_names_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "core_pi_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct parent_map gcc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { P_GPLL4_OUT_MAIN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char * const gcc_parent_names_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "gpll4_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct parent_map gcc_parent_map_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { P_GPLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { P_AUD_REF_CLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const char * const gcc_parent_names_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "aud_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct clk_fixed_factor xo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .parent_names = (const char *[]){ "xo_board" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct pll_vco fabia_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 250000000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 125000000, 1000000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct clk_alpha_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .vco_table = fabia_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .num_vco = ARRAY_SIZE(fabia_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clk_alpha_pll_postdiv gpll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "gpll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct clk_alpha_pll_postdiv gpll0_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "gpll0_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct clk_alpha_pll_postdiv gpll0_out_odd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .name = "gpll0_out_odd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct clk_alpha_pll_postdiv gpll0_out_test = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = "gpll0_out_test",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct clk_alpha_pll gpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .vco_table = fabia_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .num_vco = ARRAY_SIZE(fabia_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct clk_alpha_pll_postdiv gpll1_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "gpll1_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .parent_names = (const char *[]){ "gpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct clk_alpha_pll_postdiv gpll1_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "gpll1_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .parent_names = (const char *[]){ "gpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct clk_alpha_pll_postdiv gpll1_out_odd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = "gpll1_out_odd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .parent_names = (const char *[]){ "gpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct clk_alpha_pll_postdiv gpll1_out_test = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "gpll1_out_test",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .parent_names = (const char *[]){ "gpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct clk_alpha_pll gpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .vco_table = fabia_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_vco = ARRAY_SIZE(fabia_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct clk_alpha_pll_postdiv gpll2_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = "gpll2_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .parent_names = (const char *[]){ "gpll2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct clk_alpha_pll_postdiv gpll2_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "gpll2_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .parent_names = (const char *[]){ "gpll2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct clk_alpha_pll_postdiv gpll2_out_odd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = "gpll2_out_odd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .parent_names = (const char *[]){ "gpll2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct clk_alpha_pll_postdiv gpll2_out_test = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "gpll2_out_test",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .parent_names = (const char *[]){ "gpll2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct clk_alpha_pll gpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .offset = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .vco_table = fabia_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .num_vco = ARRAY_SIZE(fabia_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "gpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct clk_alpha_pll_postdiv gpll3_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .offset = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .name = "gpll3_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .parent_names = (const char *[]){ "gpll3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct clk_alpha_pll_postdiv gpll3_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .offset = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .name = "gpll3_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .parent_names = (const char *[]){ "gpll3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct clk_alpha_pll_postdiv gpll3_out_odd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .offset = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = "gpll3_out_odd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .parent_names = (const char *[]){ "gpll3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct clk_alpha_pll_postdiv gpll3_out_test = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .offset = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .name = "gpll3_out_test",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .parent_names = (const char *[]){ "gpll3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct clk_alpha_pll gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .offset = 0x77000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .vco_table = fabia_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .num_vco = ARRAY_SIZE(fabia_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .enable_reg = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .ops = &clk_alpha_pll_fixed_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct clk_alpha_pll_postdiv gpll4_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .offset = 0x77000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "gpll4_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .parent_names = (const char *[]){ "gpll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct clk_alpha_pll_postdiv gpll4_out_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .offset = 0x77000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "gpll4_out_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .parent_names = (const char *[]){ "gpll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct clk_alpha_pll_postdiv gpll4_out_odd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .offset = 0x77000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "gpll4_out_odd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .parent_names = (const char *[]){ "gpll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct clk_alpha_pll_postdiv gpll4_out_test = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .offset = 0x77000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .name = "gpll4_out_test",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .parent_names = (const char *[]){ "gpll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .cmd_rcgr = 0x19020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .cmd_rcgr = 0x1900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .cmd_rcgr = 0x1b020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .cmd_rcgr = 0x1b00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .cmd_rcgr = 0x1d020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .cmd_rcgr = 0x1d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .cmd_rcgr = 0x1f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .cmd_rcgr = 0x1f00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .cmd_rcgr = 0x21020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .cmd_rcgr = 0x2100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .cmd_rcgr = 0x23020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .cmd_rcgr = 0x2300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .cmd_rcgr = 0x1a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .cmd_rcgr = 0x1c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .cmd_rcgr = 0x1e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .name = "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .cmd_rcgr = 0x26020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .name = "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .cmd_rcgr = 0x2600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .cmd_rcgr = 0x28020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .name = "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .cmd_rcgr = 0x2800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .name = "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .cmd_rcgr = 0x2a020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .name = "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .cmd_rcgr = 0x2a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .name = "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .cmd_rcgr = 0x2c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .name = "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .cmd_rcgr = 0x2c00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .name = "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .cmd_rcgr = 0x2e020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .name = "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .cmd_rcgr = 0x2e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .name = "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .cmd_rcgr = 0x30020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .name = "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .cmd_rcgr = 0x3000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .name = "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .cmd_rcgr = 0x2700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .name = "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .cmd_rcgr = 0x2900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .name = "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .cmd_rcgr = 0x2b00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const struct freq_tbl ftbl_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .cmd_rcgr = 0x64004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .cmd_rcgr = 0x65004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .cmd_rcgr = 0x66004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .parent_map = gcc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .parent_names = gcc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static struct clk_rcg2 hmss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .cmd_rcgr = 0x48014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .freq_tbl = ftbl_hmss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .name = "hmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static struct clk_rcg2 hmss_rbcpr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .cmd_rcgr = 0x48044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .freq_tbl = ftbl_hmss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .name = "hmss_rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) F(1010526, P_XO, 1, 1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static struct clk_rcg2 pcie_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .cmd_rcgr = 0x6c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .freq_tbl = ftbl_pcie_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .name = "pcie_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .parent_names = gcc_parent_names_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const struct freq_tbl ftbl_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .cmd_rcgr = 0x33010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .freq_tbl = ftbl_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .cmd_rcgr = 0x14010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .parent_map = gcc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .freq_tbl = ftbl_sdcc2_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .parent_names = gcc_parent_names_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static struct clk_rcg2 sdcc4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .cmd_rcgr = 0x16010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .parent_map = gcc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .freq_tbl = ftbl_sdcc4_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .name = "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .parent_names = gcc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) F(105495, P_XO, 1, 1, 182),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static struct clk_rcg2 tsif_ref_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .cmd_rcgr = 0x36010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .parent_map = gcc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .freq_tbl = ftbl_tsif_ref_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .name = "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .parent_names = gcc_parent_names_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static struct clk_rcg2 ufs_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .cmd_rcgr = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .freq_tbl = ftbl_ufs_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .name = "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static struct clk_rcg2 ufs_unipro_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .cmd_rcgr = 0x76028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .freq_tbl = ftbl_ufs_unipro_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .name = "ufs_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static struct clk_rcg2 usb30_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .cmd_rcgr = 0xf014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .freq_tbl = ftbl_usb30_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .name = "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static struct clk_rcg2 usb30_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .cmd_rcgr = 0xf028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .parent_map = gcc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .freq_tbl = ftbl_hmss_rbcpr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .name = "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .parent_names = gcc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) F(1200000, P_XO, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static struct clk_rcg2 usb3_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .cmd_rcgr = 0x5000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .parent_map = gcc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .freq_tbl = ftbl_usb3_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .name = "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .parent_names = gcc_parent_names_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static struct clk_branch gcc_aggre1_noc_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .halt_reg = 0x8202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .enable_reg = 0x8202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .name = "gcc_aggre1_noc_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static struct clk_branch gcc_aggre1_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .halt_reg = 0x82028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .enable_reg = 0x82028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .name = "gcc_aggre1_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static struct clk_branch gcc_aggre1_usb3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .halt_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .enable_reg = 0x82024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .name = "gcc_aggre1_usb3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_reg = 0x48090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .enable_reg = 0x48090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .name = "gcc_apss_qdss_tsctr_div2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .halt_reg = 0x48094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .enable_reg = 0x48094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .name = "gcc_apss_qdss_tsctr_div8_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static struct clk_branch gcc_bimc_hmss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .halt_reg = 0x48004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .enable_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .name = "gcc_bimc_hmss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .halt_reg = 0x4401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .enable_reg = 0x4401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .name = "gcc_bimc_mss_q6_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static struct clk_branch gcc_mss_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .halt_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .enable_reg = 0x8a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .name = "gcc_mss_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static struct clk_branch gcc_mss_snoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .halt_reg = 0x8a03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .enable_reg = 0x8a03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .name = "gcc_mss_snoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .halt_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .enable_reg = 0x8a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .name = "gcc_mss_mnoc_bimc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .halt_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .hwcg_reg = 0x38004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .hwcg_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static struct clk_branch gcc_mss_gpll0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .enable_reg = 0x5200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .name = "gcc_mss_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .halt_reg = 0x17004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .halt_reg = 0x19008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .enable_reg = 0x19008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .halt_reg = 0x19004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .enable_reg = 0x19004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .halt_reg = 0x1b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .enable_reg = 0x1b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .halt_reg = 0x1b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .enable_reg = 0x1b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .halt_reg = 0x1d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .enable_reg = 0x1d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .halt_reg = 0x1d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .enable_reg = 0x1d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .halt_reg = 0x1f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .enable_reg = 0x1f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .halt_reg = 0x1f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .enable_reg = 0x1f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .halt_reg = 0x21008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .enable_reg = 0x21008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .halt_reg = 0x21004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .enable_reg = 0x21004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .halt_reg = 0x23008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .enable_reg = 0x23008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .name = "gcc_blsp1_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .halt_reg = 0x23004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .enable_reg = 0x23004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static struct clk_branch gcc_blsp1_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .halt_reg = 0x17008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .name = "gcc_blsp1_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .halt_reg = 0x1a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .enable_reg = 0x1a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .halt_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .enable_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static struct clk_branch gcc_blsp1_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .halt_reg = 0x1e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .enable_reg = 0x1e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .name = "gcc_blsp1_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static struct clk_branch gcc_blsp2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .halt_reg = 0x25004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .name = "gcc_blsp2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .halt_reg = 0x26008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .enable_reg = 0x26008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .name = "gcc_blsp2_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .halt_reg = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .enable_reg = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .name = "gcc_blsp2_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .halt_reg = 0x28008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .enable_reg = 0x28008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .name = "gcc_blsp2_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .halt_reg = 0x28004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .enable_reg = 0x28004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .name = "gcc_blsp2_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .halt_reg = 0x2a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .enable_reg = 0x2a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .name = "gcc_blsp2_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .halt_reg = 0x2a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .enable_reg = 0x2a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .name = "gcc_blsp2_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .halt_reg = 0x2c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .enable_reg = 0x2c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .name = "gcc_blsp2_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .halt_reg = 0x2c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .enable_reg = 0x2c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .name = "gcc_blsp2_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .halt_reg = 0x2e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .enable_reg = 0x2e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .name = "gcc_blsp2_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .halt_reg = 0x2e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .enable_reg = 0x2e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .name = "gcc_blsp2_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .halt_reg = 0x30008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .enable_reg = 0x30008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .name = "gcc_blsp2_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .halt_reg = 0x30004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .enable_reg = 0x30004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .name = "gcc_blsp2_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static struct clk_branch gcc_blsp2_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .halt_reg = 0x25008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .name = "gcc_blsp2_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static struct clk_branch gcc_blsp2_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .halt_reg = 0x27004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .enable_reg = 0x27004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .name = "gcc_blsp2_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static struct clk_branch gcc_blsp2_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .halt_reg = 0x29004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .enable_reg = 0x29004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .name = "gcc_blsp2_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static struct clk_branch gcc_blsp2_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .halt_reg = 0x2b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .enable_reg = 0x2b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .name = "gcc_blsp2_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .halt_reg = 0x5018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .enable_reg = 0x5018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .name = "gcc_cfg_noc_usb3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .halt_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .enable_reg = 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .halt_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .enable_reg = 0x65000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .halt_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .enable_reg = 0x66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static struct clk_branch gcc_bimc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .halt_reg = 0x46040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .enable_reg = 0x46040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .name = "gcc_bimc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static struct clk_branch gcc_gpu_bimc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .halt_reg = 0x71010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .enable_reg = 0x71010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .name = "gcc_gpu_bimc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .halt_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .enable_reg = 0x7100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .name = "gcc_gpu_bimc_gfx_src_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static struct clk_branch gcc_gpu_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .halt_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .enable_reg = 0x71004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .name = "gcc_gpu_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .halt_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .enable_reg = 0x71018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .name = "gcc_gpu_snoc_dvm_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static struct clk_branch gcc_hmss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .halt_reg = 0x48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .enable_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .name = "gcc_hmss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) "hmss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static struct clk_branch gcc_hmss_at_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .halt_reg = 0x48010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .enable_reg = 0x48010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .name = "gcc_hmss_at_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static struct clk_branch gcc_hmss_rbcpr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .halt_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .enable_reg = 0x48008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .name = "gcc_hmss_rbcpr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) "hmss_rbcpr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static struct clk_branch gcc_hmss_trig_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .halt_reg = 0x4800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .enable_reg = 0x4800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .name = "gcc_hmss_trig_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .halt_reg = 0x9004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .enable_reg = 0x9004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .name = "gcc_mmss_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) * Any access to mmss depends on this clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) * Gating this clock has been shown to crash the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * when mmssnoc_axi_rpm_clk is inited in rpmcc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) static struct clk_branch gcc_mmss_qm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .halt_reg = 0x9030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .enable_reg = 0x9030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .name = "gcc_mmss_qm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static struct clk_branch gcc_mmss_qm_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .halt_reg = 0x900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .enable_reg = 0x900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .name = "gcc_mmss_qm_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .halt_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .enable_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .name = "gcc_mmss_sys_noc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static struct clk_branch gcc_mss_at_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .halt_reg = 0x8a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .enable_reg = 0x8a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .name = "gcc_mss_at_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) static struct clk_branch gcc_pcie_0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .halt_reg = 0x6b014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .enable_reg = 0x6b014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .name = "gcc_pcie_0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) "pcie_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .halt_reg = 0x6b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .enable_reg = 0x6b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .name = "gcc_pcie_0_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .halt_reg = 0x6b00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .enable_reg = 0x6b00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .name = "gcc_pcie_0_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static struct clk_branch gcc_pcie_0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .halt_reg = 0x6b018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .enable_reg = 0x6b018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .name = "gcc_pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) static struct clk_branch gcc_pcie_0_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .halt_reg = 0x6b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .enable_reg = 0x6b008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .name = "gcc_pcie_0_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) static struct clk_branch gcc_pcie_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .halt_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .enable_reg = 0x6f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .name = "gcc_pcie_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) "pcie_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .halt_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .enable_reg = 0x3300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .halt_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .enable_reg = 0x33004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) static struct clk_branch gcc_pdm_xo4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .halt_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .enable_reg = 0x33008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .name = "gcc_pdm_xo4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .halt_reg = 0x34004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .enable_reg = 0x52004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .halt_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .enable_reg = 0x14008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .halt_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .enable_reg = 0x14004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) static struct clk_branch gcc_sdcc4_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .halt_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .enable_reg = 0x16008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .name = "gcc_sdcc4_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) static struct clk_branch gcc_sdcc4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .halt_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .enable_reg = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .name = "gcc_sdcc4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static struct clk_branch gcc_tsif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .halt_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .enable_reg = 0x36004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .name = "gcc_tsif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static struct clk_branch gcc_tsif_inactivity_timers_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .halt_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .enable_reg = 0x3600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .name = "gcc_tsif_inactivity_timers_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static struct clk_branch gcc_tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .halt_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .enable_reg = 0x36008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .name = "gcc_tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static struct clk_branch gcc_ufs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .halt_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .enable_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .name = "gcc_ufs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) static struct clk_branch gcc_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .halt_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .enable_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .name = "gcc_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) static struct clk_branch gcc_ufs_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .halt_reg = 0x7600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .enable_reg = 0x7600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .name = "gcc_ufs_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static struct clk_branch gcc_ufs_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .halt_reg = 0x76040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .enable_reg = 0x76040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .name = "gcc_ufs_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .halt_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .enable_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .name = "gcc_ufs_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .halt_reg = 0x7605c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .enable_reg = 0x7605c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .name = "gcc_ufs_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .name = "gcc_ufs_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) static struct clk_branch gcc_ufs_unipro_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .halt_reg = 0x76008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .enable_reg = 0x76008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .name = "gcc_ufs_unipro_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) "ufs_unipro_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static struct clk_branch gcc_usb30_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .halt_reg = 0xf008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .enable_reg = 0xf008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .name = "gcc_usb30_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static struct clk_branch gcc_usb30_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .halt_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .enable_reg = 0xf010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .name = "gcc_usb30_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static struct clk_branch gcc_usb30_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .halt_reg = 0xf00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .enable_reg = 0xf00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .name = "gcc_usb30_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) static struct clk_branch gcc_usb3_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .halt_reg = 0x50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .enable_reg = 0x50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .name = "gcc_usb3_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static struct clk_branch gcc_usb3_phy_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .halt_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .halt_check = BRANCH_HALT_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .enable_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .name = "gcc_usb3_phy_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) .halt_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .enable_reg = 0x6a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .name = "gcc_usb_phy_cfg_ahb2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) static struct clk_branch gcc_hdmi_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .halt_reg = 0x88000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .enable_reg = 0x88000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .name = "gcc_hdmi_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static struct clk_branch gcc_ufs_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .halt_reg = 0x88004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .enable_reg = 0x88004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .name = "gcc_ufs_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static struct clk_branch gcc_usb3_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .halt_reg = 0x88008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .enable_reg = 0x88008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .name = "gcc_usb3_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) static struct clk_branch gcc_pcie_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .halt_reg = 0x8800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .enable_reg = 0x8800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .name = "gcc_pcie_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) static struct clk_branch gcc_rx1_usb2_clkref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .halt_reg = 0x88014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .enable_reg = 0x88014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .name = "gcc_rx1_usb2_clkref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static struct gdsc pcie_0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .gdscr = 0x6b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .gds_hw_ctrl = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .name = "pcie_0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) static struct gdsc ufs_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .gdscr = 0x75004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .gds_hw_ctrl = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .name = "ufs_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) static struct gdsc usb_30_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .gdscr = 0xf004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .gds_hw_ctrl = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .name = "usb_30_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .flags = VOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) static struct clk_regmap *gcc_msm8998_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) [GPLL1] = &gpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) [GPLL2] = &gpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) [GPLL3] = &gpll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static struct gdsc *gcc_msm8998_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) [PCIE_0_GDSC] = &pcie_0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) [UFS_GDSC] = &ufs_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) [USB_30_GDSC] = &usb_30_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) static const struct qcom_reset_map gcc_msm8998_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) [GCC_PCIE_0_BCR] = { 0x6b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) [GCC_PDM_BCR] = { 0x33000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) [GCC_SDCC2_BCR] = { 0x14000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) [GCC_SDCC4_BCR] = { 0x16000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) [GCC_TSIF_BCR] = { 0x36000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) [GCC_UFS_BCR] = { 0x75000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) [GCC_USB_30_BCR] = { 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) [GCC_CONFIG_NOC_BCR] = { 0x5000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) [GCC_IMEM_BCR] = { 0x8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) [GCC_PIMEM_BCR] = { 0xa000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) [GCC_MMSS_BCR] = { 0xb000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) [GCC_QDSS_BCR] = { 0xc000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) [GCC_WCSS_BCR] = { 0x11000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) [GCC_BLSP1_BCR] = { 0x17000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) [GCC_BLSP2_BCR] = { 0x25000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) [GCC_BLSP2_UART1_BCR] = { 0x27000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) [GCC_BLSP2_UART2_BCR] = { 0x29000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) [GCC_PRNG_BCR] = { 0x34000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) [GCC_TSIF_0_RESET] = { 0x36024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) [GCC_TSIF_1_RESET] = { 0x36028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) [GCC_TCSR_BCR] = { 0x37000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) [GCC_BOOT_ROM_BCR] = { 0x38000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) [GCC_MSG_RAM_BCR] = { 0x39000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) [GCC_TLMM_BCR] = { 0x3a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) [GCC_MPM_BCR] = { 0x3b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) [GCC_SEC_CTRL_BCR] = { 0x3d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) [GCC_SPMI_BCR] = { 0x3f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) [GCC_SPDM_BCR] = { 0x40000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) [GCC_CE1_BCR] = { 0x41000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) [GCC_BIMC_BCR] = { 0x44000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) [GCC_APB2JTAG_BCR] = { 0x4c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) [GCC_RBCPR_CX_BCR] = { 0x4e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) [GCC_RBCPR_MX_BCR] = { 0x4f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) [GCC_USB3_PHY_BCR] = { 0x50020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) [GCC_SSC_BCR] = { 0x63000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) [GCC_SSC_RESET] = { 0x63020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) [GCC_PCIE_PHY_BCR] = { 0x6f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) [GCC_GPU_BCR] = { 0x71000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) [GCC_SPSS_BCR] = { 0x72000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) [GCC_OBT_ODT_BCR] = { 0x73000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) [GCC_MSS_RESTART] = { 0x79000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) [GCC_VS_BCR] = { 0x7a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) [GCC_MSS_VS_RESET] = { 0x7a100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) [GCC_GPU_VS_RESET] = { 0x7a104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) [GCC_APC0_VS_RESET] = { 0x7a108 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) [GCC_APC1_VS_RESET] = { 0x7a10c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) [GCC_DCC_BCR] = { 0x84000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) [GCC_IPA_BCR] = { 0x89000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) [GCC_GLM_BCR] = { 0x8b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) [GCC_SKL_BCR] = { 0x8c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) [GCC_MSMPU_BCR] = { 0x8d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) static const struct regmap_config gcc_msm8998_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .max_register = 0x8f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) static struct clk_hw *gcc_msm8998_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) &xo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) static const struct qcom_cc_desc gcc_msm8998_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .config = &gcc_msm8998_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) .clks = gcc_msm8998_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .resets = gcc_msm8998_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .gdscs = gcc_msm8998_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .clk_hws = gcc_msm8998_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) static int gcc_msm8998_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) * turned off by hardware during certain apps low power modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) static const struct of_device_id gcc_msm8998_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) { .compatible = "qcom,gcc-msm8998" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) static struct platform_driver gcc_msm8998_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .probe = gcc_msm8998_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .name = "gcc-msm8998",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .of_match_table = gcc_msm8998_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) .sync_state = clk_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) static int __init gcc_msm8998_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) return platform_driver_register(&gcc_msm8998_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) core_initcall(gcc_msm8998_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) static void __exit gcc_msm8998_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) platform_driver_unregister(&gcc_msm8998_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) module_exit(gcc_msm8998_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) MODULE_ALIAS("platform:gcc-msm8998");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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