^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/qcom,gcc-msm8994.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_GPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct parent_map gcc_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char * const gcc_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { P_GPLL4, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char * const gcc_xo_gpll0_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct clk_fixed_factor xo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .parent_names = (const char *[]) { "xo_board" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct clk_alpha_pll gpll0_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .offset = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .name = "gpll0_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct clk_alpha_pll_postdiv gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .offset = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .parent_names = (const char *[]) { "gpll0_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct clk_alpha_pll gpll4_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .offset = 0x1dc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "gpll4_early",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct clk_alpha_pll_postdiv gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .offset = 0x1dc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .parent_names = (const char *[]) { "gpll4_early" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ops = &clk_alpha_pll_postdiv_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) F(171430000, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) F(240000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct clk_rcg2 ufs_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .cmd_rcgr = 0x1d68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .freq_tbl = ftbl_ufs_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct freq_tbl ftbl_usb30_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) F(125000000, P_GPLL0, 1, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clk_rcg2 usb30_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .cmd_rcgr = 0x03d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .freq_tbl = ftbl_usb30_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .cmd_rcgr = 0x0660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) F(15000000, P_GPLL0, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) F(24000000, P_GPLL0, 12.5, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) F(48000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .cmd_rcgr = 0x064c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .cmd_rcgr = 0x06e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .cmd_rcgr = 0x06cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .cmd_rcgr = 0x0760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .cmd_rcgr = 0x074c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .cmd_rcgr = 0x07e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .cmd_rcgr = 0x07cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .cmd_rcgr = 0x0860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .cmd_rcgr = 0x084c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .cmd_rcgr = 0x08e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .cmd_rcgr = 0x08cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) F(3686400, P_GPLL0, 1, 96, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) F(7372800, P_GPLL0, 1, 192, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) F(14745600, P_GPLL0, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) F(16000000, P_GPLL0, 5, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) F(32000000, P_GPLL0, 1, 4, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) F(40000000, P_GPLL0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) F(46400000, P_GPLL0, 1, 29, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) F(48000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) F(51200000, P_GPLL0, 1, 32, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) F(56000000, P_GPLL0, 1, 7, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) F(58982400, P_GPLL0, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) F(63160000, P_GPLL0, 9.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .cmd_rcgr = 0x068c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .cmd_rcgr = 0x070c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .cmd_rcgr = 0x078c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .cmd_rcgr = 0x080c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .name = "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .cmd_rcgr = 0x088c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .name = "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .cmd_rcgr = 0x090c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .name = "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .cmd_rcgr = 0x09a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .name = "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .cmd_rcgr = 0x098c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .cmd_rcgr = 0x0a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .name = "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .cmd_rcgr = 0x0a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .name = "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .cmd_rcgr = 0x0aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .name = "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .cmd_rcgr = 0x0a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .name = "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .cmd_rcgr = 0x0b20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .name = "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .cmd_rcgr = 0x0b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .name = "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .cmd_rcgr = 0x0ba0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .cmd_rcgr = 0x0b8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .cmd_rcgr = 0x0c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .name = "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .cmd_rcgr = 0x0c0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .cmd_rcgr = 0x09cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .name = "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .cmd_rcgr = 0x0a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .name = "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .cmd_rcgr = 0x0acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .name = "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .cmd_rcgr = 0x0b4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .name = "blsp2_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .cmd_rcgr = 0x0bcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .name = "blsp2_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .cmd_rcgr = 0x0c4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .freq_tbl = ftbl_blsp_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = "blsp2_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct freq_tbl ftbl_gp1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .cmd_rcgr = 0x1904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .freq_tbl = ftbl_gp1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static struct freq_tbl ftbl_gp2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .cmd_rcgr = 0x1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .freq_tbl = ftbl_gp2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct freq_tbl ftbl_gp3_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .cmd_rcgr = 0x1984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .freq_tbl = ftbl_gp3_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) F(1011000, P_XO, 1, 1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static struct clk_rcg2 pcie_0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .cmd_rcgr = 0x1b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .freq_tbl = ftbl_pcie_0_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .name = "pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) F(125000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct clk_rcg2 pcie_0_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .cmd_rcgr = 0x1adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .freq_tbl = ftbl_pcie_pipe_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .name = "pcie_0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) F(1011000, P_XO, 1, 1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static struct clk_rcg2 pcie_1_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .cmd_rcgr = 0x1b80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .freq_tbl = ftbl_pcie_1_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .name = "pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static struct clk_rcg2 pcie_1_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .cmd_rcgr = 0x1b5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .freq_tbl = ftbl_pcie_pipe_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .name = "pcie_1_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static struct freq_tbl ftbl_pdm2_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .cmd_rcgr = 0x0cd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .freq_tbl = ftbl_pdm2_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) F(20000000, P_GPLL0, 15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) F(192000000, P_GPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) F(384000000, P_GPLL4, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .cmd_rcgr = 0x04d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .parent_map = gcc_xo_gpll0_gpll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .freq_tbl = ftbl_sdcc1_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .parent_names = gcc_xo_gpll0_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) F(20000000, P_GPLL0, 15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .cmd_rcgr = 0x0510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct clk_rcg2 sdcc3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .cmd_rcgr = 0x0550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .name = "sdcc3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static struct clk_rcg2 sdcc4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .cmd_rcgr = 0x0590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .name = "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) F(105500, P_XO, 1, 1, 182),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static struct clk_rcg2 tsif_ref_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .cmd_rcgr = 0x0d90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .freq_tbl = ftbl_tsif_ref_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .name = "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static struct clk_rcg2 usb30_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .cmd_rcgr = 0x03e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .name = "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) F(1200000, P_XO, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static struct clk_rcg2 usb3_phy_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .cmd_rcgr = 0x1414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .freq_tbl = ftbl_usb3_phy_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .name = "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .parent_names = (const char *[]) { "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static struct clk_rcg2 usb_hs_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .cmd_rcgr = 0x0490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .freq_tbl = ftbl_usb_hs_system_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .clkr.hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .name = "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .halt_reg = 0x05c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .halt_reg = 0x0648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .enable_reg = 0x0648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .halt_reg = 0x0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .enable_reg = 0x0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .halt_reg = 0x06c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .enable_reg = 0x06c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .halt_reg = 0x06c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .enable_reg = 0x06c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .halt_reg = 0x0748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .enable_reg = 0x0748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .halt_reg = 0x0744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .enable_reg = 0x0744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .halt_reg = 0x07c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .enable_reg = 0x07c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .halt_reg = 0x07c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .enable_reg = 0x07c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .halt_reg = 0x0848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .enable_reg = 0x0848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .halt_reg = 0x0844,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .enable_reg = 0x0844,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .halt_reg = 0x08c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .enable_reg = 0x08c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .name = "gcc_blsp1_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .halt_reg = 0x08c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .enable_reg = 0x08c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .halt_reg = 0x0684,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .enable_reg = 0x0684,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .halt_reg = 0x0704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .enable_reg = 0x0704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static struct clk_branch gcc_blsp1_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .halt_reg = 0x0784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .enable_reg = 0x0784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .name = "gcc_blsp1_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static struct clk_branch gcc_blsp1_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .halt_reg = 0x0804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .enable_reg = 0x0804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .name = "gcc_blsp1_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static struct clk_branch gcc_blsp1_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .halt_reg = 0x0884,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .enable_reg = 0x0884,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .name = "gcc_blsp1_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static struct clk_branch gcc_blsp1_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .halt_reg = 0x0904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .enable_reg = 0x0904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .name = "gcc_blsp1_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static struct clk_branch gcc_blsp2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .halt_reg = 0x0944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .name = "gcc_blsp2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .halt_reg = 0x0988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .enable_reg = 0x0988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .name = "gcc_blsp2_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .halt_reg = 0x0984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .enable_reg = 0x0984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .name = "gcc_blsp2_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .halt_reg = 0x0a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .enable_reg = 0x0a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .name = "gcc_blsp2_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .halt_reg = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_reg = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .name = "gcc_blsp2_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .halt_reg = 0x0a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .enable_reg = 0x0a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .name = "gcc_blsp2_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .halt_reg = 0x0a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .enable_reg = 0x0a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .name = "gcc_blsp2_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .halt_reg = 0x0b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .enable_reg = 0x0b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .name = "gcc_blsp2_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .halt_reg = 0x0b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .enable_reg = 0x0b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .name = "gcc_blsp2_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .halt_reg = 0x0b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .enable_reg = 0x0b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .name = "gcc_blsp2_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .halt_reg = 0x0b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .enable_reg = 0x0b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .name = "gcc_blsp2_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .halt_reg = 0x0c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .enable_reg = 0x0c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .name = "gcc_blsp2_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .halt_reg = 0x0c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .enable_reg = 0x0c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .name = "gcc_blsp2_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static struct clk_branch gcc_blsp2_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .halt_reg = 0x09c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .enable_reg = 0x09c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .name = "gcc_blsp2_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static struct clk_branch gcc_blsp2_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .halt_reg = 0x0a44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .enable_reg = 0x0a44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .name = "gcc_blsp2_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static struct clk_branch gcc_blsp2_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .halt_reg = 0x0ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .enable_reg = 0x0ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .name = "gcc_blsp2_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static struct clk_branch gcc_blsp2_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .halt_reg = 0x0b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .enable_reg = 0x0b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .name = "gcc_blsp2_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) "blsp2_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static struct clk_branch gcc_blsp2_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .halt_reg = 0x0bc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .enable_reg = 0x0bc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .name = "gcc_blsp2_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) "blsp2_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static struct clk_branch gcc_blsp2_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .halt_reg = 0x0c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .enable_reg = 0x0c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .name = "gcc_blsp2_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) "blsp2_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .halt_reg = 0x1900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .enable_reg = 0x1900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .halt_reg = 0x1940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .enable_reg = 0x1940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .halt_reg = 0x1980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .enable_reg = 0x1980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static struct clk_branch gcc_lpass_q6_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .halt_reg = 0x0280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .enable_reg = 0x0280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .name = "gcc_lpass_q6_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .halt_reg = 0x0284,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .enable_reg = 0x0284,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .name = "gcc_mss_q6_bimc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static struct clk_branch gcc_pcie_0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .halt_reg = 0x1ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .enable_reg = 0x1ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .name = "gcc_pcie_0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) "pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .halt_reg = 0x1ad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .enable_reg = 0x1ad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .name = "gcc_pcie_0_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .halt_reg = 0x1acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .enable_reg = 0x1acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .name = "gcc_pcie_0_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static struct clk_branch gcc_pcie_0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .halt_reg = 0x1ad8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .enable_reg = 0x1ad8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .name = "gcc_pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) "pcie_0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static struct clk_branch gcc_pcie_0_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .halt_reg = 0x1ac8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .enable_reg = 0x1ac8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .name = "gcc_pcie_0_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static struct clk_branch gcc_pcie_1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .halt_reg = 0x1b54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .enable_reg = 0x1b54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .name = "gcc_pcie_1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) "pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .halt_reg = 0x1b54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .enable_reg = 0x1b54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .name = "gcc_pcie_1_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .halt_reg = 0x1b50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .enable_reg = 0x1b50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .name = "gcc_pcie_1_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static struct clk_branch gcc_pcie_1_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .halt_reg = 0x1b58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .enable_reg = 0x1b58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .name = "gcc_pcie_1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) "pcie_1_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static struct clk_branch gcc_pcie_1_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .halt_reg = 0x1b48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .enable_reg = 0x1b48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .name = "gcc_pcie_1_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .halt_reg = 0x0ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .enable_reg = 0x0ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .halt_reg = 0x0cc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .enable_reg = 0x0cc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .halt_reg = 0x04c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .enable_reg = 0x04c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .halt_reg = 0x04c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .enable_reg = 0x04c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .halt_reg = 0x0508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .enable_reg = 0x0508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .halt_reg = 0x0504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .enable_reg = 0x0504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static struct clk_branch gcc_sdcc3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .halt_reg = 0x0548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .enable_reg = 0x0548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .name = "gcc_sdcc3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static struct clk_branch gcc_sdcc3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .halt_reg = 0x0544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .enable_reg = 0x0544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .name = "gcc_sdcc3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) "sdcc3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) static struct clk_branch gcc_sdcc4_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .halt_reg = 0x0588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .enable_reg = 0x0588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .name = "gcc_sdcc4_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static struct clk_branch gcc_sdcc4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .halt_reg = 0x0584,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .enable_reg = 0x0584,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .name = "gcc_sdcc4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .halt_reg = 0x1d7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .enable_reg = 0x1d7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .name = "gcc_sys_noc_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .halt_reg = 0x03fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .enable_reg = 0x03fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .name = "gcc_sys_noc_usb3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static struct clk_branch gcc_tsif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .halt_reg = 0x0d84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .enable_reg = 0x0d84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .name = "gcc_tsif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static struct clk_branch gcc_tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .halt_reg = 0x0d88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .enable_reg = 0x0d88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .name = "gcc_tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static struct clk_branch gcc_ufs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .halt_reg = 0x1d4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .enable_reg = 0x1d4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .name = "gcc_ufs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static struct clk_branch gcc_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .halt_reg = 0x1d48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .enable_reg = 0x1d48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .name = "gcc_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) static struct clk_branch gcc_ufs_rx_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .halt_reg = 0x1d54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .enable_reg = 0x1d54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .name = "gcc_ufs_rx_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .halt_reg = 0x1d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .enable_reg = 0x1d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .name = "gcc_ufs_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .halt_reg = 0x1d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .enable_reg = 0x1d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .name = "gcc_ufs_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static struct clk_branch gcc_ufs_tx_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .halt_reg = 0x1d50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .enable_reg = 0x1d50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .name = "gcc_ufs_tx_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .halt_reg = 0x1d58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .enable_reg = 0x1d58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .name = "gcc_ufs_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .halt_reg = 0x1d5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .enable_reg = 0x1d5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .name = "gcc_ufs_tx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .halt_reg = 0x04ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .enable_reg = 0x04ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .name = "gcc_usb2_hs_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static struct clk_branch gcc_usb30_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .halt_reg = 0x03c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .enable_reg = 0x03c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .name = "gcc_usb30_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) static struct clk_branch gcc_usb30_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .halt_reg = 0x03d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .enable_reg = 0x03d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .name = "gcc_usb30_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static struct clk_branch gcc_usb30_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .halt_reg = 0x03cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .enable_reg = 0x03cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .name = "gcc_usb30_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static struct clk_branch gcc_usb3_phy_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .halt_reg = 0x1408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .enable_reg = 0x1408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .name = "gcc_usb3_phy_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) "usb3_phy_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static struct clk_branch gcc_usb_hs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .halt_reg = 0x0488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .enable_reg = 0x0488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .name = "gcc_usb_hs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) static struct clk_branch gcc_usb_hs_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .halt_reg = 0x0484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .enable_reg = 0x0484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .name = "gcc_usb_hs_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .parent_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .halt_reg = 0x1a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .enable_reg = 0x1a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .hw.init = &(struct clk_init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .name = "gcc_usb_phy_cfg_ahb2phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static struct gdsc pcie_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .gdscr = 0x1e18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .name = "pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) static struct gdsc pcie_0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .gdscr = 0x1ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .name = "pcie_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static struct gdsc pcie_1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .gdscr = 0x1b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .name = "pcie_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) static struct gdsc usb30_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .gdscr = 0x3c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .name = "usb30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static struct gdsc ufs_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .gdscr = 0x1d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .name = "ufs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static struct clk_regmap *gcc_msm8994_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) [GPLL0_EARLY] = &gpll0_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) [GPLL4_EARLY] = &gpll4_early.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) static struct gdsc *gcc_msm8994_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) [PCIE_GDSC] = &pcie_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) [PCIE_0_GDSC] = &pcie_0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) [PCIE_1_GDSC] = &pcie_1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) [USB30_GDSC] = &usb30_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) [UFS_GDSC] = &ufs_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static const struct qcom_reset_map gcc_msm8994_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) [USB3_PHY_RESET] = { 0x1400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) [USB3PHY_PHY_RESET] = { 0x1404 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) [PCIE_PHY_0_RESET] = { 0x1b18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) [PCIE_PHY_1_RESET] = { 0x1b98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) [QUSB2_PHY_RESET] = { 0x04b8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const struct regmap_config gcc_msm8994_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .max_register = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static const struct qcom_cc_desc gcc_msm8994_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .config = &gcc_msm8994_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .clks = gcc_msm8994_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .resets = gcc_msm8994_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .gdscs = gcc_msm8994_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static const struct of_device_id gcc_msm8994_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) { .compatible = "qcom,gcc-msm8994" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static int gcc_msm8994_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) clk = devm_clk_register(dev, &xo.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return qcom_cc_probe(pdev, &gcc_msm8994_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static struct platform_driver gcc_msm8994_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .probe = gcc_msm8994_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .name = "gcc-msm8994",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .of_match_table = gcc_msm8994_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static int __init gcc_msm8994_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) return platform_driver_register(&gcc_msm8994_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) core_initcall(gcc_msm8994_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static void __exit gcc_msm8994_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) platform_driver_unregister(&gcc_msm8994_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) module_exit(gcc_msm8994_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) MODULE_ALIAS("platform:gcc-msm8994");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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