^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-msm8974.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,gcc-msm8974.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct parent_map gcc_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { P_GPLL0, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const char * const gcc_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { P_GPLL4, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char * const gcc_xo_gpll0_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "gpll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct clk_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .l_reg = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .m_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .n_reg = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .config_reg = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .mode_reg = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .status_reg = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct clk_regmap gpll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct clk_rcg2 config_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .cmd_rcgr = 0x0150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct clk_rcg2 periph_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .cmd_rcgr = 0x0190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct clk_rcg2 system_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .cmd_rcgr = 0x0120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct clk_pll gpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .l_reg = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .m_reg = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .n_reg = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .config_reg = 0x0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .mode_reg = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .status_reg = 0x005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct clk_regmap gpll1_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .parent_names = (const char *[]){ "gpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct clk_pll gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .l_reg = 0x1dc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .m_reg = 0x1dc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .n_reg = 0x1dcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .config_reg = 0x1dd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .mode_reg = 0x1dc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .status_reg = 0x1ddc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct clk_regmap gpll4_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .name = "gpll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .parent_names = (const char *[]){ "gpll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) F(125000000, P_GPLL0, 1, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct clk_rcg2 usb30_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .cmd_rcgr = 0x03d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .freq_tbl = ftbl_gcc_usb30_master_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) F(37500000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .cmd_rcgr = 0x0660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) F(15000000, P_GPLL0, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .cmd_rcgr = 0x064c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .cmd_rcgr = 0x06e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .cmd_rcgr = 0x06cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .cmd_rcgr = 0x0760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .cmd_rcgr = 0x074c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .cmd_rcgr = 0x07e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .cmd_rcgr = 0x07cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .cmd_rcgr = 0x0860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .cmd_rcgr = 0x084c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .cmd_rcgr = 0x08e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .cmd_rcgr = 0x08cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) F(3686400, P_GPLL0, 1, 96, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) F(7372800, P_GPLL0, 1, 192, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) F(14745600, P_GPLL0, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) F(16000000, P_GPLL0, 5, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) F(32000000, P_GPLL0, 1, 4, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) F(40000000, P_GPLL0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) F(46400000, P_GPLL0, 1, 29, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) F(48000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) F(51200000, P_GPLL0, 1, 32, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) F(56000000, P_GPLL0, 1, 7, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) F(58982400, P_GPLL0, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) F(63160000, P_GPLL0, 9.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .cmd_rcgr = 0x068c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .cmd_rcgr = 0x070c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .cmd_rcgr = 0x078c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .name = "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .cmd_rcgr = 0x080c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .cmd_rcgr = 0x088c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .name = "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .cmd_rcgr = 0x090c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .cmd_rcgr = 0x09a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .cmd_rcgr = 0x098c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .name = "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .cmd_rcgr = 0x0a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .cmd_rcgr = 0x0a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .name = "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .cmd_rcgr = 0x0aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .cmd_rcgr = 0x0a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .name = "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .cmd_rcgr = 0x0b20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .cmd_rcgr = 0x0b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .cmd_rcgr = 0x0ba0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .name = "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .cmd_rcgr = 0x0b8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .cmd_rcgr = 0x0c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .name = "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .cmd_rcgr = 0x0c0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .cmd_rcgr = 0x09cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .name = "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .cmd_rcgr = 0x0a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .cmd_rcgr = 0x0acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .cmd_rcgr = 0x0b4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .name = "blsp2_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .cmd_rcgr = 0x0bcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .name = "blsp2_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .cmd_rcgr = 0x0c4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .name = "blsp2_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static struct clk_rcg2 ce1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .cmd_rcgr = 0x1050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .freq_tbl = ftbl_gcc_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .name = "ce1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) F(150000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct clk_rcg2 ce2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .cmd_rcgr = 0x1090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .freq_tbl = ftbl_gcc_ce2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "ce2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const struct freq_tbl ftbl_gcc_gp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) F(6000000, P_GPLL0, 10, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) F(6750000, P_GPLL0, 1, 1, 89),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) F(8000000, P_GPLL0, 15, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) F(16000000, P_GPLL0, 1, 2, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .cmd_rcgr = 0x1904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .cmd_rcgr = 0x1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .cmd_rcgr = 0x1984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .cmd_rcgr = 0x0cd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .freq_tbl = ftbl_gcc_pdm2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) F(20000000, P_GPLL0, 15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) F(20000000, P_GPLL0, 15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) F(192000000, P_GPLL4, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) F(384000000, P_GPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static struct clk_init_data sdcc1_apps_clk_src_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .cmd_rcgr = 0x04d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .clkr.hw.init = &sdcc1_apps_clk_src_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .cmd_rcgr = 0x0510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static struct clk_rcg2 sdcc3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .cmd_rcgr = 0x0550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .name = "sdcc3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static struct clk_rcg2 sdcc4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .cmd_rcgr = 0x0590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .name = "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) F(105000, P_XO, 2, 1, 91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static struct clk_rcg2 tsif_ref_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .cmd_rcgr = 0x0d90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .freq_tbl = ftbl_gcc_tsif_ref_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .name = "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static struct clk_rcg2 usb30_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .cmd_rcgr = 0x03e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .name = "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static struct clk_rcg2 usb_hs_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .cmd_rcgr = 0x0490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .freq_tbl = ftbl_gcc_usb_hs_system_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .name = "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) F(480000000, P_GPLL1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const struct parent_map usb_hsic_clk_src_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) { P_GPLL1, 4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static struct clk_rcg2 usb_hsic_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .cmd_rcgr = 0x0440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .parent_map = usb_hsic_clk_src_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .freq_tbl = ftbl_gcc_usb_hsic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .name = "usb_hsic_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .cmd_rcgr = 0x0458,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .name = "usb_hsic_io_cal_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static struct clk_rcg2 usb_hsic_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .cmd_rcgr = 0x041c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .name = "usb_hsic_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static struct clk_regmap gcc_mmss_gpll0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .enable_mask = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .name = "mmss_gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .ops = &clk_branch_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static struct clk_branch gcc_bam_dma_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .halt_reg = 0x0d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .name = "gcc_bam_dma_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .halt_reg = 0x05c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .halt_reg = 0x0648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .enable_reg = 0x0648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .halt_reg = 0x0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .enable_reg = 0x0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .halt_reg = 0x06c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .enable_reg = 0x06c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .halt_reg = 0x06c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .enable_reg = 0x06c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .halt_reg = 0x0748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .enable_reg = 0x0748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .halt_reg = 0x0744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .enable_reg = 0x0744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .halt_reg = 0x07c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .enable_reg = 0x07c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .halt_reg = 0x07c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .enable_reg = 0x07c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .halt_reg = 0x0848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .enable_reg = 0x0848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_reg = 0x0844,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .enable_reg = 0x0844,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .halt_reg = 0x08c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .enable_reg = 0x08c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .name = "gcc_blsp1_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .halt_reg = 0x08c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .enable_reg = 0x08c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .halt_reg = 0x0684,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .enable_reg = 0x0684,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .halt_reg = 0x0704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .enable_reg = 0x0704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static struct clk_branch gcc_blsp1_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .halt_reg = 0x0784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .enable_reg = 0x0784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .name = "gcc_blsp1_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static struct clk_branch gcc_blsp1_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .halt_reg = 0x0804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .enable_reg = 0x0804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .name = "gcc_blsp1_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static struct clk_branch gcc_blsp1_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .halt_reg = 0x0884,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .enable_reg = 0x0884,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .name = "gcc_blsp1_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static struct clk_branch gcc_blsp1_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .halt_reg = 0x0904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .enable_reg = 0x0904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .name = "gcc_blsp1_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static struct clk_branch gcc_blsp2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .halt_reg = 0x0944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .name = "gcc_blsp2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .halt_reg = 0x0988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .enable_reg = 0x0988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .name = "gcc_blsp2_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .halt_reg = 0x0984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .enable_reg = 0x0984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .name = "gcc_blsp2_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .halt_reg = 0x0a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .enable_reg = 0x0a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .name = "gcc_blsp2_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .halt_reg = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .enable_reg = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .name = "gcc_blsp2_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .halt_reg = 0x0a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .enable_reg = 0x0a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .name = "gcc_blsp2_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .halt_reg = 0x0a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .enable_reg = 0x0a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .name = "gcc_blsp2_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .halt_reg = 0x0b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_reg = 0x0b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .name = "gcc_blsp2_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .halt_reg = 0x0b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .enable_reg = 0x0b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .name = "gcc_blsp2_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .halt_reg = 0x0b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_reg = 0x0b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .name = "gcc_blsp2_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .halt_reg = 0x0b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .enable_reg = 0x0b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .name = "gcc_blsp2_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .halt_reg = 0x0c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .enable_reg = 0x0c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .name = "gcc_blsp2_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .halt_reg = 0x0c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .enable_reg = 0x0c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .name = "gcc_blsp2_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static struct clk_branch gcc_blsp2_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .halt_reg = 0x09c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .enable_reg = 0x09c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .name = "gcc_blsp2_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static struct clk_branch gcc_blsp2_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .halt_reg = 0x0a44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .enable_reg = 0x0a44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .name = "gcc_blsp2_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static struct clk_branch gcc_blsp2_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .halt_reg = 0x0ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .enable_reg = 0x0ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .name = "gcc_blsp2_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static struct clk_branch gcc_blsp2_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .halt_reg = 0x0b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .enable_reg = 0x0b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .name = "gcc_blsp2_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) "blsp2_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static struct clk_branch gcc_blsp2_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .halt_reg = 0x0bc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .enable_reg = 0x0bc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .name = "gcc_blsp2_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) "blsp2_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static struct clk_branch gcc_blsp2_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .halt_reg = 0x0c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .enable_reg = 0x0c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .name = "gcc_blsp2_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) "blsp2_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .halt_reg = 0x0e04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static struct clk_branch gcc_ce1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .halt_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .name = "gcc_ce1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static struct clk_branch gcc_ce1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .halt_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .name = "gcc_ce1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static struct clk_branch gcc_ce1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .halt_reg = 0x1050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .name = "gcc_ce1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) "ce1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static struct clk_branch gcc_ce2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .halt_reg = 0x108c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .name = "gcc_ce2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static struct clk_branch gcc_ce2_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .halt_reg = 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .name = "gcc_ce2_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static struct clk_branch gcc_ce2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .halt_reg = 0x1090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .name = "gcc_ce2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) "ce2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .halt_reg = 0x1900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .enable_reg = 0x1900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .halt_reg = 0x1940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .enable_reg = 0x1940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .halt_reg = 0x1980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .enable_reg = 0x1980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static struct clk_branch gcc_lpass_q6_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .halt_reg = 0x11c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .enable_reg = 0x11c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .name = "gcc_lpass_q6_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .halt_reg = 0x024c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .enable_reg = 0x024c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .name = "gcc_mmss_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .halt_reg = 0x0248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .enable_reg = 0x0248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .name = "gcc_ocmem_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) static struct clk_branch gcc_mss_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .halt_reg = 0x0280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .enable_reg = 0x0280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .name = "gcc_mss_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .halt_reg = 0x0284,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .enable_reg = 0x0284,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .name = "gcc_mss_q6_bimc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .halt_reg = 0x0ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .enable_reg = 0x0ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .halt_reg = 0x0cc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .enable_reg = 0x0cc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .halt_reg = 0x0d04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .halt_reg = 0x04c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .enable_reg = 0x04c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .halt_reg = 0x04c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .enable_reg = 0x04c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .halt_reg = 0x04e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .enable_reg = 0x04e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .name = "gcc_sdcc1_cdccal_ff_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .halt_reg = 0x04e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .enable_reg = 0x04e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .name = "gcc_sdcc1_cdccal_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) "sleep_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .halt_reg = 0x0508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .enable_reg = 0x0508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .halt_reg = 0x0504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .enable_reg = 0x0504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static struct clk_branch gcc_sdcc3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .halt_reg = 0x0548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .enable_reg = 0x0548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .name = "gcc_sdcc3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) static struct clk_branch gcc_sdcc3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .halt_reg = 0x0544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .enable_reg = 0x0544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .name = "gcc_sdcc3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) "sdcc3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) static struct clk_branch gcc_sdcc4_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .halt_reg = 0x0588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .enable_reg = 0x0588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .name = "gcc_sdcc4_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static struct clk_branch gcc_sdcc4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .halt_reg = 0x0584,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .enable_reg = 0x0584,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .name = "gcc_sdcc4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .halt_reg = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .enable_reg = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .name = "gcc_sys_noc_usb3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static struct clk_branch gcc_tsif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .halt_reg = 0x0d84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .enable_reg = 0x0d84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .name = "gcc_tsif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) static struct clk_branch gcc_tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .halt_reg = 0x0d88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .enable_reg = 0x0d88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .name = "gcc_tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static struct clk_branch gcc_usb2a_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .halt_reg = 0x04ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .enable_reg = 0x04ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .name = "gcc_usb2a_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static struct clk_branch gcc_usb2b_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .halt_reg = 0x04b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .enable_reg = 0x04b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .name = "gcc_usb2b_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) static struct clk_branch gcc_usb30_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .halt_reg = 0x03c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .enable_reg = 0x03c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .name = "gcc_usb30_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) static struct clk_branch gcc_usb30_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .halt_reg = 0x03d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .enable_reg = 0x03d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .name = "gcc_usb30_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static struct clk_branch gcc_usb30_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .halt_reg = 0x03cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .enable_reg = 0x03cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .name = "gcc_usb30_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static struct clk_branch gcc_usb_hs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .halt_reg = 0x0488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .enable_reg = 0x0488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .name = "gcc_usb_hs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static struct clk_branch gcc_usb_hs_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .halt_reg = 0x0484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .enable_reg = 0x0484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .name = "gcc_usb_hs_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) static struct clk_branch gcc_usb_hsic_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .halt_reg = 0x0408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .enable_reg = 0x0408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .name = "gcc_usb_hsic_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) static struct clk_branch gcc_usb_hsic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .halt_reg = 0x0410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .enable_reg = 0x0410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .name = "gcc_usb_hsic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) "usb_hsic_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static struct clk_branch gcc_usb_hsic_io_cal_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .halt_reg = 0x0414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .enable_reg = 0x0414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .name = "gcc_usb_hsic_io_cal_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) "usb_hsic_io_cal_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .halt_reg = 0x0418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .enable_reg = 0x0418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .name = "gcc_usb_hsic_io_cal_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static struct clk_branch gcc_usb_hsic_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .halt_reg = 0x040c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .enable_reg = 0x040c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .name = "gcc_usb_hsic_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "usb_hsic_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static struct gdsc usb_hs_hsic_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .gdscr = 0x404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .name = "usb_hs_hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static struct clk_regmap *gcc_msm8974_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) [GPLL0_VOTE] = &gpll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) [GPLL1] = &gpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) [GPLL1_VOTE] = &gpll1_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) [CE1_CLK_SRC] = &ce1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) [CE2_CLK_SRC] = &ce2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) [GPLL4] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) [GPLL4_VOTE] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) [GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) static const struct qcom_reset_map gcc_msm8974_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) [GCC_CONFIG_NOC_BCR] = { 0x0140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) [GCC_PERIPH_NOC_BCR] = { 0x0180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) [GCC_IMEM_BCR] = { 0x0200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) [GCC_MMSS_BCR] = { 0x0240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) [GCC_QDSS_BCR] = { 0x0300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) [GCC_USB_30_BCR] = { 0x03c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) [GCC_USB3_PHY_BCR] = { 0x03fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) [GCC_USB_HS_BCR] = { 0x0480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) [GCC_USB2A_PHY_BCR] = { 0x04a8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) [GCC_USB2B_PHY_BCR] = { 0x04b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) [GCC_SDCC1_BCR] = { 0x04c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) [GCC_SDCC2_BCR] = { 0x0500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) [GCC_SDCC3_BCR] = { 0x0540 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) [GCC_SDCC4_BCR] = { 0x0580 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) [GCC_BLSP1_BCR] = { 0x05c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) [GCC_BLSP1_UART1_BCR] = { 0x0680 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) [GCC_BLSP1_UART2_BCR] = { 0x0700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) [GCC_BLSP1_UART3_BCR] = { 0x0780 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) [GCC_BLSP1_UART4_BCR] = { 0x0800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) [GCC_BLSP1_UART5_BCR] = { 0x0880 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) [GCC_BLSP1_UART6_BCR] = { 0x0900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) [GCC_BLSP2_BCR] = { 0x0940 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) [GCC_PDM_BCR] = { 0x0cc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) [GCC_BAM_DMA_BCR] = { 0x0d40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) [GCC_TSIF_BCR] = { 0x0d80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) [GCC_TCSR_BCR] = { 0x0dc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) [GCC_BOOT_ROM_BCR] = { 0x0e00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) [GCC_MSG_RAM_BCR] = { 0x0e40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) [GCC_TLMM_BCR] = { 0x0e80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) [GCC_MPM_BCR] = { 0x0ec0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) [GCC_SEC_CTRL_BCR] = { 0x0f40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) [GCC_SPMI_BCR] = { 0x0fc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) [GCC_SPDM_BCR] = { 0x1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) [GCC_CE1_BCR] = { 0x1040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) [GCC_CE2_BCR] = { 0x1080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) [GCC_BIMC_BCR] = { 0x1100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) [GCC_DEHR_BCR] = { 0x1300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) [GCC_RBCPR_BCR] = { 0x1380 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) [GCC_MSS_RESTART] = { 0x1680 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) [GCC_LPASS_RESTART] = { 0x16c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) [GCC_WCSS_RESTART] = { 0x1700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) [GCC_VENUS_RESTART] = { 0x1740 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static struct gdsc *gcc_msm8974_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static const struct regmap_config gcc_msm8974_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .max_register = 0x1fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) static const struct qcom_cc_desc gcc_msm8974_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .config = &gcc_msm8974_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .clks = gcc_msm8974_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .resets = gcc_msm8974_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .num_resets = ARRAY_SIZE(gcc_msm8974_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .gdscs = gcc_msm8974_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static const struct of_device_id gcc_msm8974_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) { .compatible = "qcom,gcc-msm8974" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) static void msm8974_pro_clock_override(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) sdcc1_apps_clk_src_init.num_parents = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) &gcc_sdcc1_cdccal_sleep_clk.clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) &gcc_sdcc1_cdccal_ff_clk.clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) static int gcc_msm8974_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) bool pro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) id = of_match_device(gcc_msm8974_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) pro = !!(id->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) if (pro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) msm8974_pro_clock_override();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ret = qcom_cc_register_sleep_clk(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return qcom_cc_probe(pdev, &gcc_msm8974_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) static struct platform_driver gcc_msm8974_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .probe = gcc_msm8974_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .name = "gcc-msm8974",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .of_match_table = gcc_msm8974_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static int __init gcc_msm8974_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) return platform_driver_register(&gcc_msm8974_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) core_initcall(gcc_msm8974_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) static void __exit gcc_msm8974_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) platform_driver_unregister(&gcc_msm8974_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) module_exit(gcc_msm8974_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) MODULE_ALIAS("platform:gcc-msm8974");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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