^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-msm8960.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,gcc-msm8960.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk-hfpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct clk_pll pll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .l_reg = 0x3164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .m_reg = 0x3168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .n_reg = 0x316c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .config_reg = 0x3174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .mode_reg = 0x3160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .status_reg = 0x3178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = "pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct clk_regmap pll4_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "pll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .parent_names = (const char *[]){ "pll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct clk_pll pll8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .l_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .m_reg = 0x3148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .n_reg = 0x314c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .config_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .mode_reg = 0x3140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .status_reg = 0x3158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "pll8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct clk_regmap pll8_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .parent_names = (const char *[]){ "pll8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct hfpll_data hfpll0_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mode_reg = 0x3200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .l_reg = 0x3208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .m_reg = 0x320c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .n_reg = 0x3210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .config_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .status_reg = 0x321c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .droop_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct clk_hfpll hfpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .d = &hfpll0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "hfpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct hfpll_data hfpll1_8064_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .mode_reg = 0x3240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .l_reg = 0x3248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .m_reg = 0x324c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .n_reg = 0x3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .config_reg = 0x3244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .status_reg = 0x325c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .droop_reg = 0x3254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct hfpll_data hfpll1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .mode_reg = 0x3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .l_reg = 0x3308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .m_reg = 0x330c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .n_reg = 0x3310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .config_reg = 0x3304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .status_reg = 0x331c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .droop_reg = 0x3314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct clk_hfpll hfpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .d = &hfpll1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "hfpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct hfpll_data hfpll2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .mode_reg = 0x3280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .l_reg = 0x3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .m_reg = 0x328c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .n_reg = 0x3290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .config_reg = 0x3284,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .status_reg = 0x329c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .droop_reg = 0x3294,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct clk_hfpll hfpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .d = &hfpll2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .name = "hfpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct hfpll_data hfpll3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .mode_reg = 0x32c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .l_reg = 0x32c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .m_reg = 0x32cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .n_reg = 0x32d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .config_reg = 0x32c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .status_reg = 0x32dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .droop_reg = 0x32d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct clk_hfpll hfpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .d = &hfpll3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "hfpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct hfpll_data hfpll_l2_8064_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .mode_reg = 0x3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .l_reg = 0x3308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .m_reg = 0x330c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .n_reg = 0x3310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .config_reg = 0x3304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .status_reg = 0x331c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .droop_reg = 0x3314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct hfpll_data hfpll_l2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .mode_reg = 0x3400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .l_reg = 0x3408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .m_reg = 0x340c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .n_reg = 0x3410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .config_reg = 0x3404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .status_reg = 0x341c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .droop_reg = 0x3414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct clk_hfpll hfpll_l2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .d = &hfpll_l2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "hfpll_l2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct clk_pll pll14 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .l_reg = 0x31c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .m_reg = 0x31c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .n_reg = 0x31cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .config_reg = 0x31d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .mode_reg = 0x31c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .status_reg = 0x31d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "pll14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct clk_regmap pll14_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "pll14_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .parent_names = (const char *[]){ "pll14" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) P_PXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) P_PLL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) P_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) P_CXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct parent_map gcc_pxo_pll8_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { P_PLL8, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const char * const gcc_pxo_pll8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { P_PLL8, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { P_CXO, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const char * const gcc_pxo_pll8_cxo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { P_PLL8, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { P_PLL3, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const char * const gcc_pxo_pll8_pll3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct freq_tbl clk_tbl_gsbi_uart[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 1843200, P_PLL8, 2, 6, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 3686400, P_PLL8, 2, 12, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 7372800, P_PLL8, 2, 24, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 14745600, P_PLL8, 2, 48, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 32000000, P_PLL8, 4, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 40000000, P_PLL8, 1, 5, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 46400000, P_PLL8, 1, 29, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 56000000, P_PLL8, 1, 7, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 58982400, P_PLL8, 1, 96, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct clk_rcg gsbi1_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .ns_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .md_reg = 0x29d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct clk_branch gsbi1_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "gsbi1_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct clk_rcg gsbi2_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .ns_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .md_reg = 0x29f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct clk_branch gsbi2_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "gsbi2_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct clk_rcg gsbi3_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .ns_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .md_reg = 0x2a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .enable_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = "gsbi3_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct clk_branch gsbi3_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .enable_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .name = "gsbi3_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "gsbi3_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct clk_rcg gsbi4_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ns_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .md_reg = 0x2a30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct clk_branch gsbi4_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "gsbi4_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct clk_rcg gsbi5_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .ns_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .md_reg = 0x2a50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .name = "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static struct clk_branch gsbi5_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .name = "gsbi5_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct clk_rcg gsbi6_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ns_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .md_reg = 0x2a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .enable_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .name = "gsbi6_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static struct clk_branch gsbi6_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .enable_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .name = "gsbi6_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "gsbi6_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct clk_rcg gsbi7_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .ns_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .md_reg = 0x2a90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .enable_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .name = "gsbi7_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static struct clk_branch gsbi7_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .enable_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = "gsbi7_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "gsbi7_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static struct clk_rcg gsbi8_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .ns_reg = 0x2ab4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .md_reg = 0x2ab0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .enable_reg = 0x2ab4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "gsbi8_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static struct clk_branch gsbi8_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .enable_reg = 0x2ab4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .name = "gsbi8_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .parent_names = (const char *[]){ "gsbi8_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static struct clk_rcg gsbi9_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .ns_reg = 0x2ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .md_reg = 0x2ad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .enable_reg = 0x2ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = "gsbi9_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static struct clk_branch gsbi9_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .enable_reg = 0x2ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .name = "gsbi9_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .parent_names = (const char *[]){ "gsbi9_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static struct clk_rcg gsbi10_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .ns_reg = 0x2af4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .md_reg = 0x2af0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .enable_reg = 0x2af4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .name = "gsbi10_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct clk_branch gsbi10_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .enable_reg = 0x2af4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .name = "gsbi10_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .parent_names = (const char *[]){ "gsbi10_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static struct clk_rcg gsbi11_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .ns_reg = 0x2b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .md_reg = 0x2b10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .enable_reg = 0x2b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .name = "gsbi11_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static struct clk_branch gsbi11_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .enable_reg = 0x2b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .name = "gsbi11_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .parent_names = (const char *[]){ "gsbi11_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static struct clk_rcg gsbi12_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .ns_reg = 0x2b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .md_reg = 0x2b30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .enable_reg = 0x2b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .name = "gsbi12_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static struct clk_branch gsbi12_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .enable_reg = 0x2b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .name = "gsbi12_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .parent_names = (const char *[]){ "gsbi12_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static struct freq_tbl clk_tbl_gsbi_qup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) { 1100000, P_PXO, 1, 2, 49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) { 5400000, P_PXO, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) { 10800000, P_PXO, 1, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) { 15060000, P_PLL8, 1, 2, 51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { 25600000, P_PLL8, 1, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct clk_rcg gsbi1_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .ns_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .md_reg = 0x29c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .name = "gsbi1_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static struct clk_branch gsbi1_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .name = "gsbi1_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .parent_names = (const char *[]){ "gsbi1_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct clk_rcg gsbi2_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .ns_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .md_reg = 0x29e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .name = "gsbi2_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static struct clk_branch gsbi2_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .name = "gsbi2_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .parent_names = (const char *[]){ "gsbi2_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static struct clk_rcg gsbi3_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .ns_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .md_reg = 0x2a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .enable_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .name = "gsbi3_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static struct clk_branch gsbi3_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .enable_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .name = "gsbi3_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .parent_names = (const char *[]){ "gsbi3_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static struct clk_rcg gsbi4_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .ns_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .md_reg = 0x2a28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .name = "gsbi4_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static struct clk_branch gsbi4_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .name = "gsbi4_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .parent_names = (const char *[]){ "gsbi4_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static struct clk_rcg gsbi5_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .ns_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .md_reg = 0x2a48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .name = "gsbi5_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static struct clk_branch gsbi5_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .name = "gsbi5_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .parent_names = (const char *[]){ "gsbi5_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static struct clk_rcg gsbi6_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .ns_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .md_reg = 0x2a68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .enable_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .name = "gsbi6_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static struct clk_branch gsbi6_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .enable_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .name = "gsbi6_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .parent_names = (const char *[]){ "gsbi6_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static struct clk_rcg gsbi7_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .ns_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .md_reg = 0x2a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .enable_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .name = "gsbi7_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static struct clk_branch gsbi7_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .enable_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .name = "gsbi7_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .parent_names = (const char *[]){ "gsbi7_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static struct clk_rcg gsbi8_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .ns_reg = 0x2aac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .md_reg = 0x2aa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .enable_reg = 0x2aac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .name = "gsbi8_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static struct clk_branch gsbi8_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .enable_reg = 0x2aac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .name = "gsbi8_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .parent_names = (const char *[]){ "gsbi8_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static struct clk_rcg gsbi9_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .ns_reg = 0x2acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .md_reg = 0x2ac8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .enable_reg = 0x2acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .name = "gsbi9_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static struct clk_branch gsbi9_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .enable_reg = 0x2acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .name = "gsbi9_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .parent_names = (const char *[]){ "gsbi9_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static struct clk_rcg gsbi10_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .ns_reg = 0x2aec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .md_reg = 0x2ae8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .enable_reg = 0x2aec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .name = "gsbi10_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static struct clk_branch gsbi10_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .enable_reg = 0x2aec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .name = "gsbi10_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .parent_names = (const char *[]){ "gsbi10_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static struct clk_rcg gsbi11_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .ns_reg = 0x2b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .md_reg = 0x2b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .enable_reg = 0x2b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .name = "gsbi11_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static struct clk_branch gsbi11_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .enable_reg = 0x2b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .name = "gsbi11_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .parent_names = (const char *[]){ "gsbi11_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static struct clk_rcg gsbi12_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .ns_reg = 0x2b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .md_reg = 0x2b28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .enable_reg = 0x2b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .name = "gsbi12_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static struct clk_branch gsbi12_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .enable_reg = 0x2b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .name = "gsbi12_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .parent_names = (const char *[]){ "gsbi12_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static const struct freq_tbl clk_tbl_gp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) { 9600000, P_CXO, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) { 13500000, P_PXO, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) { 19200000, P_CXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) { 76800000, P_PLL8, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) { 96000000, P_PLL8, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) { 128000000, P_PLL8, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { 192000000, P_PLL8, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static struct clk_rcg gp0_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .ns_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .md_reg = 0x2d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .name = "gp0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static struct clk_branch gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .name = "gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .parent_names = (const char *[]){ "gp0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static struct clk_rcg gp1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .ns_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .md_reg = 0x2d40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .name = "gp1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static struct clk_branch gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .name = "gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .parent_names = (const char *[]){ "gp1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static struct clk_rcg gp2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .ns_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .md_reg = 0x2d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .name = "gp2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static struct clk_branch gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .name = "gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .parent_names = (const char *[]){ "gp2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static struct clk_branch pmem_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .hwcg_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .enable_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .name = "pmem_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static struct clk_rcg prng_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .ns_reg = 0x2e80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .name = "prng_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static struct clk_branch prng_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .name = "prng_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .parent_names = (const char *[]){ "prng_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static const struct freq_tbl clk_tbl_sdc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) { 144000, P_PXO, 3, 2, 125 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) { 400000, P_PLL8, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) { 17070000, P_PLL8, 1, 2, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) { 20210000, P_PLL8, 1, 1, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) { 64000000, P_PLL8, 3, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) { 96000000, P_PLL8, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) { 192000000, P_PLL8, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static struct clk_rcg sdc1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .ns_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .md_reg = 0x2828,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .name = "sdc1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static struct clk_branch sdc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .name = "sdc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .parent_names = (const char *[]){ "sdc1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static struct clk_rcg sdc2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .ns_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .md_reg = 0x2848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .enable_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .name = "sdc2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static struct clk_branch sdc2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .enable_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .name = "sdc2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .parent_names = (const char *[]){ "sdc2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static struct clk_rcg sdc3_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .ns_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .md_reg = 0x2868,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .enable_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .name = "sdc3_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static struct clk_branch sdc3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .enable_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .name = "sdc3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .parent_names = (const char *[]){ "sdc3_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static struct clk_rcg sdc4_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .ns_reg = 0x288c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .md_reg = 0x2888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .enable_reg = 0x288c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .name = "sdc4_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static struct clk_branch sdc4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .enable_reg = 0x288c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .name = "sdc4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .parent_names = (const char *[]){ "sdc4_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static struct clk_rcg sdc5_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .ns_reg = 0x28ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .md_reg = 0x28a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .enable_reg = 0x28ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .name = "sdc5_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) static struct clk_branch sdc5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .enable_reg = 0x28ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .name = "sdc5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .parent_names = (const char *[]){ "sdc5_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static const struct freq_tbl clk_tbl_tsif_ref[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) { 105000, P_PXO, 1, 1, 256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static struct clk_rcg tsif_ref_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .ns_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .md_reg = 0x270c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .freq_tbl = clk_tbl_tsif_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .enable_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .name = "tsif_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static struct clk_branch tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .enable_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .name = "tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .parent_names = (const char *[]){ "tsif_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static const struct freq_tbl clk_tbl_usb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) { 60000000, P_PLL8, 1, 5, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static struct clk_rcg usb_hs1_xcvr_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .ns_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .md_reg = 0x2908,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .enable_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .name = "usb_hs1_xcvr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) static struct clk_branch usb_hs1_xcvr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .enable_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .name = "usb_hs1_xcvr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static struct clk_rcg usb_hs3_xcvr_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .ns_reg = 0x370c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .md_reg = 0x3708,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .enable_reg = 0x370c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .name = "usb_hs3_xcvr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static struct clk_branch usb_hs3_xcvr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .halt_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .enable_reg = 0x370c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .name = "usb_hs3_xcvr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static struct clk_rcg usb_hs4_xcvr_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .ns_reg = 0x372c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .md_reg = 0x3728,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .enable_reg = 0x372c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .name = "usb_hs4_xcvr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static struct clk_branch usb_hs4_xcvr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .enable_reg = 0x372c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .name = "usb_hs4_xcvr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static struct clk_rcg usb_hsic_xcvr_fs_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .ns_reg = 0x2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .md_reg = 0x2924,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .enable_reg = 0x2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .name = "usb_hsic_xcvr_fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static struct clk_branch usb_hsic_xcvr_fs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .enable_reg = 0x2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .name = "usb_hsic_xcvr_fs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .parent_names = usb_hsic_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static struct clk_branch usb_hsic_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .enable_reg = 0x292c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .parent_names = usb_hsic_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .name = "usb_hsic_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static struct clk_branch usb_hsic_hsic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .enable_reg = 0x2b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .parent_names = (const char *[]){ "pll14_vote" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .name = "usb_hsic_hsic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) static struct clk_branch usb_hsic_hsio_cal_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .enable_reg = 0x2b48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .name = "usb_hsic_hsio_cal_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) static struct clk_rcg usb_fs1_xcvr_fs_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .ns_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .md_reg = 0x2964,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .enable_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .name = "usb_fs1_xcvr_fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static struct clk_branch usb_fs1_xcvr_fs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .enable_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .name = "usb_fs1_xcvr_fs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .parent_names = usb_fs1_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) static struct clk_branch usb_fs1_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .enable_reg = 0x296c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .parent_names = usb_fs1_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .name = "usb_fs1_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static struct clk_rcg usb_fs2_xcvr_fs_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .ns_reg = 0x2988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .md_reg = 0x2984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .enable_reg = 0x2988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .name = "usb_fs2_xcvr_fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static struct clk_branch usb_fs2_xcvr_fs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .enable_reg = 0x2988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .name = "usb_fs2_xcvr_fs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .parent_names = usb_fs2_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static struct clk_branch usb_fs2_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .enable_reg = 0x298c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .name = "usb_fs2_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .parent_names = usb_fs2_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static struct clk_branch ce1_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .hwcg_reg = 0x2724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .enable_reg = 0x2724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .name = "ce1_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static struct clk_branch ce1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .enable_reg = 0x2720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .name = "ce1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static struct clk_branch dma_bam_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .hwcg_reg = 0x25c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .enable_reg = 0x25c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .name = "dma_bam_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static struct clk_branch gsbi1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .hwcg_reg = 0x29c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .enable_reg = 0x29c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .name = "gsbi1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static struct clk_branch gsbi2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .hwcg_reg = 0x29e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .enable_reg = 0x29e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .name = "gsbi2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) static struct clk_branch gsbi3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .hwcg_reg = 0x2a00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .enable_reg = 0x2a00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .name = "gsbi3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) static struct clk_branch gsbi4_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .hwcg_reg = 0x2a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .enable_reg = 0x2a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .name = "gsbi4_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static struct clk_branch gsbi5_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .hwcg_reg = 0x2a40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .enable_reg = 0x2a40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .name = "gsbi5_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static struct clk_branch gsbi6_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .hwcg_reg = 0x2a60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .enable_reg = 0x2a60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .name = "gsbi6_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static struct clk_branch gsbi7_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .hwcg_reg = 0x2a80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .enable_reg = 0x2a80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .name = "gsbi7_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) static struct clk_branch gsbi8_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .hwcg_reg = 0x2aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .enable_reg = 0x2aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .name = "gsbi8_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static struct clk_branch gsbi9_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .hwcg_reg = 0x2ac0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .enable_reg = 0x2ac0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .name = "gsbi9_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) static struct clk_branch gsbi10_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .hwcg_reg = 0x2ae0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .enable_reg = 0x2ae0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .name = "gsbi10_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static struct clk_branch gsbi11_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .hwcg_reg = 0x2b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .enable_reg = 0x2b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .name = "gsbi11_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static struct clk_branch gsbi12_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .hwcg_reg = 0x2b20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .enable_reg = 0x2b20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .name = "gsbi12_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) static struct clk_branch tsif_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .hwcg_reg = 0x2700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .enable_reg = 0x2700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .name = "tsif_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) static struct clk_branch usb_fs1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .enable_reg = 0x2960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .name = "usb_fs1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static struct clk_branch usb_fs2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .enable_reg = 0x2980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .name = "usb_fs2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) static struct clk_branch usb_hs1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .hwcg_reg = 0x2900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .enable_reg = 0x2900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .name = "usb_hs1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static struct clk_branch usb_hs3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .halt_bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .enable_reg = 0x3700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .name = "usb_hs3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) static struct clk_branch usb_hs4_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .enable_reg = 0x3720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .name = "usb_hs4_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) static struct clk_branch usb_hsic_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .halt_bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .enable_reg = 0x2920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .name = "usb_hsic_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) static struct clk_branch sdc1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .hwcg_reg = 0x2820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .enable_reg = 0x2820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .name = "sdc1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) static struct clk_branch sdc2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .hwcg_reg = 0x2840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .enable_reg = 0x2840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .name = "sdc2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) static struct clk_branch sdc3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .hwcg_reg = 0x2860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .enable_reg = 0x2860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .name = "sdc3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) static struct clk_branch sdc4_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .hwcg_reg = 0x2880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .enable_reg = 0x2880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .name = "sdc4_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) static struct clk_branch sdc5_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .hwcg_reg = 0x28a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .enable_reg = 0x28a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .name = "sdc5_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) static struct clk_branch adm0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .name = "adm0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) static struct clk_branch adm0_pbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .hwcg_reg = 0x2208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .name = "adm0_pbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static struct freq_tbl clk_tbl_ce3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) { 48000000, P_PLL8, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) { 100000000, P_PLL3, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) { 120000000, P_PLL3, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static struct clk_rcg ce3_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .ns_reg = 0x36c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .parent_map = gcc_pxo_pll8_pll3_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .freq_tbl = clk_tbl_ce3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .enable_reg = 0x36c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .name = "ce3_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .parent_names = gcc_pxo_pll8_pll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) static struct clk_branch ce3_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .enable_reg = 0x36cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .name = "ce3_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .parent_names = (const char *[]){ "ce3_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) static struct clk_branch ce3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .halt_reg = 0x2fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .enable_reg = 0x36c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .name = "ce3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .parent_names = (const char *[]){ "ce3_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) static const struct freq_tbl clk_tbl_sata_ref[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) { 48000000, P_PLL8, 8, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) { 100000000, P_PLL3, 12, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) static struct clk_rcg sata_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .ns_reg = 0x2c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .parent_map = gcc_pxo_pll8_pll3_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) .freq_tbl = clk_tbl_sata_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .enable_reg = 0x2c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .name = "sata_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .parent_names = gcc_pxo_pll8_pll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) static struct clk_branch sata_rxoob_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .enable_reg = 0x2c0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .name = "sata_rxoob_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .parent_names = (const char *[]){ "sata_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) static struct clk_branch sata_pmalive_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .halt_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .enable_reg = 0x2c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .name = "sata_pmalive_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .parent_names = (const char *[]){ "sata_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) static struct clk_branch sata_phy_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .enable_reg = 0x2c14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .name = "sata_phy_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static struct clk_branch sata_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .halt_reg = 0x2fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .enable_reg = 0x2c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) .name = "sata_a_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) static struct clk_branch sata_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .enable_reg = 0x2c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .name = "sata_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static struct clk_branch sfab_sata_s_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .halt_reg = 0x2fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .enable_reg = 0x2480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .name = "sfab_sata_s_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) static struct clk_branch sata_phy_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .enable_reg = 0x2c40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .name = "sata_phy_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) static struct clk_branch pcie_phy_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .halt_bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .enable_reg = 0x22d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .name = "pcie_phy_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) static struct clk_branch pcie_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) .enable_reg = 0x22cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .name = "pcie_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) static struct clk_branch pcie_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .halt_reg = 0x2fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) .enable_reg = 0x22c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) .name = "pcie_a_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) static struct clk_branch pmic_arb0_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) .name = "pmic_arb0_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) static struct clk_branch pmic_arb1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .name = "pmic_arb1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) static struct clk_branch pmic_ssbi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .name = "pmic_ssbi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) static struct clk_branch rpm_msg_ram_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) .hwcg_reg = 0x27e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) .name = "rpm_msg_ram_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static struct clk_regmap *gcc_msm8960_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) [PLL3] = &pll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) [PLL4_VOTE] = &pll4_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) [PLL8] = &pll8.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) [PLL8_VOTE] = &pll8_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) [PLL14] = &pll14.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) [PLL14_VOTE] = &pll14_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) [GP0_SRC] = &gp0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) [GP0_CLK] = &gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) [GP1_SRC] = &gp1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) [GP1_CLK] = &gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) [GP2_SRC] = &gp2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) [GP2_CLK] = &gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) [PMEM_A_CLK] = &pmem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) [PRNG_SRC] = &prng_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) [PRNG_CLK] = &prng_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) [SDC1_SRC] = &sdc1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) [SDC1_CLK] = &sdc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) [SDC2_SRC] = &sdc2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) [SDC2_CLK] = &sdc2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) [SDC3_SRC] = &sdc3_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) [SDC3_CLK] = &sdc3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) [SDC4_SRC] = &sdc4_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) [SDC4_CLK] = &sdc4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) [SDC5_SRC] = &sdc5_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) [SDC5_CLK] = &sdc5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) [TSIF_REF_SRC] = &tsif_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) [CE1_CORE_CLK] = &ce1_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) [CE1_H_CLK] = &ce1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) [TSIF_H_CLK] = &tsif_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) [SDC1_H_CLK] = &sdc1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) [SDC2_H_CLK] = &sdc2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) [SDC3_H_CLK] = &sdc3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) [SDC4_H_CLK] = &sdc4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) [SDC5_H_CLK] = &sdc5_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) [ADM0_CLK] = &adm0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) [PLL9] = &hfpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) [PLL10] = &hfpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) [PLL12] = &hfpll_l2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) static const struct qcom_reset_map gcc_msm8960_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) [QDSS_STM_RESET] = { 0x2060, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) [ADM0_C2_RESET] = { 0x220c, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) [ADM0_C1_RESET] = { 0x220c, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) [ADM0_C0_RESET] = { 0x220c, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) [ADM0_PBUS_RESET] = { 0x220c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) [ADM0_RESET] = { 0x220c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) [QDSS_POR_RESET] = { 0x2260, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) [QDSS_TSCTR_RESET] = { 0x2260, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) [QDSS_HRESET_RESET] = { 0x2260, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) [QDSS_AXI_RESET] = { 0x2260, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) [QDSS_DBG_RESET] = { 0x2260 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) [PCIE_A_RESET] = { 0x22c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) [PCIE_AUX_RESET] = { 0x22c8, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) [PCIE_H_RESET] = { 0x22d0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) [SFAB_PCIE_S_RESET] = { 0x22d4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) [SFAB_MSS_M_RESET] = { 0x2340, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) [SFAB_USB3_M_RESET] = { 0x2360, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) [SFAB_LPASS_RESET] = { 0x23a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) [SFAB_SATA_S_RESET] = { 0x2480, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) [DFAB_SWAY0_RESET] = { 0x2540, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) [DFAB_SWAY1_RESET] = { 0x2544, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) [DFAB_ARB0_RESET] = { 0x2560, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) [DFAB_ARB1_RESET] = { 0x2564, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) [PPSS_PROC_RESET] = { 0x2594, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) [PPSS_RESET] = { 0x2594},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) [DMA_BAM_RESET] = { 0x25c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) [SPS_TIC_H_RESET] = { 0x2600, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) [SLIMBUS_H_RESET] = { 0x2620, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) [TSIF_H_RESET] = { 0x2700, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [CE1_H_RESET] = { 0x2720, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [CE1_CORE_RESET] = { 0x2724, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [CE1_SLEEP_RESET] = { 0x2728, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [CE2_H_RESET] = { 0x2740, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [CE2_CORE_RESET] = { 0x2744, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [RPM_PROC_RESET] = { 0x27c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [PMIC_SSBI2_RESET] = { 0x280c, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [SDC1_RESET] = { 0x2830 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) [SDC2_RESET] = { 0x2850 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [SDC3_RESET] = { 0x2870 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [SDC4_RESET] = { 0x2890 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [SDC5_RESET] = { 0x28b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [DFAB_A2_RESET] = { 0x28c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [USB_HS1_RESET] = { 0x2910 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) [USB_HSIC_RESET] = { 0x2934 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [USB_FS1_RESET] = { 0x2974 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [USB_FS2_RESET] = { 0x2994 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) [GSBI1_RESET] = { 0x29dc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [GSBI2_RESET] = { 0x29fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [GSBI3_RESET] = { 0x2a1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [GSBI4_RESET] = { 0x2a3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [GSBI5_RESET] = { 0x2a5c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) [GSBI6_RESET] = { 0x2a7c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) [GSBI7_RESET] = { 0x2a9c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) [GSBI8_RESET] = { 0x2abc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [GSBI9_RESET] = { 0x2adc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [GSBI10_RESET] = { 0x2afc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) [GSBI11_RESET] = { 0x2b1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) [GSBI12_RESET] = { 0x2b3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) [SPDM_RESET] = { 0x2b6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) [TLMM_H_RESET] = { 0x2ba0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [MSS_SLP_RESET] = { 0x2c60, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) [MSS_RESET] = { 0x2c64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) [SATA_H_RESET] = { 0x2c80, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) [TSSC_RESET] = { 0x2ca0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) [PDM_RESET] = { 0x2cc0, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) [MPM_H_RESET] = { 0x2da0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) [MPM_RESET] = { 0x2da4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) [PRNG_RESET] = { 0x2e80, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) [RIVA_RESET] = { 0x35e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) static struct clk_regmap *gcc_apq8064_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) [PLL3] = &pll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) [PLL4_VOTE] = &pll4_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) [PLL8] = &pll8.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) [PLL8_VOTE] = &pll8_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) [PLL14] = &pll14.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) [PLL14_VOTE] = &pll14_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) [GP0_SRC] = &gp0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) [GP0_CLK] = &gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) [GP1_SRC] = &gp1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) [GP1_CLK] = &gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) [GP2_SRC] = &gp2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) [GP2_CLK] = &gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) [PMEM_A_CLK] = &pmem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) [PRNG_SRC] = &prng_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) [PRNG_CLK] = &prng_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) [SDC1_SRC] = &sdc1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) [SDC1_CLK] = &sdc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) [SDC2_SRC] = &sdc2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) [SDC2_CLK] = &sdc2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) [SDC3_SRC] = &sdc3_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) [SDC3_CLK] = &sdc3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) [SDC4_SRC] = &sdc4_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) [SDC4_CLK] = &sdc4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) [TSIF_REF_SRC] = &tsif_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) [SATA_H_CLK] = &sata_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) [SATA_CLK_SRC] = &sata_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) [SATA_A_CLK] = &sata_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) [CE3_SRC] = &ce3_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) [CE3_CORE_CLK] = &ce3_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) [CE3_H_CLK] = &ce3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) [TSIF_H_CLK] = &tsif_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) [SDC1_H_CLK] = &sdc1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) [SDC2_H_CLK] = &sdc2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) [SDC3_H_CLK] = &sdc3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) [SDC4_H_CLK] = &sdc4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) [ADM0_CLK] = &adm0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) [PCIE_A_CLK] = &pcie_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) [PCIE_H_CLK] = &pcie_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) [PLL9] = &hfpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) [PLL10] = &hfpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) [PLL12] = &hfpll_l2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) [PLL16] = &hfpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) [PLL17] = &hfpll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) static const struct qcom_reset_map gcc_apq8064_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) [QDSS_STM_RESET] = { 0x2060, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) [ADM0_C2_RESET] = { 0x220c, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) [ADM0_C1_RESET] = { 0x220c, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) [ADM0_C0_RESET] = { 0x220c, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) [ADM0_PBUS_RESET] = { 0x220c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) [ADM0_RESET] = { 0x220c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) [QDSS_POR_RESET] = { 0x2260, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) [QDSS_TSCTR_RESET] = { 0x2260, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) [QDSS_HRESET_RESET] = { 0x2260, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) [QDSS_AXI_RESET] = { 0x2260, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) [QDSS_DBG_RESET] = { 0x2260 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) [SFAB_PCIE_S_RESET] = { 0x22d8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) [PCIE_PHY_RESET] = { 0x22dc, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) [PCIE_PCI_RESET] = { 0x22dc, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) [PCIE_POR_RESET] = { 0x22dc, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) [PCIE_HCLK_RESET] = { 0x22dc, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) [PCIE_ACLK_RESET] = { 0x22dc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) [SFAB_USB3_M_RESET] = { 0x2360, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) [SFAB_LPASS_RESET] = { 0x23a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) [SFAB_SATA_S_RESET] = { 0x2480, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) [DFAB_SWAY0_RESET] = { 0x2540, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) [DFAB_SWAY1_RESET] = { 0x2544, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) [DFAB_ARB0_RESET] = { 0x2560, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) [DFAB_ARB1_RESET] = { 0x2564, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) [PPSS_PROC_RESET] = { 0x2594, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) [PPSS_RESET] = { 0x2594},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) [DMA_BAM_RESET] = { 0x25c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) [SPS_TIC_H_RESET] = { 0x2600, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) [TSIF_H_RESET] = { 0x2700, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) [CE1_H_RESET] = { 0x2720, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) [CE1_CORE_RESET] = { 0x2724, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) [CE1_SLEEP_RESET] = { 0x2728, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) [CE2_H_RESET] = { 0x2740, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) [CE2_CORE_RESET] = { 0x2744, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) [RPM_PROC_RESET] = { 0x27c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) [PMIC_SSBI2_RESET] = { 0x280c, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) [SDC1_RESET] = { 0x2830 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) [SDC2_RESET] = { 0x2850 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) [SDC3_RESET] = { 0x2870 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) [SDC4_RESET] = { 0x2890 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) [USB_HS1_RESET] = { 0x2910 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) [USB_HSIC_RESET] = { 0x2934 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) [USB_FS1_RESET] = { 0x2974 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) [GSBI1_RESET] = { 0x29dc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) [GSBI2_RESET] = { 0x29fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) [GSBI3_RESET] = { 0x2a1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) [GSBI4_RESET] = { 0x2a3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) [GSBI5_RESET] = { 0x2a5c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) [GSBI6_RESET] = { 0x2a7c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) [GSBI7_RESET] = { 0x2a9c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) [SPDM_RESET] = { 0x2b6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) [TLMM_H_RESET] = { 0x2ba0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) [SATA_SFAB_M_RESET] = { 0x2c18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) [SATA_RESET] = { 0x2c1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) [GSS_SLP_RESET] = { 0x2c60, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) [GSS_RESET] = { 0x2c64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) [TSSC_RESET] = { 0x2ca0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) [PDM_RESET] = { 0x2cc0, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) [MPM_H_RESET] = { 0x2da0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) [MPM_RESET] = { 0x2da4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) [PRNG_RESET] = { 0x2e80, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) [RIVA_RESET] = { 0x35e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) [CE3_H_RESET] = { 0x36c4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) [SFAB_CE3_S_RESET] = { 0x36c8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) [CE3_RESET] = { 0x36cc, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) [CE3_SLEEP_RESET] = { 0x36d0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) [USB_HS3_RESET] = { 0x3710 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) [USB_HS4_RESET] = { 0x3730 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) static const struct regmap_config gcc_msm8960_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) .max_register = 0x3660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) static const struct regmap_config gcc_apq8064_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) .max_register = 0x3880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) static const struct qcom_cc_desc gcc_msm8960_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) .config = &gcc_msm8960_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) .clks = gcc_msm8960_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) .resets = gcc_msm8960_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) static const struct qcom_cc_desc gcc_apq8064_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) .config = &gcc_apq8064_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) .clks = gcc_apq8064_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) .resets = gcc_apq8064_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) static const struct of_device_id gcc_msm8960_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) static int gcc_msm8960_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) struct platform_device *tsens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) ret = qcom_cc_probe(pdev, match->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) if (match->data == &gcc_apq8064_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) hfpll1.d = &hfpll1_8064_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) hfpll_l2.d = &hfpll_l2_8064_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) if (IS_ERR(tsens))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) return PTR_ERR(tsens);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) platform_set_drvdata(pdev, tsens);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) static int gcc_msm8960_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) struct platform_device *tsens = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) platform_device_unregister(tsens);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) static struct platform_driver gcc_msm8960_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) .probe = gcc_msm8960_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) .remove = gcc_msm8960_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) .name = "gcc-msm8960",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) .of_match_table = gcc_msm8960_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) static int __init gcc_msm8960_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) return platform_driver_register(&gcc_msm8960_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) core_initcall(gcc_msm8960_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) static void __exit gcc_msm8960_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) platform_driver_unregister(&gcc_msm8960_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) module_exit(gcc_msm8960_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) MODULE_ALIAS("platform:gcc-msm8960");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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