^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2020 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-msm8939.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,gcc-msm8939.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL0_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_BIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_GPLL1_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_GPLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_GPLL2_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_GPLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_GPLL3_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_GPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_GPLL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_GPLL5_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_GPLL5_EARLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) P_GPLL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) P_GPLL6_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) P_DSI0_PHYPLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) P_DSI0_PHYPLL_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) P_EXT_PRI_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) P_EXT_SEC_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) P_EXT_MCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct clk_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .l_reg = 0x21004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .m_reg = 0x21008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .n_reg = 0x2100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .config_reg = 0x21010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .mode_reg = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .status_reg = 0x2101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct clk_regmap gpll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .hw = &gpll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct clk_pll gpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .l_reg = 0x20004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .m_reg = 0x20008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .n_reg = 0x2000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .config_reg = 0x20010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .mode_reg = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .status_reg = 0x2001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct clk_regmap gpll1_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .hw = &gpll1.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct clk_pll gpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .l_reg = 0x4a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .m_reg = 0x4a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .n_reg = 0x4a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .config_reg = 0x4a010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .mode_reg = 0x4a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .status_reg = 0x4a01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct clk_regmap gpll2_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "gpll2_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .hw = &gpll2.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct clk_pll bimc_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .l_reg = 0x23004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .m_reg = 0x23008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .n_reg = 0x2300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .config_reg = 0x23010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .mode_reg = 0x23000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .status_reg = 0x2301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "bimc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct clk_regmap bimc_pll_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "bimc_pll_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .hw = &bimc_pll.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct clk_pll gpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .l_reg = 0x22004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .m_reg = 0x22008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .n_reg = 0x2200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .config_reg = 0x22010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .mode_reg = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .status_reg = 0x2201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "gpll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct clk_regmap gpll3_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "gpll3_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .hw = &gpll3.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* GPLL3 at 1100 MHz, main output enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct pll_config gpll3_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .l = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .m = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .n = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .vco_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .vco_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .pre_div_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .post_div_mask = BIT(9) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .mn_ena_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .aux_output_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct clk_pll gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .l_reg = 0x24004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .m_reg = 0x24008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .n_reg = 0x2400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .config_reg = 0x24010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .mode_reg = 0x24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .status_reg = 0x2401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct clk_regmap gpll4_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .name = "gpll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .hw = &gpll4.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* GPLL4 at 1200 MHz, main output enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct pll_config gpll4_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .l = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .m = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .n = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .vco_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .vco_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .pre_div_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .post_div_mask = BIT(9) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .mn_ena_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct clk_pll gpll5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .l_reg = 0x25004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .m_reg = 0x25008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .n_reg = 0x2500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .config_reg = 0x25010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .mode_reg = 0x25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .status_reg = 0x2501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = "gpll5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct clk_regmap gpll5_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "gpll5_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .hw = &gpll5.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct clk_pll gpll6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .l_reg = 0x37004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .m_reg = 0x37008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .n_reg = 0x3700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .config_reg = 0x37010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .mode_reg = 0x37000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .status_reg = 0x3701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct clk_regmap gpll6_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .name = "gpll6_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .hw = &gpll6.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct parent_map gcc_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { P_BIMC, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { .hw = &bimc_pll_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { P_GPLL6_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .hw = &gpll6_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { P_GPLL2_AUX, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { P_GPLL3, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { P_GPLL6_AUX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { .hw = &gpll2_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { .hw = &gpll3_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { .hw = &gpll6_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { P_GPLL2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .hw = &gpll2_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { P_GPLL2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { P_GPLL4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { .hw = &gpll2_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { .hw = &gpll4_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct parent_map gcc_xo_gpll0a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { P_GPLL0_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { P_GPLL1_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { P_SLEEP_CLK, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .hw = &gpll1_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { P_GPLL1_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { P_SLEEP_CLK, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { .hw = &gpll1_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { .hw = &gpll6_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { P_GPLL1_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { .hw = &gpll1_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct parent_map gcc_xo_dsibyte_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { P_XO, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { P_DSI0_PHYPLL_BYTE, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { P_GPLL0_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { P_DSI0_PHYPLL_BYTE, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { P_DSI0_PHYPLL_DSI, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { P_GPLL6, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { P_GPLL3_AUX, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { P_GPLL0_AUX, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { .hw = &gpll1_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { .fw_name = "dsi0pll", .name = "dsi0pll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { .hw = &gpll6_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { .hw = &gpll3_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { P_GPLL0_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { P_DSI0_PHYPLL_DSI, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { .fw_name = "dsi0pll", .name = "dsi0pll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { P_GPLL5_AUX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { P_BIMC, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { .hw = &gpll5_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { .hw = &gpll6_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { .hw = &bimc_pll_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { P_GPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .hw = &gpll1_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { P_EXT_PRI_I2S, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { P_EXT_MCLK, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { .fw_name = "ext_mclk", .name = "ext_mclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { P_EXT_SEC_I2S, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { P_EXT_MCLK, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { .hw = &gpll1_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { .fw_name = "ext_mclk", .name = "ext_mclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct parent_map gcc_xo_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { P_EXT_MCLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { .hw = &gpll1_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { .fw_name = "ext_mclk", .name = "ext_mclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { .fw_name = "sleep_clk", .name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { .hw = &gpll6_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { .hw = &gpll6_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { .hw = &gpll0_vote.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .cmd_rcgr = 0x27000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .name = "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static struct clk_rcg2 system_noc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .cmd_rcgr = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .parent_map = gcc_xo_gpll0_gpll6a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .name = "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct clk_rcg2 bimc_ddr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .cmd_rcgr = 0x32004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .parent_map = gcc_xo_gpll0_bimc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .name = "bimc_ddr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .parent_data = gcc_xo_gpll0_bimc_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) F(40000000, P_GPLL0, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct clk_rcg2 camss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .cmd_rcgr = 0x5a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .freq_tbl = ftbl_gcc_camss_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .name = "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct freq_tbl ftbl_apss_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) F(133330000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct clk_rcg2 apss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .cmd_rcgr = 0x46000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .freq_tbl = ftbl_apss_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .name = "apss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static struct clk_rcg2 csi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .cmd_rcgr = 0x4e020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .name = "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static struct clk_rcg2 csi1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .cmd_rcgr = 0x4f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .name = "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) F(220000000, P_GPLL3, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) F(266670000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) F(310000000, P_GPLL2_AUX, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) F(465000000, P_GPLL2_AUX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) F(550000000, P_GPLL3, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct clk_rcg2 gfx3d_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .cmd_rcgr = 0x59000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) F(177780000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) F(266670000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) F(465000000, P_GPLL2, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) F(480000000, P_GPLL4, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) F(600000000, P_GPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static struct clk_rcg2 vfe0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .cmd_rcgr = 0x58000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .freq_tbl = ftbl_gcc_camss_vfe0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .name = "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .cmd_rcgr = 0x0200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) F(16000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .cmd_rcgr = 0x02024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .cmd_rcgr = 0x03000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .cmd_rcgr = 0x03014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .cmd_rcgr = 0x04000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .cmd_rcgr = 0x04024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .cmd_rcgr = 0x05000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .cmd_rcgr = 0x05024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .cmd_rcgr = 0x06000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .cmd_rcgr = 0x06024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .cmd_rcgr = 0x07000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .cmd_rcgr = 0x07024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) F(3686400, P_GPLL0, 1, 72, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) F(7372800, P_GPLL0, 1, 144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) F(14745600, P_GPLL0, 1, 288, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) F(16000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) F(24000000, P_GPLL0, 1, 3, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) F(32000000, P_GPLL0, 1, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) F(40000000, P_GPLL0, 1, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) F(46400000, P_GPLL0, 1, 29, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) F(48000000, P_GPLL0, 1, 3, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) F(51200000, P_GPLL0, 1, 8, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) F(56000000, P_GPLL0, 1, 7, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) F(58982400, P_GPLL0, 1, 1152, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) F(60000000, P_GPLL0, 1, 3, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .cmd_rcgr = 0x02044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .cmd_rcgr = 0x03034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static struct clk_rcg2 cci_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .cmd_rcgr = 0x51000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .parent_map = gcc_xo_gpll0a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .freq_tbl = ftbl_gcc_camss_cci_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .name = "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .parent_data = gcc_xo_gpll0a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static struct clk_rcg2 camss_gp0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .cmd_rcgr = 0x54000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .name = "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static struct clk_rcg2 camss_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .cmd_rcgr = 0x55000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .name = "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) F(133330000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) F(266670000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static struct clk_rcg2 jpeg0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .cmd_rcgr = 0x57000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .name = "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) F(24000000, P_GPLL0, 1, 1, 45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) F(66670000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static struct clk_rcg2 mclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .cmd_rcgr = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .name = "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static struct clk_rcg2 mclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .cmd_rcgr = 0x53000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .name = "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static struct clk_rcg2 csi0phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .cmd_rcgr = 0x4e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .parent_map = gcc_xo_gpll0_gpll1a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .name = "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static struct clk_rcg2 csi1phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .cmd_rcgr = 0x4f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .parent_map = gcc_xo_gpll0_gpll1a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .name = "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) F(465000000, P_GPLL2, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static struct clk_rcg2 cpp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .cmd_rcgr = 0x58018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .parent_map = gcc_xo_gpll0_gpll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .freq_tbl = ftbl_gcc_camss_cpp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .name = "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .parent_data = gcc_xo_gpll0_gpll2_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* This is not in the documentation but is in the downstream driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static struct clk_rcg2 crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .cmd_rcgr = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .freq_tbl = ftbl_gcc_crypto_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .name = "crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .cmd_rcgr = 0x08004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .freq_tbl = ftbl_gcc_gp1_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .cmd_rcgr = 0x09004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .freq_tbl = ftbl_gcc_gp1_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .cmd_rcgr = 0x0a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .freq_tbl = ftbl_gcc_gp1_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static struct clk_rcg2 byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .cmd_rcgr = 0x4d044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .parent_map = gcc_xo_gpll0a_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .name = "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static struct clk_rcg2 byte1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .cmd_rcgr = 0x4d0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .parent_map = gcc_xo_gpll0a_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .name = "byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static struct clk_rcg2 esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .cmd_rcgr = 0x4d060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .parent_map = gcc_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .freq_tbl = ftbl_gcc_mdss_esc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .name = "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .parent_data = gcc_xo_dsibyte_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static struct clk_rcg2 esc1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .cmd_rcgr = 0x4d0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .parent_map = gcc_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .freq_tbl = ftbl_gcc_mdss_esc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .name = "esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .parent_data = gcc_xo_dsibyte_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) F(50000000, P_GPLL0_AUX, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) F(80000000, P_GPLL0_AUX, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) F(100000000, P_GPLL0_AUX, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) F(160000000, P_GPLL0_AUX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) F(200000000, P_GPLL0_AUX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) F(266670000, P_GPLL0_AUX, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) F(307200000, P_GPLL1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) F(366670000, P_GPLL3_AUX, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static struct clk_rcg2 mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .cmd_rcgr = 0x4d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .freq_tbl = ftbl_gcc_mdss_mdp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .name = "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static struct clk_rcg2 pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .cmd_rcgr = 0x4d000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .parent_map = gcc_xo_gpll0a_dsiphy_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .name = "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static struct clk_rcg2 pclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .cmd_rcgr = 0x4d0b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .parent_map = gcc_xo_gpll0a_dsiphy_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .name = "pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static struct clk_rcg2 vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .cmd_rcgr = 0x4d02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .parent_map = gcc_xo_gpll0a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .freq_tbl = ftbl_gcc_mdss_vsync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .name = "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .parent_data = gcc_xo_gpll0a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) F(64000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* This is not in the documentation but is in the downstream driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .cmd_rcgr = 0x44010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .freq_tbl = ftbl_gcc_pdm2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) F(20000000, P_GPLL0, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) F(177770000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .cmd_rcgr = 0x42004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .freq_tbl = ftbl_gcc_sdcc_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .cmd_rcgr = 0x43004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .freq_tbl = ftbl_gcc_sdcc_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) F(154285000, P_GPLL6, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static struct clk_rcg2 apss_tcu_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .cmd_rcgr = 0x1207c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .freq_tbl = ftbl_gcc_apss_tcu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .name = "apss_tcu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) F(266500000, P_BIMC, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) F(533000000, P_BIMC, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static struct clk_rcg2 bimc_gpu_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .cmd_rcgr = 0x31028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .freq_tbl = ftbl_gcc_bimc_gpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .name = "bimc_gpu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static struct clk_rcg2 usb_hs_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .cmd_rcgr = 0x41010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .freq_tbl = ftbl_gcc_usb_hs_system_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .name = "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) F(64000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static struct clk_rcg2 usb_fs_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .cmd_rcgr = 0x3f010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .freq_tbl = ftbl_gcc_usb_fs_system_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .name = "usb_fs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .parent_data = gcc_xo_gpll6_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) F(60000000, P_GPLL6, 1, 1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static struct clk_rcg2 usb_fs_ic_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .cmd_rcgr = 0x3f034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .name = "usb_fs_ic_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) F(3200000, P_XO, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) F(6400000, P_XO, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) F(40000000, P_GPLL0, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) F(66670000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .cmd_rcgr = 0x1c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .name = "ultaudio_ahbfabric_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .halt_reg = 0x1c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_reg = 0x1c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .halt_reg = 0x1c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .enable_reg = 0x1c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) F(128000, P_XO, 10, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) F(256000, P_XO, 5, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) F(384000, P_XO, 5, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) F(512000, P_XO, 5, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) F(576000, P_XO, 5, 3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) F(705600, P_GPLL1, 16, 1, 80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) F(768000, P_XO, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) F(800000, P_XO, 5, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) F(1024000, P_XO, 5, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) F(1152000, P_XO, 1, 3, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) F(1411200, P_GPLL1, 16, 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) F(1536000, P_XO, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) F(1600000, P_XO, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) F(1728000, P_XO, 5, 9, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) F(2048000, P_XO, 5, 8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) F(2304000, P_XO, 5, 3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) F(2400000, P_XO, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) F(2822400, P_GPLL1, 16, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) F(3072000, P_XO, 5, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) F(4096000, P_GPLL1, 9, 2, 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) F(5644800, P_GPLL1, 16, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) F(6144000, P_GPLL1, 7, 1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) F(8192000, P_GPLL1, 9, 4, 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) F(11289600, P_GPLL1, 16, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) F(12288000, P_GPLL1, 7, 2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .cmd_rcgr = 0x1c054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .name = "ultaudio_lpaif_pri_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .halt_reg = 0x1c068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .enable_reg = 0x1c068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .hw = &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .cmd_rcgr = 0x1c06c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .name = "ultaudio_lpaif_sec_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .halt_reg = 0x1c080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .enable_reg = 0x1c080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .hw = &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .cmd_rcgr = 0x1c084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .parent_map = gcc_xo_gpll1_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .name = "ultaudio_lpaif_aux_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .halt_reg = 0x1c098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .enable_reg = 0x1c098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .hw = &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static struct clk_rcg2 ultaudio_xo_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .cmd_rcgr = 0x1c034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .parent_map = gcc_xo_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .name = "ultaudio_xo_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .parent_data = gcc_xo_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .halt_reg = 0x1c04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .enable_reg = 0x1c04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .name = "gcc_ultaudio_avsync_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .hw = &ultaudio_xo_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static struct clk_branch gcc_ultaudio_stc_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .halt_reg = 0x1c050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .enable_reg = 0x1c050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .name = "gcc_ultaudio_stc_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .hw = &ultaudio_xo_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static const struct freq_tbl ftbl_codec_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) F(12288000, P_XO, 1, 16, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) F(11289600, P_EXT_MCLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static struct clk_rcg2 codec_digcodec_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .cmd_rcgr = 0x1c09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .parent_map = gcc_xo_gpll1_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .freq_tbl = ftbl_codec_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .name = "codec_digcodec_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static struct clk_branch gcc_codec_digcodec_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .halt_reg = 0x1c0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .enable_reg = 0x1c0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .name = "gcc_ultaudio_codec_digcodec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .hw = &codec_digcodec_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .halt_reg = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .enable_reg = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .name = "gcc_ultaudio_pcnoc_mport_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .halt_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .enable_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .name = "gcc_ultaudio_pcnoc_sway_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) F(228570000, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static struct clk_rcg2 vcodec0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .cmd_rcgr = 0x4C000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .name = "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .parent_data = gcc_xo_gpll0_parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .halt_reg = 0x01008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static struct clk_branch gcc_blsp1_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .halt_reg = 0x01004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .enable_reg = 0x01004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .name = "gcc_blsp1_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .halt_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .enable_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .hw = &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .halt_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .enable_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .hw = &blsp1_qup1_spi_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .halt_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .enable_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .hw = &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .halt_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .enable_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .hw = &blsp1_qup2_spi_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .halt_reg = 0x04020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .enable_reg = 0x04020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .hw = &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .halt_reg = 0x0401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .enable_reg = 0x0401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .hw = &blsp1_qup3_spi_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .halt_reg = 0x05020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .enable_reg = 0x05020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .hw = &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .halt_reg = 0x0501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .enable_reg = 0x0501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .hw = &blsp1_qup4_spi_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .halt_reg = 0x06020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .enable_reg = 0x06020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .hw = &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .halt_reg = 0x0601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .enable_reg = 0x0601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .hw = &blsp1_qup5_spi_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .halt_reg = 0x07020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .enable_reg = 0x07020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .name = "gcc_blsp1_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .hw = &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .halt_reg = 0x0701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .enable_reg = 0x0701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .hw = &blsp1_qup6_spi_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .halt_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .enable_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .hw = &blsp1_uart1_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .halt_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .enable_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .hw = &blsp1_uart2_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .halt_reg = 0x1300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static struct clk_branch gcc_camss_cci_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .halt_reg = 0x5101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .enable_reg = 0x5101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .name = "gcc_camss_cci_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static struct clk_branch gcc_camss_cci_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .halt_reg = 0x51018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .enable_reg = 0x51018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .name = "gcc_camss_cci_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .hw = &cci_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static struct clk_branch gcc_camss_csi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .halt_reg = 0x4e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .enable_reg = 0x4e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .name = "gcc_camss_csi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static struct clk_branch gcc_camss_csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .halt_reg = 0x4e03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .enable_reg = 0x4e03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .name = "gcc_camss_csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .hw = &csi0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static struct clk_branch gcc_camss_csi0phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .halt_reg = 0x4e048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .enable_reg = 0x4e048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .name = "gcc_camss_csi0phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .hw = &csi0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static struct clk_branch gcc_camss_csi0pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .halt_reg = 0x4e058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .enable_reg = 0x4e058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .name = "gcc_camss_csi0pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .hw = &csi0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static struct clk_branch gcc_camss_csi0rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .halt_reg = 0x4e050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .enable_reg = 0x4e050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .name = "gcc_camss_csi0rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .hw = &csi0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static struct clk_branch gcc_camss_csi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .halt_reg = 0x4f040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .enable_reg = 0x4f040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .name = "gcc_camss_csi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static struct clk_branch gcc_camss_csi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .halt_reg = 0x4f03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .enable_reg = 0x4f03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .name = "gcc_camss_csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .hw = &csi1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) static struct clk_branch gcc_camss_csi1phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .halt_reg = 0x4f048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .enable_reg = 0x4f048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .name = "gcc_camss_csi1phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .hw = &csi1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) static struct clk_branch gcc_camss_csi1pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .halt_reg = 0x4f058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .enable_reg = 0x4f058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .name = "gcc_camss_csi1pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .hw = &csi1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static struct clk_branch gcc_camss_csi1rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .halt_reg = 0x4f050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .enable_reg = 0x4f050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .name = "gcc_camss_csi1rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .hw = &csi1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) static struct clk_branch gcc_camss_csi_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .halt_reg = 0x58050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .enable_reg = 0x58050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .name = "gcc_camss_csi_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .hw = &vfe0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static struct clk_branch gcc_camss_gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .halt_reg = 0x54018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .enable_reg = 0x54018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .name = "gcc_camss_gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .hw = &camss_gp0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static struct clk_branch gcc_camss_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .halt_reg = 0x55018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .enable_reg = 0x55018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .name = "gcc_camss_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .hw = &camss_gp1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) static struct clk_branch gcc_camss_ispif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .halt_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .enable_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .name = "gcc_camss_ispif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static struct clk_branch gcc_camss_jpeg0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .halt_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .enable_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .name = "gcc_camss_jpeg0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .hw = &jpeg0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static struct clk_branch gcc_camss_jpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .halt_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .enable_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .name = "gcc_camss_jpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) static struct clk_branch gcc_camss_jpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .halt_reg = 0x57028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .enable_reg = 0x57028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .name = "gcc_camss_jpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static struct clk_branch gcc_camss_mclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .halt_reg = 0x52018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .enable_reg = 0x52018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .name = "gcc_camss_mclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .hw = &mclk0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static struct clk_branch gcc_camss_mclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .halt_reg = 0x53018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .enable_reg = 0x53018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .name = "gcc_camss_mclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .hw = &mclk1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static struct clk_branch gcc_camss_micro_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .halt_reg = 0x5600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .enable_reg = 0x5600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .name = "gcc_camss_micro_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static struct clk_branch gcc_camss_csi0phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .halt_reg = 0x4e01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .enable_reg = 0x4e01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .name = "gcc_camss_csi0phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .hw = &csi0phytimer_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) static struct clk_branch gcc_camss_csi1phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .halt_reg = 0x4f01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .enable_reg = 0x4f01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .name = "gcc_camss_csi1phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .hw = &csi1phytimer_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) static struct clk_branch gcc_camss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .halt_reg = 0x5a014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .enable_reg = 0x5a014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .name = "gcc_camss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) static struct clk_branch gcc_camss_top_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .halt_reg = 0x56004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .enable_reg = 0x56004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .name = "gcc_camss_top_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static struct clk_branch gcc_camss_cpp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .halt_reg = 0x58040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .enable_reg = 0x58040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .name = "gcc_camss_cpp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static struct clk_branch gcc_camss_cpp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .halt_reg = 0x5803c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .enable_reg = 0x5803c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .name = "gcc_camss_cpp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .hw = &cpp_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) static struct clk_branch gcc_camss_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .halt_reg = 0x58038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .enable_reg = 0x58038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .name = "gcc_camss_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .hw = &vfe0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) static struct clk_branch gcc_camss_vfe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .halt_reg = 0x58044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .enable_reg = 0x58044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .name = "gcc_camss_vfe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .hw = &camss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) static struct clk_branch gcc_camss_vfe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .halt_reg = 0x58048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .enable_reg = 0x58048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .name = "gcc_camss_vfe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) static struct clk_branch gcc_crypto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .halt_reg = 0x16024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) .name = "gcc_crypto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) static struct clk_branch gcc_crypto_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .halt_reg = 0x16020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .name = "gcc_crypto_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) static struct clk_branch gcc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .halt_reg = 0x1601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .name = "gcc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .hw = &crypto_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) static struct clk_branch gcc_oxili_gmem_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .halt_reg = 0x59024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .enable_reg = 0x59024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .name = "gcc_oxili_gmem_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .hw = &gfx3d_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .halt_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .enable_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .hw = &gp1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .halt_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .enable_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .hw = &gp2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .halt_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .enable_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .hw = &gp3_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) static struct clk_branch gcc_mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .halt_reg = 0x4d07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .enable_reg = 0x4d07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .name = "gcc_mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static struct clk_branch gcc_mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .halt_reg = 0x4d080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .enable_reg = 0x4d080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .name = "gcc_mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) static struct clk_branch gcc_mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .halt_reg = 0x4d094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .enable_reg = 0x4d094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .name = "gcc_mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .hw = &byte0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static struct clk_branch gcc_mdss_byte1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .halt_reg = 0x4d0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .enable_reg = 0x4d0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .name = "gcc_mdss_byte1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .hw = &byte1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) static struct clk_branch gcc_mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .halt_reg = 0x4d098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .enable_reg = 0x4d098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .name = "gcc_mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .hw = &esc0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) static struct clk_branch gcc_mdss_esc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .halt_reg = 0x4d09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .enable_reg = 0x4d09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .name = "gcc_mdss_esc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .hw = &esc1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) static struct clk_branch gcc_mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .halt_reg = 0x4D088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .enable_reg = 0x4D088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .name = "gcc_mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .hw = &mdp_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) static struct clk_branch gcc_mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .halt_reg = 0x4d084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .enable_reg = 0x4d084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .name = "gcc_mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .hw = &pclk0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) static struct clk_branch gcc_mdss_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .halt_reg = 0x4d0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .enable_reg = 0x4d0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .name = "gcc_mdss_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .hw = &pclk1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) static struct clk_branch gcc_mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .halt_reg = 0x4d090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .enable_reg = 0x4d090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .name = "gcc_mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .hw = &vsync_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static struct clk_branch gcc_mss_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .halt_reg = 0x49000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .enable_reg = 0x49000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .name = "gcc_mss_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .halt_reg = 0x49004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .enable_reg = 0x49004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .name = "gcc_mss_q6_bimc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) .hw = &bimc_ddr_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) static struct clk_branch gcc_oxili_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .halt_reg = 0x59028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .enable_reg = 0x59028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .name = "gcc_oxili_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) static struct clk_branch gcc_oxili_gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .halt_reg = 0x59020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .enable_reg = 0x59020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .name = "gcc_oxili_gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .hw = &gfx3d_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .halt_reg = 0x4400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .enable_reg = 0x4400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .hw = &pdm2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .halt_reg = 0x44004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .enable_reg = 0x44004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .halt_reg = 0x13004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .halt_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .enable_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) .halt_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .enable_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) .hw = &sdcc1_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .halt_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .enable_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .halt_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) .enable_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) .hw = &sdcc2_apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) static struct clk_branch gcc_apss_tcu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) .halt_reg = 0x12018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .name = "gcc_apss_tcu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) .hw = &bimc_ddr_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) static struct clk_branch gcc_gfx_tcu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) .halt_reg = 0x12020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .name = "gcc_gfx_tcu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) .hw = &bimc_ddr_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) static struct clk_branch gcc_gfx_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .halt_reg = 0x12010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .name = "gcc_gfx_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) .hw = &bimc_ddr_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static struct clk_branch gcc_mdp_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .halt_reg = 0x1201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) .name = "gcc_mdp_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) static struct clk_branch gcc_venus_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .halt_reg = 0x12014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) .name = "gcc_venus_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) static struct clk_branch gcc_vfe_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) .halt_reg = 0x1203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) .name = "gcc_vfe_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) static struct clk_branch gcc_jpeg_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) .halt_reg = 0x12034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) .name = "gcc_jpeg_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) static struct clk_branch gcc_smmu_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) .halt_reg = 0x12038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .name = "gcc_smmu_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) static struct clk_branch gcc_gtcu_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) .halt_reg = 0x12044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .name = "gcc_gtcu_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) static struct clk_branch gcc_cpp_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) .halt_reg = 0x12040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) .name = "gcc_cpp_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) static struct clk_branch gcc_mdp_rt_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) .halt_reg = 0x1201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) .name = "gcc_mdp_rt_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) static struct clk_branch gcc_bimc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) .halt_reg = 0x31024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) .enable_reg = 0x31024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .name = "gcc_bimc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) .hw = &bimc_gpu_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) static struct clk_branch gcc_bimc_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) .halt_reg = 0x31040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) .enable_reg = 0x31040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) .name = "gcc_bimc_gpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) .hw = &bimc_gpu_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) static struct clk_branch gcc_usb2a_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .halt_reg = 0x4102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .enable_reg = 0x4102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) .name = "gcc_usb2a_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) static struct clk_branch gcc_usb_fs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) .halt_reg = 0x3f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) .enable_reg = 0x3f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) .name = "gcc_usb_fs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) static struct clk_branch gcc_usb_fs_ic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) .halt_reg = 0x3f030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) .enable_reg = 0x3f030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) .name = "gcc_usb_fs_ic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) .hw = &usb_fs_ic_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) static struct clk_branch gcc_usb_fs_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) .halt_reg = 0x3f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) .enable_reg = 0x3f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) .name = "gcc_usb_fs_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) .hw = &usb_fs_system_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) static struct clk_branch gcc_usb_hs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) .halt_reg = 0x41008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) .enable_reg = 0x41008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) .name = "gcc_usb_hs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) static struct clk_branch gcc_usb_hs_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) .halt_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) .enable_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) .name = "gcc_usb_hs_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) .hw = &usb_hs_system_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) static struct clk_branch gcc_venus0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) .halt_reg = 0x4c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) .enable_reg = 0x4c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) .name = "gcc_venus0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) static struct clk_branch gcc_venus0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) .halt_reg = 0x4c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) .enable_reg = 0x4c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) .name = "gcc_venus0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) .hw = &system_noc_bfdcd_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) static struct clk_branch gcc_venus0_vcodec0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) .halt_reg = 0x4c01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) .enable_reg = 0x4c01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) .name = "gcc_venus0_vcodec0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) .hw = &vcodec0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) .halt_reg = 0x4c02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) .enable_reg = 0x4c02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) .name = "gcc_venus0_core0_vcodec0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) .hw = &vcodec0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) .halt_reg = 0x4c034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) .enable_reg = 0x4c034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) .name = "gcc_venus0_core1_vcodec0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) .hw = &vcodec0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) static struct clk_branch gcc_oxili_timer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) .halt_reg = 0x59040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) .enable_reg = 0x59040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) .name = "gcc_oxili_timer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) static struct gdsc venus_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) .gdscr = 0x4c018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) .name = "venus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) .gdscr = 0x4d078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) .name = "mdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) static struct gdsc jpeg_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) .gdscr = 0x5701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) .name = "jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) static struct gdsc vfe_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) .gdscr = 0x58034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) .name = "vfe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) static struct gdsc oxili_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) .gdscr = 0x5901c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) .name = "oxili",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) static struct gdsc venus_core0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) .gdscr = 0x4c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) .name = "venus_core0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) static struct gdsc venus_core1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) .gdscr = 0x4c030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) .name = "venus_core1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) static struct clk_regmap *gcc_msm8939_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) [GPLL0_VOTE] = &gpll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) [BIMC_PLL] = &bimc_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) [BIMC_PLL_VOTE] = &bimc_pll_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) [GPLL1] = &gpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) [GPLL1_VOTE] = &gpll1_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) [GPLL2] = &gpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) [GPLL2_VOTE] = &gpll2_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) [CCI_CLK_SRC] = &cci_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) [CPP_CLK_SRC] = &cpp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) [MDP_CLK_SRC] = &mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) [GPLL3] = &gpll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) [GPLL3_VOTE] = &gpll3_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) [GPLL4_VOTE] = &gpll4_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) [GPLL5] = &gpll5.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) [GPLL5_VOTE] = &gpll5_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) [GPLL6] = &gpll6.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) [GPLL6_VOTE] = &gpll6_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) static struct gdsc *gcc_msm8939_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) [VENUS_GDSC] = &venus_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) [JPEG_GDSC] = &jpeg_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) [VFE_GDSC] = &vfe_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) [OXILI_GDSC] = &oxili_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) static const struct qcom_reset_map gcc_msm8939_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) [GCC_BLSP1_BCR] = { 0x01000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) [GCC_BLSP1_UART1_BCR] = { 0x02038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) [GCC_BLSP1_UART2_BCR] = { 0x03028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) [GCC_BLSP1_UART3_BCR] = { 0x04038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) [GCC_IMEM_BCR] = { 0x0e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) [GCC_SMMU_BCR] = { 0x12000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) [GCC_APSS_TCU_BCR] = { 0x12050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) [GCC_SMMU_XPU_BCR] = { 0x12054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) [GCC_PCNOC_TBU_BCR] = { 0x12058 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) [GCC_PRNG_BCR] = { 0x13000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) [GCC_BOOT_ROM_BCR] = { 0x13008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) [GCC_CRYPTO_BCR] = { 0x16000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) [GCC_SEC_CTRL_BCR] = { 0x1a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) [GCC_DEHR_BCR] = { 0x1f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) [GCC_PCNOC_BCR] = { 0x27018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) [GCC_TCSR_BCR] = { 0x28000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) [GCC_QDSS_BCR] = { 0x29000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) [GCC_DCD_BCR] = { 0x2a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) [GCC_MSG_RAM_BCR] = { 0x2b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) [GCC_MPM_BCR] = { 0x2c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) [GCC_SPMI_BCR] = { 0x2e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) [GCC_SPDM_BCR] = { 0x2f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) [GCC_MM_SPDM_BCR] = { 0x2f024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) [GCC_BIMC_BCR] = { 0x31000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) [GCC_RBCPR_BCR] = { 0x33000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) [GCC_TLMM_BCR] = { 0x34000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) [GCC_USB_FS_BCR] = { 0x3f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) [GCC_USB_HS_BCR] = { 0x41000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) [GCC_USB2A_PHY_BCR] = { 0x41028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) [GCC_SDCC1_BCR] = { 0x42000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) [GCC_SDCC2_BCR] = { 0x43000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) [GCC_PDM_BCR] = { 0x44000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) [GCC_MMSS_BCR] = { 0x4b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) [GCC_VENUS0_BCR] = { 0x4c014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) [GCC_MDSS_BCR] = { 0x4d074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) [GCC_CAMSS_CCI_BCR] = { 0x51014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) [GCC_CAMSS_GP0_BCR] = { 0x54014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) [GCC_CAMSS_GP1_BCR] = { 0x55014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) [GCC_CAMSS_TOP_BCR] = { 0x56000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) [GCC_CAMSS_VFE_BCR] = { 0x58030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) [GCC_OXILI_BCR] = { 0x59018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) [GCC_GMEM_BCR] = { 0x5902c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) [GCC_MDP_TBU_BCR] = { 0x62000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) [GCC_GFX_TBU_BCR] = { 0x63000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) [GCC_GFX_TCU_BCR] = { 0x64000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) [GCC_GTCU_AHB_BCR] = { 0x68000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) [GCC_SMMU_CFG_BCR] = { 0x69000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) [GCC_VFE_TBU_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) [GCC_VENUS_TBU_BCR] = { 0x6b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) [GCC_JPEG_TBU_BCR] = { 0x6c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) [GCC_CPP_TBU_BCR] = { 0x6e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) [GCC_SMMU_CATS_BCR] = { 0x7c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) static const struct regmap_config gcc_msm8939_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) .max_register = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) static const struct qcom_cc_desc gcc_msm8939_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) .config = &gcc_msm8939_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) .clks = gcc_msm8939_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) .resets = gcc_msm8939_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) .gdscs = gcc_msm8939_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) static const struct of_device_id gcc_msm8939_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) { .compatible = "qcom,gcc-msm8939" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) static int gcc_msm8939_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) static struct platform_driver gcc_msm8939_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) .probe = gcc_msm8939_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) .name = "gcc-msm8939",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) .of_match_table = gcc_msm8939_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) static int __init gcc_msm8939_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) return platform_driver_register(&gcc_msm8939_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) core_initcall(gcc_msm8939_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) static void __exit gcc_msm8939_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) platform_driver_unregister(&gcc_msm8939_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) module_exit(gcc_msm8939_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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