^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-msm8916.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,gcc-msm8916.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL0_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_BIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_GPLL1_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_GPLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_GPLL2_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_DSI0_PHYPLL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_DSI0_PHYPLL_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_EXT_PRI_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_EXT_SEC_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_EXT_MCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct parent_map gcc_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char * const gcc_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { P_BIMC, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const char * const gcc_xo_gpll0_bimc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "bimc_pll_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { P_GPLL0_AUX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { P_GPLL2_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "gpll2_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { P_GPLL2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char * const gcc_xo_gpll0_gpll2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "gpll2_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct parent_map gcc_xo_gpll0a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { P_GPLL0_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char * const gcc_xo_gpll0a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { P_GPLL1_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { P_SLEEP_CLK, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { P_GPLL1_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char * const gcc_xo_gpll0_gpll1a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct parent_map gcc_xo_dsibyte_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { P_XO, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { P_DSI0_PHYPLL_BYTE, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char * const gcc_xo_dsibyte[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "dsi0pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { P_GPLL0_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { P_DSI0_PHYPLL_BYTE, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const char * const gcc_xo_gpll0a_dsibyte[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "dsi0pllbyte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { P_DSI0_PHYPLL_DSI, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const char * const gcc_xo_gpll0_dsiphy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { P_GPLL0_AUX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { P_DSI0_PHYPLL_DSI, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const char * const gcc_xo_gpll0a_dsiphy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "dsi0pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { P_GPLL0_AUX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { P_GPLL1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { P_GPLL2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "gpll2_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { P_GPLL1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { P_EXT_PRI_I2S, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { P_EXT_MCLK, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "ext_pri_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "ext_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { P_EXT_SEC_I2S, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { P_EXT_MCLK, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "ext_sec_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "ext_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct parent_map gcc_xo_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char * const gcc_xo_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { P_GPLL1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { P_EXT_MCLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const char * const gcc_xo_gpll1_emclk_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "ext_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct clk_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .l_reg = 0x21004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .m_reg = 0x21008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .n_reg = 0x2100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .config_reg = 0x21010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .mode_reg = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .status_reg = 0x2101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct clk_regmap gpll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct clk_pll gpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .l_reg = 0x20004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .m_reg = 0x20008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .n_reg = 0x2000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .config_reg = 0x20010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .mode_reg = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .status_reg = 0x2001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .name = "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct clk_regmap gpll1_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .parent_names = (const char *[]){ "gpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct clk_pll gpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .l_reg = 0x4a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .m_reg = 0x4a008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .n_reg = 0x4a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .config_reg = 0x4a010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .mode_reg = 0x4a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .status_reg = 0x4a01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .name = "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct clk_regmap gpll2_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "gpll2_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .parent_names = (const char *[]){ "gpll2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct clk_pll bimc_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .l_reg = 0x23004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .m_reg = 0x23008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .n_reg = 0x2300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .config_reg = 0x23010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .mode_reg = 0x23000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .status_reg = 0x2301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .name = "bimc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct clk_regmap bimc_pll_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .enable_reg = 0x45000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "bimc_pll_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .parent_names = (const char *[]){ "bimc_pll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .cmd_rcgr = 0x27000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .parent_map = gcc_xo_gpll0_bimc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .parent_names = gcc_xo_gpll0_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct clk_rcg2 system_noc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .cmd_rcgr = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .parent_map = gcc_xo_gpll0_bimc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .name = "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .parent_names = gcc_xo_gpll0_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) F(40000000, P_GPLL0, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct clk_rcg2 camss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .cmd_rcgr = 0x5a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .freq_tbl = ftbl_gcc_camss_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct freq_tbl ftbl_apss_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) F(133330000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct clk_rcg2 apss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .cmd_rcgr = 0x46000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .freq_tbl = ftbl_apss_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .name = "apss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static struct clk_rcg2 csi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .cmd_rcgr = 0x4e020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct clk_rcg2 csi1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .cmd_rcgr = 0x4f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) F(50000000, P_GPLL0_AUX, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) F(80000000, P_GPLL0_AUX, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) F(100000000, P_GPLL0_AUX, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) F(160000000, P_GPLL0_AUX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) F(200000000, P_GPLL0_AUX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) F(266670000, P_GPLL0_AUX, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) F(294912000, P_GPLL1, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) F(310000000, P_GPLL2, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) F(400000000, P_GPLL0_AUX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct clk_rcg2 gfx3d_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .cmd_rcgr = 0x59000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .name = "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) F(177780000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) F(266670000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) F(465000000, P_GPLL2, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct clk_rcg2 vfe0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .cmd_rcgr = 0x58000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .parent_map = gcc_xo_gpll0_gpll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .freq_tbl = ftbl_gcc_camss_vfe0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .name = "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .parent_names = gcc_xo_gpll0_gpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .cmd_rcgr = 0x0200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) F(100000, P_XO, 16, 2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) F(250000, P_XO, 16, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) F(500000, P_XO, 8, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) F(1000000, P_XO, 4, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) F(16000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .cmd_rcgr = 0x02024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .cmd_rcgr = 0x03000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .cmd_rcgr = 0x03014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .cmd_rcgr = 0x04000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .cmd_rcgr = 0x04024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .cmd_rcgr = 0x05000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .cmd_rcgr = 0x05024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .cmd_rcgr = 0x06000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .cmd_rcgr = 0x06024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .cmd_rcgr = 0x07000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .cmd_rcgr = 0x07024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) F(3686400, P_GPLL0, 1, 72, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) F(7372800, P_GPLL0, 1, 144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) F(14745600, P_GPLL0, 1, 288, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) F(16000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) F(24000000, P_GPLL0, 1, 3, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) F(32000000, P_GPLL0, 1, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) F(40000000, P_GPLL0, 1, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) F(46400000, P_GPLL0, 1, 29, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) F(48000000, P_GPLL0, 1, 3, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) F(51200000, P_GPLL0, 1, 8, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) F(56000000, P_GPLL0, 1, 7, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) F(58982400, P_GPLL0, 1, 1152, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) F(60000000, P_GPLL0, 1, 3, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .cmd_rcgr = 0x02044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .cmd_rcgr = 0x03034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct clk_rcg2 cci_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .cmd_rcgr = 0x51000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .parent_map = gcc_xo_gpll0a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .freq_tbl = ftbl_gcc_camss_cci_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .name = "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .parent_names = gcc_xo_gpll0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static struct clk_rcg2 camss_gp0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .cmd_rcgr = 0x54000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .name = "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .parent_names = gcc_xo_gpll0_gpll1a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static struct clk_rcg2 camss_gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .cmd_rcgr = 0x55000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .name = "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .parent_names = gcc_xo_gpll0_gpll1a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) F(133330000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) F(266670000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static struct clk_rcg2 jpeg0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .cmd_rcgr = 0x57000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .name = "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) F(23880000, P_GPLL0, 1, 2, 67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) F(66670000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static struct clk_rcg2 mclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .cmd_rcgr = 0x52000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .name = "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .parent_names = gcc_xo_gpll0_gpll1a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static struct clk_rcg2 mclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .cmd_rcgr = 0x53000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .name = "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .parent_names = gcc_xo_gpll0_gpll1a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static struct clk_rcg2 csi0phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .cmd_rcgr = 0x4e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .parent_map = gcc_xo_gpll0_gpll1a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .parent_names = gcc_xo_gpll0_gpll1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static struct clk_rcg2 csi1phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .cmd_rcgr = 0x4f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .parent_map = gcc_xo_gpll0_gpll1a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .name = "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .parent_names = gcc_xo_gpll0_gpll1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) F(465000000, P_GPLL2, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static struct clk_rcg2 cpp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .cmd_rcgr = 0x58018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .parent_map = gcc_xo_gpll0_gpll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .freq_tbl = ftbl_gcc_camss_cpp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .parent_names = gcc_xo_gpll0_gpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static struct clk_rcg2 crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .cmd_rcgr = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .freq_tbl = ftbl_gcc_crypto_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = "crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .cmd_rcgr = 0x08004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .freq_tbl = ftbl_gcc_gp1_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .parent_names = gcc_xo_gpll0_gpll1a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .cmd_rcgr = 0x09004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .freq_tbl = ftbl_gcc_gp1_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .parent_names = gcc_xo_gpll0_gpll1a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .cmd_rcgr = 0x0a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .freq_tbl = ftbl_gcc_gp1_3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .parent_names = gcc_xo_gpll0_gpll1a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static struct clk_rcg2 byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .cmd_rcgr = 0x4d044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .parent_map = gcc_xo_gpll0a_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .name = "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .parent_names = gcc_xo_gpll0a_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static struct clk_rcg2 esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .cmd_rcgr = 0x4d05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .parent_map = gcc_xo_dsibyte_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .freq_tbl = ftbl_gcc_mdss_esc0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .name = "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .parent_names = gcc_xo_dsibyte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) F(177780000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) F(266670000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static struct clk_rcg2 mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .cmd_rcgr = 0x4d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .parent_map = gcc_xo_gpll0_dsiphy_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .freq_tbl = ftbl_gcc_mdss_mdp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .name = "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .parent_names = gcc_xo_gpll0_dsiphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static struct clk_rcg2 pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .cmd_rcgr = 0x4d000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .parent_map = gcc_xo_gpll0a_dsiphy_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .name = "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .parent_names = gcc_xo_gpll0a_dsiphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static struct clk_rcg2 vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .cmd_rcgr = 0x4d02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .parent_map = gcc_xo_gpll0a_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .freq_tbl = ftbl_gcc_mdss_vsync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .name = "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .parent_names = gcc_xo_gpll0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) F(64000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .cmd_rcgr = 0x44010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .freq_tbl = ftbl_gcc_pdm2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) F(20000000, P_GPLL0, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) F(177770000, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .cmd_rcgr = 0x42004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) F(20000000, P_GPLL0, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .cmd_rcgr = 0x43004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) F(155000000, P_GPLL2, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) F(310000000, P_GPLL2, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static struct clk_rcg2 apss_tcu_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .cmd_rcgr = 0x1207c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .freq_tbl = ftbl_gcc_apss_tcu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .name = "apss_tcu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) F(266500000, P_BIMC, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) F(533000000, P_BIMC, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static struct clk_rcg2 bimc_gpu_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .cmd_rcgr = 0x31028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .parent_map = gcc_xo_gpll0_bimc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .freq_tbl = ftbl_gcc_bimc_gpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .name = "bimc_gpu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .parent_names = gcc_xo_gpll0_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static struct clk_rcg2 usb_hs_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .cmd_rcgr = 0x41010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .freq_tbl = ftbl_gcc_usb_hs_system_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .name = "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) F(3200000, P_XO, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) F(6400000, P_XO, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) F(40000000, P_GPLL0, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) F(66670000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .cmd_rcgr = 0x1c010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .name = "ultaudio_ahbfabric_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .parent_names = gcc_xo_gpll0_gpll1_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .halt_reg = 0x1c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .enable_reg = 0x1c028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "ultaudio_ahbfabric_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_reg = 0x1c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .enable_reg = 0x1c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "ultaudio_ahbfabric_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) F(128000, P_XO, 10, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) F(256000, P_XO, 5, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) F(384000, P_XO, 5, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) F(512000, P_XO, 5, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) F(576000, P_XO, 5, 3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) F(705600, P_GPLL1, 16, 1, 80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) F(768000, P_XO, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) F(800000, P_XO, 5, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) F(1024000, P_XO, 5, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) F(1152000, P_XO, 1, 3, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) F(1411200, P_GPLL1, 16, 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) F(1536000, P_XO, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) F(1600000, P_XO, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) F(1728000, P_XO, 5, 9, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) F(2048000, P_XO, 5, 8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) F(2304000, P_XO, 5, 3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) F(2400000, P_XO, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) F(2822400, P_GPLL1, 16, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) F(3072000, P_XO, 5, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) F(4096000, P_GPLL1, 9, 2, 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) F(5644800, P_GPLL1, 16, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) F(6144000, P_GPLL1, 7, 1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) F(8192000, P_GPLL1, 9, 4, 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) F(11289600, P_GPLL1, 16, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) F(12288000, P_GPLL1, 7, 2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .cmd_rcgr = 0x1c054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .name = "ultaudio_lpaif_pri_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .halt_reg = 0x1c068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .enable_reg = 0x1c068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) "ultaudio_lpaif_pri_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .cmd_rcgr = 0x1c06c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .name = "ultaudio_lpaif_sec_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .halt_reg = 0x1c080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .enable_reg = 0x1c080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) "ultaudio_lpaif_sec_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .cmd_rcgr = 0x1c084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .parent_map = gcc_xo_gpll1_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .name = "ultaudio_lpaif_aux_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .halt_reg = 0x1c098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .enable_reg = 0x1c098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) "ultaudio_lpaif_aux_i2s_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static struct clk_rcg2 ultaudio_xo_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .cmd_rcgr = 0x1c034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .parent_map = gcc_xo_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .name = "ultaudio_xo_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .parent_names = gcc_xo_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .halt_reg = 0x1c04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .enable_reg = 0x1c04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .name = "gcc_ultaudio_avsync_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) "ultaudio_xo_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static struct clk_branch gcc_ultaudio_stc_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .halt_reg = 0x1c050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .enable_reg = 0x1c050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .name = "gcc_ultaudio_stc_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) "ultaudio_xo_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const struct freq_tbl ftbl_codec_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) F(12288000, P_XO, 1, 16, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) F(11289600, P_EXT_MCLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static struct clk_rcg2 codec_digcodec_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .cmd_rcgr = 0x1c09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .parent_map = gcc_xo_gpll1_emclk_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .freq_tbl = ftbl_codec_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .name = "codec_digcodec_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .parent_names = gcc_xo_gpll1_emclk_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static struct clk_branch gcc_codec_digcodec_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .halt_reg = 0x1c0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .enable_reg = 0x1c0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .name = "gcc_ultaudio_codec_digcodec_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) "codec_digcodec_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .halt_reg = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .enable_reg = 0x1c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .name = "gcc_ultaudio_pcnoc_mport_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .halt_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .enable_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .name = "gcc_ultaudio_pcnoc_sway_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) F(228570000, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static struct clk_rcg2 vcodec0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .cmd_rcgr = 0x4C000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .name = "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .halt_reg = 0x01008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static struct clk_branch gcc_blsp1_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .halt_reg = 0x01004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .enable_reg = 0x01004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .name = "gcc_blsp1_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .halt_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .enable_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .halt_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .enable_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .halt_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .enable_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .halt_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .enable_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .halt_reg = 0x04020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .enable_reg = 0x04020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .halt_reg = 0x0401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .enable_reg = 0x0401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .halt_reg = 0x05020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .enable_reg = 0x05020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .halt_reg = 0x0501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .enable_reg = 0x0501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .halt_reg = 0x06020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .enable_reg = 0x06020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .halt_reg = 0x0601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .enable_reg = 0x0601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .halt_reg = 0x07020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .enable_reg = 0x07020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .name = "gcc_blsp1_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .halt_reg = 0x0701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .enable_reg = 0x0701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .halt_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .enable_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .halt_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .enable_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .halt_reg = 0x1300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static struct clk_branch gcc_camss_cci_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .halt_reg = 0x5101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .enable_reg = 0x5101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .name = "gcc_camss_cci_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static struct clk_branch gcc_camss_cci_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .halt_reg = 0x51018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .enable_reg = 0x51018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .name = "gcc_camss_cci_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) "cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static struct clk_branch gcc_camss_csi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .halt_reg = 0x4e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .enable_reg = 0x4e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .name = "gcc_camss_csi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static struct clk_branch gcc_camss_csi0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .halt_reg = 0x4e03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .enable_reg = 0x4e03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .name = "gcc_camss_csi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static struct clk_branch gcc_camss_csi0phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .halt_reg = 0x4e048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .enable_reg = 0x4e048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .name = "gcc_camss_csi0phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static struct clk_branch gcc_camss_csi0pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .halt_reg = 0x4e058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .enable_reg = 0x4e058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .name = "gcc_camss_csi0pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static struct clk_branch gcc_camss_csi0rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .halt_reg = 0x4e050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .enable_reg = 0x4e050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .name = "gcc_camss_csi0rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) "csi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static struct clk_branch gcc_camss_csi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .halt_reg = 0x4f040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .enable_reg = 0x4f040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .name = "gcc_camss_csi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static struct clk_branch gcc_camss_csi1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .halt_reg = 0x4f03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .enable_reg = 0x4f03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .name = "gcc_camss_csi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static struct clk_branch gcc_camss_csi1phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .halt_reg = 0x4f048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .enable_reg = 0x4f048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .name = "gcc_camss_csi1phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) static struct clk_branch gcc_camss_csi1pix_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .halt_reg = 0x4f058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .enable_reg = 0x4f058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .name = "gcc_camss_csi1pix_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static struct clk_branch gcc_camss_csi1rdi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .halt_reg = 0x4f050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .enable_reg = 0x4f050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .name = "gcc_camss_csi1rdi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) "csi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static struct clk_branch gcc_camss_csi_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .halt_reg = 0x58050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .enable_reg = 0x58050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .name = "gcc_camss_csi_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static struct clk_branch gcc_camss_gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .halt_reg = 0x54018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .enable_reg = 0x54018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .name = "gcc_camss_gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) "camss_gp0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static struct clk_branch gcc_camss_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .halt_reg = 0x55018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .enable_reg = 0x55018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .name = "gcc_camss_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) "camss_gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static struct clk_branch gcc_camss_ispif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .halt_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .enable_reg = 0x50004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .name = "gcc_camss_ispif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static struct clk_branch gcc_camss_jpeg0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .halt_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .enable_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .name = "gcc_camss_jpeg0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) "jpeg0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static struct clk_branch gcc_camss_jpeg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .halt_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .enable_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .name = "gcc_camss_jpeg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) static struct clk_branch gcc_camss_jpeg_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .halt_reg = 0x57028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .enable_reg = 0x57028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .name = "gcc_camss_jpeg_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static struct clk_branch gcc_camss_mclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .halt_reg = 0x52018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .enable_reg = 0x52018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .name = "gcc_camss_mclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) "mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static struct clk_branch gcc_camss_mclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .halt_reg = 0x53018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .enable_reg = 0x53018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .name = "gcc_camss_mclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) "mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) static struct clk_branch gcc_camss_micro_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .halt_reg = 0x5600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .enable_reg = 0x5600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .name = "gcc_camss_micro_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static struct clk_branch gcc_camss_csi0phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .halt_reg = 0x4e01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .enable_reg = 0x4e01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .name = "gcc_camss_csi0phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) "csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static struct clk_branch gcc_camss_csi1phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .halt_reg = 0x4f01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .enable_reg = 0x4f01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .name = "gcc_camss_csi1phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) "csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static struct clk_branch gcc_camss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .halt_reg = 0x5a014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .enable_reg = 0x5a014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .name = "gcc_camss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static struct clk_branch gcc_camss_top_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .halt_reg = 0x56004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .enable_reg = 0x56004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .name = "gcc_camss_top_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static struct clk_branch gcc_camss_cpp_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .halt_reg = 0x58040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .enable_reg = 0x58040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .name = "gcc_camss_cpp_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static struct clk_branch gcc_camss_cpp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .halt_reg = 0x5803c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .enable_reg = 0x5803c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .name = "gcc_camss_cpp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) "cpp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) static struct clk_branch gcc_camss_vfe0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .halt_reg = 0x58038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .enable_reg = 0x58038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .name = "gcc_camss_vfe0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) "vfe0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) static struct clk_branch gcc_camss_vfe_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .halt_reg = 0x58044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .enable_reg = 0x58044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .name = "gcc_camss_vfe_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) "camss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) static struct clk_branch gcc_camss_vfe_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .halt_reg = 0x58048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .enable_reg = 0x58048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .name = "gcc_camss_vfe_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) static struct clk_branch gcc_crypto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .halt_reg = 0x16024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .name = "gcc_crypto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) static struct clk_branch gcc_crypto_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .halt_reg = 0x16020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .name = "gcc_crypto_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static struct clk_branch gcc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .halt_reg = 0x1601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .name = "gcc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) "crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static struct clk_branch gcc_oxili_gmem_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .halt_reg = 0x59024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enable_reg = 0x59024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .name = "gcc_oxili_gmem_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .halt_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .enable_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .halt_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .enable_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .halt_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .enable_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) static struct clk_branch gcc_mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .halt_reg = 0x4d07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .enable_reg = 0x4d07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .name = "gcc_mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static struct clk_branch gcc_mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .halt_reg = 0x4d080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .enable_reg = 0x4d080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .name = "gcc_mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static struct clk_branch gcc_mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .halt_reg = 0x4d094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .enable_reg = 0x4d094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .name = "gcc_mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) "byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) static struct clk_branch gcc_mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .halt_reg = 0x4d098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .enable_reg = 0x4d098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .name = "gcc_mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) "esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static struct clk_branch gcc_mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .halt_reg = 0x4D088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .enable_reg = 0x4D088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .name = "gcc_mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) "mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) static struct clk_branch gcc_mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .halt_reg = 0x4d084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .enable_reg = 0x4d084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .name = "gcc_mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) "pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static struct clk_branch gcc_mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .halt_reg = 0x4d090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .enable_reg = 0x4d090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .name = "gcc_mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) "vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) static struct clk_branch gcc_mss_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .halt_reg = 0x49000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .enable_reg = 0x49000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .name = "gcc_mss_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .halt_reg = 0x49004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .enable_reg = 0x49004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .name = "gcc_mss_q6_bimc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) "bimc_ddr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) static struct clk_branch gcc_oxili_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .halt_reg = 0x59028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .enable_reg = 0x59028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .name = "gcc_oxili_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static struct clk_branch gcc_oxili_gfx3d_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .halt_reg = 0x59020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .enable_reg = 0x59020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .name = "gcc_oxili_gfx3d_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) "gfx3d_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .halt_reg = 0x4400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .enable_reg = 0x4400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .halt_reg = 0x44004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .enable_reg = 0x44004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .halt_reg = 0x13004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .enable_reg = 0x45004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .halt_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .enable_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .halt_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .enable_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .halt_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .enable_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .halt_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .enable_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) static struct clk_rcg2 bimc_ddr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .cmd_rcgr = 0x32004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .parent_map = gcc_xo_gpll0_bimc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .name = "bimc_ddr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .parent_names = gcc_xo_gpll0_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) static struct clk_branch gcc_apss_tcu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .halt_reg = 0x12018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .name = "gcc_apss_tcu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) "bimc_ddr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static struct clk_branch gcc_gfx_tcu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .halt_reg = 0x12020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .name = "gcc_gfx_tcu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) "bimc_ddr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) static struct clk_branch gcc_gtcu_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .halt_reg = 0x12044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .name = "gcc_gtcu_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) static struct clk_branch gcc_bimc_gfx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .halt_reg = 0x31024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .enable_reg = 0x31024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .name = "gcc_bimc_gfx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) "bimc_gpu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) static struct clk_branch gcc_bimc_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .halt_reg = 0x31040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .enable_reg = 0x31040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .name = "gcc_bimc_gpu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) "bimc_gpu_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static struct clk_branch gcc_jpeg_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .halt_reg = 0x12034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .name = "gcc_jpeg_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) static struct clk_branch gcc_mdp_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .halt_reg = 0x1201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .name = "gcc_mdp_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) static struct clk_branch gcc_smmu_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .halt_reg = 0x12038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .name = "gcc_smmu_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) static struct clk_branch gcc_venus_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) .halt_reg = 0x12014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .name = "gcc_venus_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) static struct clk_branch gcc_vfe_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .halt_reg = 0x1203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .enable_reg = 0x4500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .name = "gcc_vfe_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) static struct clk_branch gcc_usb2a_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .halt_reg = 0x4102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .enable_reg = 0x4102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .name = "gcc_usb2a_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static struct clk_branch gcc_usb_hs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .halt_reg = 0x41008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .enable_reg = 0x41008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .name = "gcc_usb_hs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) static struct clk_branch gcc_usb_hs_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .halt_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .enable_reg = 0x41004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .name = "gcc_usb_hs_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) static struct clk_branch gcc_venus0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .halt_reg = 0x4c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .enable_reg = 0x4c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .name = "gcc_venus0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static struct clk_branch gcc_venus0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .halt_reg = 0x4c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .enable_reg = 0x4c024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .name = "gcc_venus0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) static struct clk_branch gcc_venus0_vcodec0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .halt_reg = 0x4c01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .enable_reg = 0x4c01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .name = "gcc_venus0_vcodec0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) "vcodec0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) static struct gdsc venus_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .gdscr = 0x4c018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .name = "venus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .gdscr = 0x4d078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) .name = "mdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) static struct gdsc jpeg_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .gdscr = 0x5701c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .name = "jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) static struct gdsc vfe_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) .gdscr = 0x58034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) .name = "vfe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) static struct gdsc oxili_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .gdscr = 0x5901c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .name = "oxili",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static struct clk_regmap *gcc_msm8916_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) [GPLL0_VOTE] = &gpll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) [BIMC_PLL] = &bimc_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) [BIMC_PLL_VOTE] = &bimc_pll_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) [GPLL1] = &gpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) [GPLL1_VOTE] = &gpll1_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) [GPLL2] = &gpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) [GPLL2_VOTE] = &gpll2_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) [CCI_CLK_SRC] = &cci_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) [CPP_CLK_SRC] = &cpp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) [MDP_CLK_SRC] = &mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) static struct gdsc *gcc_msm8916_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) [VENUS_GDSC] = &venus_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) [JPEG_GDSC] = &jpeg_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) [VFE_GDSC] = &vfe_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) [OXILI_GDSC] = &oxili_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) static const struct qcom_reset_map gcc_msm8916_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) [GCC_BLSP1_BCR] = { 0x01000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) [GCC_BLSP1_UART1_BCR] = { 0x02038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) [GCC_BLSP1_UART2_BCR] = { 0x03028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) [GCC_IMEM_BCR] = { 0x0e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) [GCC_SMMU_BCR] = { 0x12000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) [GCC_APSS_TCU_BCR] = { 0x12050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) [GCC_SMMU_XPU_BCR] = { 0x12054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) [GCC_PCNOC_TBU_BCR] = { 0x12058 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) [GCC_PRNG_BCR] = { 0x13000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) [GCC_BOOT_ROM_BCR] = { 0x13008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) [GCC_CRYPTO_BCR] = { 0x16000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) [GCC_SEC_CTRL_BCR] = { 0x1a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) [GCC_DEHR_BCR] = { 0x1f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) [GCC_PCNOC_BCR] = { 0x27018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) [GCC_TCSR_BCR] = { 0x28000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) [GCC_QDSS_BCR] = { 0x29000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) [GCC_DCD_BCR] = { 0x2a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) [GCC_MSG_RAM_BCR] = { 0x2b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) [GCC_MPM_BCR] = { 0x2c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) [GCC_SPMI_BCR] = { 0x2e000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) [GCC_SPDM_BCR] = { 0x2f000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) [GCC_MM_SPDM_BCR] = { 0x2f024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) [GCC_BIMC_BCR] = { 0x31000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) [GCC_RBCPR_BCR] = { 0x33000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) [GCC_TLMM_BCR] = { 0x34000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) [GCC_USB_HS_BCR] = { 0x41000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) [GCC_USB2A_PHY_BCR] = { 0x41028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) [GCC_SDCC1_BCR] = { 0x42000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) [GCC_SDCC2_BCR] = { 0x43000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) [GCC_PDM_BCR] = { 0x44000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) [GCC_MMSS_BCR] = { 0x4b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) [GCC_VENUS0_BCR] = { 0x4c014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) [GCC_MDSS_BCR] = { 0x4d074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [GCC_CAMSS_CCI_BCR] = { 0x51014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [GCC_CAMSS_GP0_BCR] = { 0x54014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [GCC_CAMSS_GP1_BCR] = { 0x55014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) [GCC_CAMSS_TOP_BCR] = { 0x56000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [GCC_CAMSS_VFE_BCR] = { 0x58030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) [GCC_OXILI_BCR] = { 0x59018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [GCC_GMEM_BCR] = { 0x5902c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [GCC_MDP_TBU_BCR] = { 0x62000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [GCC_GFX_TBU_BCR] = { 0x63000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) [GCC_GFX_TCU_BCR] = { 0x64000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [GCC_GTCU_AHB_BCR] = { 0x68000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) [GCC_SMMU_CFG_BCR] = { 0x69000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) [GCC_VFE_TBU_BCR] = { 0x6a000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) [GCC_VENUS_TBU_BCR] = { 0x6b000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) [GCC_JPEG_TBU_BCR] = { 0x6c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [GCC_SMMU_CATS_BCR] = { 0x7c000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) static const struct regmap_config gcc_msm8916_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .max_register = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) static const struct qcom_cc_desc gcc_msm8916_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) .config = &gcc_msm8916_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) .clks = gcc_msm8916_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .resets = gcc_msm8916_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) .gdscs = gcc_msm8916_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) static const struct of_device_id gcc_msm8916_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) { .compatible = "qcom,gcc-msm8916" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static int gcc_msm8916_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) ret = qcom_cc_register_sleep_clk(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) return qcom_cc_probe(pdev, &gcc_msm8916_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) static struct platform_driver gcc_msm8916_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) .probe = gcc_msm8916_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) .name = "gcc-msm8916",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) .of_match_table = gcc_msm8916_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) static int __init gcc_msm8916_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) return platform_driver_register(&gcc_msm8916_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) core_initcall(gcc_msm8916_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) static void __exit gcc_msm8916_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) platform_driver_unregister(&gcc_msm8916_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) module_exit(gcc_msm8916_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) MODULE_ALIAS("platform:gcc-msm8916");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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