^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-msm8660.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,gcc-msm8660.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct clk_pll pll8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .l_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .m_reg = 0x3148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .n_reg = 0x314c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .config_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .mode_reg = 0x3140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .status_reg = 0x3158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .name = "pll8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct clk_regmap pll8_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .name = "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .parent_names = (const char *[]){ "pll8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) P_PXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) P_PLL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) P_CXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct parent_map gcc_pxo_pll8_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { P_PLL8, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char * const gcc_pxo_pll8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { P_PLL8, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { P_CXO, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char * const gcc_pxo_pll8_cxo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct freq_tbl clk_tbl_gsbi_uart[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 1843200, P_PLL8, 2, 6, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 3686400, P_PLL8, 2, 12, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 7372800, P_PLL8, 2, 24, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 14745600, P_PLL8, 2, 48, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 32000000, P_PLL8, 4, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 40000000, P_PLL8, 1, 5, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 46400000, P_PLL8, 1, 29, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 56000000, P_PLL8, 1, 7, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { 58982400, P_PLL8, 1, 96, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct clk_rcg gsbi1_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .ns_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .md_reg = 0x29d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct clk_branch gsbi1_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "gsbi1_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct clk_rcg gsbi2_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .ns_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .md_reg = 0x29f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clk_branch gsbi2_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "gsbi2_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct clk_rcg gsbi3_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .ns_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .md_reg = 0x2a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .enable_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "gsbi3_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct clk_branch gsbi3_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .enable_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "gsbi3_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "gsbi3_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct clk_rcg gsbi4_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .ns_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .md_reg = 0x2a30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct clk_branch gsbi4_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "gsbi4_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct clk_rcg gsbi5_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .ns_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .md_reg = 0x2a50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct clk_branch gsbi5_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "gsbi5_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct clk_rcg gsbi6_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .ns_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .md_reg = 0x2a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .enable_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .name = "gsbi6_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct clk_branch gsbi6_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .enable_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "gsbi6_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "gsbi6_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct clk_rcg gsbi7_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .ns_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .md_reg = 0x2a90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .enable_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "gsbi7_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct clk_branch gsbi7_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .enable_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "gsbi7_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "gsbi7_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct clk_rcg gsbi8_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .ns_reg = 0x2ab4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .md_reg = 0x2ab0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .enable_reg = 0x2ab4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .name = "gsbi8_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static struct clk_branch gsbi8_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .enable_reg = 0x2ab4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = "gsbi8_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .parent_names = (const char *[]){ "gsbi8_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct clk_rcg gsbi9_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .ns_reg = 0x2ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .md_reg = 0x2ad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .enable_reg = 0x2ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .name = "gsbi9_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct clk_branch gsbi9_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .enable_reg = 0x2ad4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "gsbi9_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .parent_names = (const char *[]){ "gsbi9_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct clk_rcg gsbi10_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .ns_reg = 0x2af4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .md_reg = 0x2af0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .enable_reg = 0x2af4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .name = "gsbi10_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static struct clk_branch gsbi10_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .enable_reg = 0x2af4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .name = "gsbi10_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .parent_names = (const char *[]){ "gsbi10_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static struct clk_rcg gsbi11_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .ns_reg = 0x2b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .md_reg = 0x2b10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .enable_reg = 0x2b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .name = "gsbi11_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static struct clk_branch gsbi11_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .enable_reg = 0x2b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .name = "gsbi11_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .parent_names = (const char *[]){ "gsbi11_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct clk_rcg gsbi12_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .ns_reg = 0x2b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .md_reg = 0x2b30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .enable_reg = 0x2b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .name = "gsbi12_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static struct clk_branch gsbi12_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .enable_reg = 0x2b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .name = "gsbi12_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .parent_names = (const char *[]){ "gsbi12_uart_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static struct freq_tbl clk_tbl_gsbi_qup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { 1100000, P_PXO, 1, 2, 49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { 5400000, P_PXO, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { 10800000, P_PXO, 1, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { 15060000, P_PLL8, 1, 2, 51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { 25600000, P_PLL8, 1, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct clk_rcg gsbi1_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .ns_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .md_reg = 0x29c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .name = "gsbi1_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static struct clk_branch gsbi1_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .name = "gsbi1_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .parent_names = (const char *[]){ "gsbi1_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static struct clk_rcg gsbi2_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .ns_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .md_reg = 0x29e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .name = "gsbi2_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static struct clk_branch gsbi2_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .name = "gsbi2_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .parent_names = (const char *[]){ "gsbi2_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static struct clk_rcg gsbi3_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .ns_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .md_reg = 0x2a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .enable_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .name = "gsbi3_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static struct clk_branch gsbi3_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .enable_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .name = "gsbi3_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .parent_names = (const char *[]){ "gsbi3_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static struct clk_rcg gsbi4_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .ns_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .md_reg = 0x2a28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .name = "gsbi4_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static struct clk_branch gsbi4_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "gsbi4_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .parent_names = (const char *[]){ "gsbi4_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static struct clk_rcg gsbi5_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .ns_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .md_reg = 0x2a48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .name = "gsbi5_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static struct clk_branch gsbi5_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .name = "gsbi5_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .parent_names = (const char *[]){ "gsbi5_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static struct clk_rcg gsbi6_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .ns_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .md_reg = 0x2a68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .enable_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .name = "gsbi6_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static struct clk_branch gsbi6_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .enable_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .name = "gsbi6_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .parent_names = (const char *[]){ "gsbi6_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static struct clk_rcg gsbi7_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .ns_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .md_reg = 0x2a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .enable_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .name = "gsbi7_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static struct clk_branch gsbi7_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .enable_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .name = "gsbi7_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .parent_names = (const char *[]){ "gsbi7_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static struct clk_rcg gsbi8_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .ns_reg = 0x2aac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .md_reg = 0x2aa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .enable_reg = 0x2aac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .name = "gsbi8_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static struct clk_branch gsbi8_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .enable_reg = 0x2aac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .name = "gsbi8_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .parent_names = (const char *[]){ "gsbi8_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static struct clk_rcg gsbi9_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .ns_reg = 0x2acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .md_reg = 0x2ac8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .enable_reg = 0x2acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .name = "gsbi9_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static struct clk_branch gsbi9_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .enable_reg = 0x2acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .name = "gsbi9_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .parent_names = (const char *[]){ "gsbi9_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static struct clk_rcg gsbi10_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .ns_reg = 0x2aec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .md_reg = 0x2ae8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .enable_reg = 0x2aec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .name = "gsbi10_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static struct clk_branch gsbi10_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .enable_reg = 0x2aec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .name = "gsbi10_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .parent_names = (const char *[]){ "gsbi10_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static struct clk_rcg gsbi11_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .ns_reg = 0x2b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .md_reg = 0x2b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .enable_reg = 0x2b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .name = "gsbi11_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static struct clk_branch gsbi11_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .enable_reg = 0x2b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .name = "gsbi11_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .parent_names = (const char *[]){ "gsbi11_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static struct clk_rcg gsbi12_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .ns_reg = 0x2b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .md_reg = 0x2b28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .enable_reg = 0x2b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .name = "gsbi12_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static struct clk_branch gsbi12_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .enable_reg = 0x2b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .name = "gsbi12_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .parent_names = (const char *[]){ "gsbi12_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const struct freq_tbl clk_tbl_gp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { 9600000, P_CXO, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { 13500000, P_PXO, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { 19200000, P_CXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { 27000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { 76800000, P_PLL8, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { 96000000, P_PLL8, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) { 128000000, P_PLL8, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) { 192000000, P_PLL8, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static struct clk_rcg gp0_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .ns_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .md_reg = 0x2d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .name = "gp0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static struct clk_branch gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .name = "gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .parent_names = (const char *[]){ "gp0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static struct clk_rcg gp1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .ns_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .md_reg = 0x2d40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .name = "gp1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static struct clk_branch gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .name = "gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .parent_names = (const char *[]){ "gp1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static struct clk_rcg gp2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .ns_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .md_reg = 0x2d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .name = "gp2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static struct clk_branch gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .name = "gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .parent_names = (const char *[]){ "gp2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static struct clk_branch pmem_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .hwcg_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .enable_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .name = "pmem_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static struct clk_rcg prng_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .ns_reg = 0x2e80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .clkr.hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .name = "prng_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static struct clk_branch prng_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .name = "prng_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .parent_names = (const char *[]){ "prng_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const struct freq_tbl clk_tbl_sdc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { 144000, P_PXO, 3, 2, 125 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) { 400000, P_PLL8, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) { 17070000, P_PLL8, 1, 2, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) { 20210000, P_PLL8, 1, 1, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static struct clk_rcg sdc1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .ns_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .md_reg = 0x2828,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .name = "sdc1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static struct clk_branch sdc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .name = "sdc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .parent_names = (const char *[]){ "sdc1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static struct clk_rcg sdc2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .ns_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .md_reg = 0x2848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .enable_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .name = "sdc2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static struct clk_branch sdc2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .enable_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .name = "sdc2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .parent_names = (const char *[]){ "sdc2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static struct clk_rcg sdc3_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .ns_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .md_reg = 0x2868,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .enable_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .name = "sdc3_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static struct clk_branch sdc3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .enable_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .name = "sdc3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .parent_names = (const char *[]){ "sdc3_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static struct clk_rcg sdc4_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .ns_reg = 0x288c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .md_reg = 0x2888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .enable_reg = 0x288c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .name = "sdc4_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static struct clk_branch sdc4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .enable_reg = 0x288c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .name = "sdc4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .parent_names = (const char *[]){ "sdc4_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static struct clk_rcg sdc5_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .ns_reg = 0x28ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .md_reg = 0x28a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .enable_reg = 0x28ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .name = "sdc5_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static struct clk_branch sdc5_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .enable_reg = 0x28ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .name = "sdc5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .parent_names = (const char *[]){ "sdc5_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static const struct freq_tbl clk_tbl_tsif_ref[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) { 105000, P_PXO, 1, 1, 256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static struct clk_rcg tsif_ref_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .ns_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .md_reg = 0x270c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .freq_tbl = clk_tbl_tsif_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .enable_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .name = "tsif_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static struct clk_branch tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .enable_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .name = "tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .parent_names = (const char *[]){ "tsif_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static const struct freq_tbl clk_tbl_usb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) { 60000000, P_PLL8, 1, 5, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static struct clk_rcg usb_hs1_xcvr_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .ns_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .md_reg = 0x2908,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .enable_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .name = "usb_hs1_xcvr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static struct clk_branch usb_hs1_xcvr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .enable_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .name = "usb_hs1_xcvr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static struct clk_rcg usb_fs1_xcvr_fs_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .ns_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .md_reg = 0x2964,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .enable_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .name = "usb_fs1_xcvr_fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static struct clk_branch usb_fs1_xcvr_fs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .enable_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .name = "usb_fs1_xcvr_fs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .parent_names = usb_fs1_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static struct clk_branch usb_fs1_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .enable_reg = 0x296c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .parent_names = usb_fs1_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .name = "usb_fs1_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static struct clk_rcg usb_fs2_xcvr_fs_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .ns_reg = 0x2988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .md_reg = 0x2984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .enable_reg = 0x2988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .name = "usb_fs2_xcvr_fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static struct clk_branch usb_fs2_xcvr_fs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .enable_reg = 0x2988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .name = "usb_fs2_xcvr_fs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .parent_names = usb_fs2_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static struct clk_branch usb_fs2_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .enable_reg = 0x298c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .name = "usb_fs2_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .parent_names = usb_fs2_xcvr_fs_src_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static struct clk_branch gsbi1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .enable_reg = 0x29c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .name = "gsbi1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static struct clk_branch gsbi2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .enable_reg = 0x29e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .name = "gsbi2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static struct clk_branch gsbi3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .enable_reg = 0x2a00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .name = "gsbi3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static struct clk_branch gsbi4_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .enable_reg = 0x2a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .name = "gsbi4_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static struct clk_branch gsbi5_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .enable_reg = 0x2a40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .name = "gsbi5_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static struct clk_branch gsbi6_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .enable_reg = 0x2a60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .name = "gsbi6_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static struct clk_branch gsbi7_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .enable_reg = 0x2a80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .name = "gsbi7_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static struct clk_branch gsbi8_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .enable_reg = 0x2aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .name = "gsbi8_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static struct clk_branch gsbi9_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .enable_reg = 0x2ac0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .name = "gsbi9_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static struct clk_branch gsbi10_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .enable_reg = 0x2ae0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .name = "gsbi10_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static struct clk_branch gsbi11_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .enable_reg = 0x2b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .name = "gsbi11_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) static struct clk_branch gsbi12_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .enable_reg = 0x2b20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .name = "gsbi12_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static struct clk_branch tsif_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .enable_reg = 0x2700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .name = "tsif_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static struct clk_branch usb_fs1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .enable_reg = 0x2960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .name = "usb_fs1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static struct clk_branch usb_fs2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .enable_reg = 0x2980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .name = "usb_fs2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static struct clk_branch usb_hs1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .enable_reg = 0x2900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .name = "usb_hs1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static struct clk_branch sdc1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .enable_reg = 0x2820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .name = "sdc1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static struct clk_branch sdc2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .enable_reg = 0x2840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .name = "sdc2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) static struct clk_branch sdc3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .enable_reg = 0x2860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .name = "sdc3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static struct clk_branch sdc4_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .enable_reg = 0x2880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .name = "sdc4_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static struct clk_branch sdc5_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .enable_reg = 0x28a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .name = "sdc5_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static struct clk_branch ebi2_2x_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .enable_reg = 0x2660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .name = "ebi2_2x_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static struct clk_branch ebi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .enable_reg = 0x2664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .name = "ebi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static struct clk_branch adm0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .name = "adm0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) static struct clk_branch adm0_pbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .name = "adm0_pbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) static struct clk_branch adm1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .name = "adm1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) static struct clk_branch adm1_pbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .name = "adm1_pbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static struct clk_branch modem_ahb1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .name = "modem_ahb1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static struct clk_branch modem_ahb2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .name = "modem_ahb2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static struct clk_branch pmic_arb0_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .name = "pmic_arb0_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static struct clk_branch pmic_arb1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .name = "pmic_arb1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) static struct clk_branch pmic_ssbi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .name = "pmic_ssbi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) static struct clk_branch rpm_msg_ram_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .hwcg_reg = 0x27e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .name = "rpm_msg_ram_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static struct clk_regmap *gcc_msm8660_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) [PLL8] = &pll8.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) [PLL8_VOTE] = &pll8_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) [GP0_SRC] = &gp0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) [GP0_CLK] = &gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) [GP1_SRC] = &gp1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) [GP1_CLK] = &gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) [GP2_SRC] = &gp2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) [GP2_CLK] = &gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) [PMEM_CLK] = &pmem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) [PRNG_SRC] = &prng_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) [PRNG_CLK] = &prng_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) [SDC1_SRC] = &sdc1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) [SDC1_CLK] = &sdc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) [SDC2_SRC] = &sdc2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) [SDC2_CLK] = &sdc2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) [SDC3_SRC] = &sdc3_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) [SDC3_CLK] = &sdc3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) [SDC4_SRC] = &sdc4_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) [SDC4_CLK] = &sdc4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) [SDC5_SRC] = &sdc5_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) [SDC5_CLK] = &sdc5_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) [TSIF_REF_SRC] = &tsif_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) [TSIF_H_CLK] = &tsif_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) [SDC1_H_CLK] = &sdc1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) [SDC2_H_CLK] = &sdc2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) [SDC3_H_CLK] = &sdc3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) [SDC4_H_CLK] = &sdc4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) [SDC5_H_CLK] = &sdc5_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) [EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) [EBI2_CLK] = &ebi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) [ADM0_CLK] = &adm0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) [ADM1_CLK] = &adm1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static const struct qcom_reset_map gcc_msm8660_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) [AFAB_CORE_RESET] = { 0x2080, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) [SCSS_SYS_RESET] = { 0x20b4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) [SCSS_SYS_POR_RESET] = { 0x20b4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) [AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) [SFAB_CORE_RESET] = { 0x2120, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) [ADM0_C2_RESET] = { 0x220c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) [ADM0_C1_RESET] = { 0x220c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) [ADM0_C0_RESET] = { 0x220c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) [ADM0_PBUS_RESET] = { 0x220c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) [ADM0_RESET] = { 0x220c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) [SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) [SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) [SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) [ADM1_C3_RESET] = { 0x226c, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) [ADM1_C2_RESET] = { 0x226c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) [ADM1_C1_RESET] = { 0x226c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) [ADM1_C0_RESET] = { 0x226c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) [ADM1_PBUS_RESET] = { 0x226c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) [ADM1_RESET] = { 0x226c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) [IMEM0_RESET] = { 0x2280, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) [DFAB_CORE_RESET] = { 0x24ac, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) [DFAB_SWAY0_RESET] = { 0x2540, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) [DFAB_SWAY1_RESET] = { 0x2544, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) [DFAB_ARB0_RESET] = { 0x2560, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) [DFAB_ARB1_RESET] = { 0x2564, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) [PPSS_PROC_RESET] = { 0x2594, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) [PPSS_RESET] = { 0x2594 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) [PMEM_RESET] = { 0x25a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) [DMA_BAM_RESET] = { 0x25c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) [SIC_RESET] = { 0x25e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) [SPS_TIC_RESET] = { 0x2600, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) [CFBP0_RESET] = { 0x2650, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) [CFBP1_RESET] = { 0x2654, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) [CFBP2_RESET] = { 0x2658, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) [EBI2_RESET] = { 0x2664, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) [CFPB_MASTER_RESET] = { 0x26a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) [CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) [TSIF_RESET] = { 0x2700, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) [CE1_RESET] = { 0x2720, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) [CE2_RESET] = { 0x2740, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) [RPM_PROC_RESET] = { 0x27c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) [RPM_BUS_RESET] = { 0x27c4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) [RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) [PMIC_ARB0_RESET] = { 0x2800, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) [PMIC_ARB1_RESET] = { 0x2804, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) [PMIC_SSBI2_RESET] = { 0x280c, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) [SDC1_RESET] = { 0x2830 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) [SDC2_RESET] = { 0x2850 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) [SDC3_RESET] = { 0x2870 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) [SDC4_RESET] = { 0x2890 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) [SDC5_RESET] = { 0x28b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) [USB_HS1_RESET] = { 0x2910 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) [USB_HS2_XCVR_RESET] = { 0x2934, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) [USB_HS2_RESET] = { 0x2934 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) [USB_FS1_RESET] = { 0x2974 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) [USB_FS2_RESET] = { 0x2994 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) [GSBI1_RESET] = { 0x29dc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) [GSBI2_RESET] = { 0x29fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) [GSBI3_RESET] = { 0x2a1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) [GSBI4_RESET] = { 0x2a3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) [GSBI5_RESET] = { 0x2a5c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) [GSBI6_RESET] = { 0x2a7c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) [GSBI7_RESET] = { 0x2a9c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) [GSBI8_RESET] = { 0x2abc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) [GSBI9_RESET] = { 0x2adc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) [GSBI10_RESET] = { 0x2afc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) [GSBI11_RESET] = { 0x2b1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) [GSBI12_RESET] = { 0x2b3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) [SPDM_RESET] = { 0x2b6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) [SEC_CTRL_RESET] = { 0x2b80, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) [TLMM_H_RESET] = { 0x2ba0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) [TLMM_RESET] = { 0x2ba4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) [MARRM_PWRON_RESET] = { 0x2bd4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) [MARM_RESET] = { 0x2bd4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) [MAHB1_RESET] = { 0x2be4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) [MAHB2_RESET] = { 0x2c20, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) [MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) [MODEM_RESET] = { 0x2c48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) [SFAB_MSS_MDM0_RESET] = { 0x2c4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) [MSS_SLP_RESET] = { 0x2c60, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) [MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) [MSS_WDOG_RESET] = { 0x2c68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) [TSSC_RESET] = { 0x2ca0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) [PDM_RESET] = { 0x2cc0, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) [SCSS_CORE0_RESET] = { 0x2d60, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) [SCSS_CORE0_POR_RESET] = { 0x2d60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) [SCSS_CORE1_RESET] = { 0x2d80, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) [SCSS_CORE1_POR_RESET] = { 0x2d80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) [MPM_RESET] = { 0x2da4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) [EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) [EBI1_RESET] = { 0x2dec, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) [USB_PHY0_RESET] = { 0x2e20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) [USB_PHY1_RESET] = { 0x2e40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) [PRNG_RESET] = { 0x2e80, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static const struct regmap_config gcc_msm8660_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .max_register = 0x363c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static const struct qcom_cc_desc gcc_msm8660_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .config = &gcc_msm8660_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .clks = gcc_msm8660_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .num_clks = ARRAY_SIZE(gcc_msm8660_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .resets = gcc_msm8660_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .num_resets = ARRAY_SIZE(gcc_msm8660_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static const struct of_device_id gcc_msm8660_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) { .compatible = "qcom,gcc-msm8660" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static int gcc_msm8660_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) return qcom_cc_probe(pdev, &gcc_msm8660_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) static struct platform_driver gcc_msm8660_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .probe = gcc_msm8660_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .name = "gcc-msm8660",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .of_match_table = gcc_msm8660_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) static int __init gcc_msm8660_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return platform_driver_register(&gcc_msm8660_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) core_initcall(gcc_msm8660_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) static void __exit gcc_msm8660_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) platform_driver_unregister(&gcc_msm8660_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) module_exit(gcc_msm8660_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) MODULE_DESCRIPTION("GCC MSM 8660 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) MODULE_ALIAS("platform:gcc-msm8660");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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