^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author : Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct clk_fixed_factor cxo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .name = "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .parent_names = (const char *[]){ "cxo_board" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct clk_pll pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .l_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .m_reg = 0x30c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .n_reg = 0x30cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .config_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .mode_reg = 0x30c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .status_reg = 0x30d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct clk_regmap pll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "pll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .parent_names = (const char *[]){ "pll8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct clk_regmap pll4_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .name = "pll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .parent_names = (const char *[]){ "pll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clk_pll pll8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .l_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .m_reg = 0x3148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .n_reg = 0x314c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .config_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mode_reg = 0x3140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .status_reg = 0x3158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "pll8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct clk_regmap pll8_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .parent_names = (const char *[]){ "pll8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clk_pll pll14 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .l_reg = 0x31c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .m_reg = 0x31c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .n_reg = 0x31cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .config_reg = 0x31d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .mode_reg = 0x31c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .status_reg = 0x31d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "pll14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct clk_regmap pll14_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "pll14_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .parent_names = (const char *[]){ "pll14" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) P_CXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) P_PLL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) P_PLL14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct parent_map gcc_cxo_pll8_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { P_CXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { P_PLL8, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char * const gcc_cxo_pll8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct parent_map gcc_cxo_pll14_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { P_CXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { P_PLL14, 4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const gcc_cxo_pll14[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "pll14_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct parent_map gcc_cxo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { P_CXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char * const gcc_cxo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct freq_tbl clk_tbl_gsbi_uart[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 1843200, P_PLL8, 2, 6, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 3686400, P_PLL8, 2, 12, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 7372800, P_PLL8, 2, 24, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 14745600, P_PLL8, 2, 48, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 32000000, P_PLL8, 4, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 40000000, P_PLL8, 1, 5, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 46400000, P_PLL8, 1, 29, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 56000000, P_PLL8, 1, 7, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 58982400, P_PLL8, 1, 96, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clk_rcg gsbi1_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .ns_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .md_reg = 0x29d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct clk_branch gsbi1_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "gsbi1_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct clk_rcg gsbi2_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .ns_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .md_reg = 0x29f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct clk_branch gsbi2_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "gsbi2_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct clk_rcg gsbi3_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .ns_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .md_reg = 0x2a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .enable_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "gsbi3_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct clk_branch gsbi3_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .halt_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .enable_reg = 0x2a14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .name = "gsbi3_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "gsbi3_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct clk_rcg gsbi4_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .ns_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .md_reg = 0x2a30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct clk_branch gsbi4_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .name = "gsbi4_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct clk_rcg gsbi5_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .ns_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .md_reg = 0x2a50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct clk_branch gsbi5_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "gsbi5_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct freq_tbl clk_tbl_gsbi_qup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { 960000, P_CXO, 4, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { 4800000, P_CXO, 4, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { 9600000, P_CXO, 2, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { 15060000, P_PLL8, 1, 2, 51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 25600000, P_PLL8, 1, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct clk_rcg gsbi1_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .ns_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .md_reg = 0x29c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .name = "gsbi1_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct clk_branch gsbi1_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .name = "gsbi1_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .parent_names = (const char *[]){ "gsbi1_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct clk_rcg gsbi2_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .ns_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .md_reg = 0x29e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .name = "gsbi2_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct clk_branch gsbi2_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .name = "gsbi2_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .parent_names = (const char *[]){ "gsbi2_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static struct clk_rcg gsbi3_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .ns_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .md_reg = 0x2a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .enable_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .name = "gsbi3_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static struct clk_branch gsbi3_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .enable_reg = 0x2a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .name = "gsbi3_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .parent_names = (const char *[]){ "gsbi3_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct clk_rcg gsbi4_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .ns_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .md_reg = 0x2a28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .name = "gsbi4_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static struct clk_branch gsbi4_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "gsbi4_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .parent_names = (const char *[]){ "gsbi4_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static struct clk_rcg gsbi5_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .ns_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .md_reg = 0x2a48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .name = "gsbi5_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct clk_branch gsbi5_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .name = "gsbi5_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .parent_names = (const char *[]){ "gsbi5_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const struct freq_tbl clk_tbl_gp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { 9600000, P_CXO, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { 19200000, P_CXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static struct clk_rcg gp0_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .ns_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .md_reg = 0x2d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .parent_map = gcc_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .name = "gp0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .parent_names = gcc_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static struct clk_branch gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .parent_names = (const char *[]){ "gp0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct clk_rcg gp1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .ns_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .md_reg = 0x2d40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .parent_map = gcc_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .name = "gp1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .parent_names = gcc_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static struct clk_branch gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .name = "gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .parent_names = (const char *[]){ "gp1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static struct clk_rcg gp2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .ns_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .md_reg = 0x2d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .parent_map = gcc_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .name = "gp2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .parent_names = gcc_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static struct clk_branch gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .name = "gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .parent_names = (const char *[]){ "gp2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static struct clk_branch pmem_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .hwcg_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .enable_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .name = "pmem_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static struct clk_rcg prng_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ns_reg = 0x2e80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .name = "prng_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct clk_branch prng_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .name = "prng_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .parent_names = (const char *[]){ "prng_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const struct freq_tbl clk_tbl_sdc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { 144000, P_CXO, 1, 1, 133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { 400000, P_PLL8, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) { 17070000, P_PLL8, 1, 2, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) { 20210000, P_PLL8, 1, 1, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) { 38400000, P_PLL8, 2, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { 64000000, P_PLL8, 3, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) { 76800000, P_PLL8, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static struct clk_rcg sdc1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .ns_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .md_reg = 0x2828,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .name = "sdc1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static struct clk_branch sdc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .name = "sdc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .parent_names = (const char *[]){ "sdc1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static struct clk_rcg sdc2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .ns_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .md_reg = 0x2848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .enable_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .name = "sdc2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static struct clk_branch sdc2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .enable_reg = 0x284c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .name = "sdc2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .parent_names = (const char *[]){ "sdc2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const struct freq_tbl clk_tbl_usb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { 60000000, P_PLL8, 1, 5, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static struct clk_rcg usb_hs1_xcvr_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .ns_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .md_reg = 0x2908,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .enable_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .name = "usb_hs1_xcvr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static struct clk_branch usb_hs1_xcvr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .enable_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .name = "usb_hs1_xcvr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static struct clk_rcg usb_hsic_xcvr_fs_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .ns_reg = 0x2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .md_reg = 0x2924,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .enable_reg = 0x2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .name = "usb_hsic_xcvr_fs_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static struct clk_branch usb_hsic_xcvr_fs_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .enable_reg = 0x2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .name = "usb_hsic_xcvr_fs_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .parent_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) (const char *[]){ "usb_hsic_xcvr_fs_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const struct freq_tbl clk_tbl_usb_hs1_system[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) { 60000000, P_PLL8, 1, 5, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static struct clk_rcg usb_hs1_system_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .ns_reg = 0x36a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .md_reg = 0x36a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .freq_tbl = clk_tbl_usb_hs1_system,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .enable_reg = 0x36a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .name = "usb_hs1_system_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static struct clk_branch usb_hs1_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .enable_reg = 0x36a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .parent_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) (const char *[]){ "usb_hs1_system_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .name = "usb_hs1_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static const struct freq_tbl clk_tbl_usb_hsic_system[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) { 64000000, P_PLL8, 1, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static struct clk_rcg usb_hsic_system_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .ns_reg = 0x2b58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .md_reg = 0x2b54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .parent_map = gcc_cxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .freq_tbl = clk_tbl_usb_hsic_system,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .enable_reg = 0x2b58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .name = "usb_hsic_system_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .parent_names = gcc_cxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static struct clk_branch usb_hsic_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .enable_reg = 0x2b58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .parent_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) (const char *[]){ "usb_hsic_system_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .name = "usb_hsic_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static const struct freq_tbl clk_tbl_usb_hsic_hsic[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { 48000000, P_PLL14, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static struct clk_rcg usb_hsic_hsic_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .ns_reg = 0x2b50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .md_reg = 0x2b4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .parent_map = gcc_cxo_pll14_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .freq_tbl = clk_tbl_usb_hsic_hsic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .enable_reg = 0x2b50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .name = "usb_hsic_hsic_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .parent_names = gcc_cxo_pll14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static struct clk_branch usb_hsic_hsic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .enable_reg = 0x2b50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .name = "usb_hsic_hsic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static struct clk_branch usb_hsic_hsio_cal_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .enable_reg = 0x2b48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .parent_names = (const char *[]){ "cxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .name = "usb_hsic_hsio_cal_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static struct clk_branch ce1_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .hwcg_reg = 0x2724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .enable_reg = 0x2724,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .name = "ce1_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static struct clk_branch ce1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .enable_reg = 0x2720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .name = "ce1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static struct clk_branch dma_bam_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .hwcg_reg = 0x25c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .enable_reg = 0x25c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .name = "dma_bam_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static struct clk_branch gsbi1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .hwcg_reg = 0x29c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .enable_reg = 0x29c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .name = "gsbi1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static struct clk_branch gsbi2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .hwcg_reg = 0x29e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .enable_reg = 0x29e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .name = "gsbi2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static struct clk_branch gsbi3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .hwcg_reg = 0x2a00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .halt_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enable_reg = 0x2a00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .name = "gsbi3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static struct clk_branch gsbi4_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .hwcg_reg = 0x2a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .enable_reg = 0x2a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .name = "gsbi4_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static struct clk_branch gsbi5_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .hwcg_reg = 0x2a40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .enable_reg = 0x2a40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .name = "gsbi5_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static struct clk_branch usb_hs1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .hwcg_reg = 0x2900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .enable_reg = 0x2900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .name = "usb_hs1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static struct clk_branch usb_hsic_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .halt_bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .enable_reg = 0x2920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .name = "usb_hsic_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static struct clk_branch sdc1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .hwcg_reg = 0x2820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .enable_reg = 0x2820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .name = "sdc1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static struct clk_branch sdc2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .hwcg_reg = 0x2840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .enable_reg = 0x2840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .name = "sdc2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static struct clk_branch adm0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .name = "adm0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static struct clk_branch adm0_pbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .hwcg_reg = 0x2208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .name = "adm0_pbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static struct clk_branch pmic_arb0_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .name = "pmic_arb0_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static struct clk_branch pmic_arb1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .name = "pmic_arb1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct clk_branch pmic_ssbi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .name = "pmic_ssbi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static struct clk_branch rpm_msg_ram_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .hwcg_reg = 0x27e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .name = "rpm_msg_ram_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static struct clk_branch ebi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .hwcg_reg = 0x2664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .enable_reg = 0x2664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .enable_mask = BIT(6) | BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .name = "ebi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static struct clk_branch ebi2_aon_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .enable_reg = 0x2664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .name = "ebi2_aon_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static struct clk_hw *gcc_mdm9615_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) &cxo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static struct clk_regmap *gcc_mdm9615_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) [PLL0] = &pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) [PLL0_VOTE] = &pll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) [PLL4_VOTE] = &pll4_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) [PLL8] = &pll8.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) [PLL8_VOTE] = &pll8_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) [PLL14] = &pll14.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) [PLL14_VOTE] = &pll14_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) [GP0_SRC] = &gp0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) [GP0_CLK] = &gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) [GP1_SRC] = &gp1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) [GP1_CLK] = &gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) [GP2_SRC] = &gp2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) [GP2_CLK] = &gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) [PMEM_A_CLK] = &pmem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) [PRNG_SRC] = &prng_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) [PRNG_CLK] = &prng_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) [SDC1_SRC] = &sdc1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) [SDC1_CLK] = &sdc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) [SDC2_SRC] = &sdc2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) [SDC2_CLK] = &sdc2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) [USB_HS1_SYSTEM_CLK_SRC] = &usb_hs1_system_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) [USB_HS1_SYSTEM_CLK] = &usb_hs1_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) [USB_HSIC_HSIC_CLK_SRC] = &usb_hsic_hsic_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) [CE1_CORE_CLK] = &ce1_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) [CE1_H_CLK] = &ce1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) [SDC1_H_CLK] = &sdc1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) [SDC2_H_CLK] = &sdc2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) [ADM0_CLK] = &adm0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) [EBI2_CLK] = &ebi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static const struct qcom_reset_map gcc_mdm9615_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) [DMA_BAM_RESET] = { 0x25c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) [CE1_H_RESET] = { 0x2720, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) [CE1_CORE_RESET] = { 0x2724, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) [SDC1_RESET] = { 0x2830 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) [SDC2_RESET] = { 0x2850 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) [ADM0_C2_RESET] = { 0x220c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) [ADM0_C1_RESET] = { 0x220c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) [ADM0_C0_RESET] = { 0x220c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) [ADM0_PBUS_RESET] = { 0x220c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) [ADM0_RESET] = { 0x220c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) [USB_HS1_RESET] = { 0x2910 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) [USB_HSIC_RESET] = { 0x2934 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) [GSBI1_RESET] = { 0x29dc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) [GSBI2_RESET] = { 0x29fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) [GSBI3_RESET] = { 0x2a1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) [GSBI4_RESET] = { 0x2a3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) [GSBI5_RESET] = { 0x2a5c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) [PDM_RESET] = { 0x2CC0, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static const struct regmap_config gcc_mdm9615_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .max_register = 0x3660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static const struct qcom_cc_desc gcc_mdm9615_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .config = &gcc_mdm9615_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .clks = gcc_mdm9615_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .resets = gcc_mdm9615_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .clk_hws = gcc_mdm9615_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static const struct of_device_id gcc_mdm9615_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) { .compatible = "qcom,gcc-mdm9615" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static int gcc_mdm9615_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static struct platform_driver gcc_mdm9615_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .probe = gcc_mdm9615_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .name = "gcc-mdm9615",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .of_match_table = gcc_mdm9615_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) static int __init gcc_mdm9615_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return platform_driver_register(&gcc_mdm9615_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) core_initcall(gcc_mdm9615_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static void __exit gcc_mdm9615_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) platform_driver_unregister(&gcc_mdm9615_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) module_exit(gcc_mdm9615_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) MODULE_DESCRIPTION("QCOM GCC MDM9615 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) MODULE_ALIAS("platform:gcc-mdm9615");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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