^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-regmap-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_GPLL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_PCIE20_PHY0_PIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_PCIE20_PHY1_PIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_USB3PHY_0_PIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_USB3PHY_1_PIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_UBI32_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_NSS_CRYPTO_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_BIAS_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_BIAS_PLL_NSS_NOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) P_UNIPHY0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) P_UNIPHY0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) P_UNIPHY1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) P_UNIPHY1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) P_UNIPHY2_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) P_UNIPHY2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct parent_map gcc_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { P_GPLL2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const gcc_xo_gpll0_sleep_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { P_SLEEP_CLK, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { P_GPLL6, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { P_GPLL0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { P_GPLL0_DIV2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "usb3phy_0_cc_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { P_USB3PHY_0_PIPE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { P_XO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "usb3phy_1_cc_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { P_USB3PHY_1_PIPE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { P_XO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "pcie20_phy0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { P_PCIE20_PHY0_PIPE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { P_XO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "pcie20_phy1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { P_PCIE20_PHY1_PIPE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { P_XO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { P_GPLL0_DIV2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "bias_pll_nss_noc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { P_BIAS_PLL_NSS_NOC, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { P_GPLL2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "nss_crypto_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { P_NSS_CRYPTO_PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { P_UBI32_PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { P_GPLL2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { P_GPLL4, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { P_GPLL6, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const gcc_xo_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { P_GPLL0_DIV2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "bias_pll_cc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "nss_crypto_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { P_BIAS_PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { P_GPLL4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { P_NSS_CRYPTO_PLL, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char * const gcc_xo_gpll0_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { P_GPLL4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "uniphy0_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "uniphy0_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "bias_pll_cc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { P_UNIPHY0_RX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { P_UNIPHY0_TX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "uniphy0_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "uniphy0_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "bias_pll_cc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { P_UNIPHY0_TX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { P_UNIPHY0_RX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "uniphy0_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "uniphy0_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "uniphy1_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "uniphy1_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "bias_pll_cc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct parent_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { P_UNIPHY0_RX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { P_UNIPHY0_TX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { P_UNIPHY1_RX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { P_UNIPHY1_TX, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "uniphy0_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "uniphy0_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "uniphy1_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "uniphy1_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "bias_pll_cc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct parent_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { P_UNIPHY0_TX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { P_UNIPHY0_RX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { P_UNIPHY1_TX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { P_UNIPHY1_RX, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "uniphy2_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "uniphy2_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "bias_pll_cc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { P_UNIPHY2_RX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { P_UNIPHY2_TX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "uniphy2_gcc_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "uniphy2_gcc_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "bias_pll_cc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { P_UNIPHY2_TX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { P_UNIPHY2_RX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { P_SLEEP_CLK, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct clk_alpha_pll gpll0_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .offset = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "gpll0_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk_fixed_factor gpll0_out_main_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .name = "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "gpll0_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct clk_alpha_pll_postdiv gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .offset = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "gpll0_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct clk_alpha_pll gpll2_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .offset = 0x4a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "gpll2_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct clk_alpha_pll_postdiv gpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .offset = 0x4a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .name = "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "gpll2_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct clk_alpha_pll gpll4_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .offset = 0x24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "gpll4_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static struct clk_alpha_pll_postdiv gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .offset = 0x24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "gpll4_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static struct clk_alpha_pll gpll6_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .offset = 0x37000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .flags = SUPPORTS_DYNAMIC_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .name = "gpll6_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct clk_alpha_pll_postdiv gpll6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .offset = 0x37000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .name = "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "gpll6_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct clk_fixed_factor gpll6_out_main_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .name = "gpll6_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "gpll6_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct clk_alpha_pll ubi32_pll_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .offset = 0x25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .flags = SUPPORTS_DYNAMIC_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .name = "ubi32_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .ops = &clk_alpha_pll_huayra_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct clk_alpha_pll_postdiv ubi32_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .offset = 0x25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "ubi32_pll_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static struct clk_alpha_pll nss_crypto_pll_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .offset = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "nss_crypto_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static struct clk_alpha_pll_postdiv nss_crypto_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .offset = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "nss_crypto_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "nss_crypto_pll_main"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .cmd_rcgr = 0x27000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static struct clk_fixed_factor pcnoc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .name = "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "pcnoc_bfdcd_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct clk_branch gcc_sleep_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .halt_reg = 0x30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .enable_reg = 0x30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = "gcc_sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "sleep_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) F(25000000, P_GPLL0_DIV2, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .cmd_rcgr = 0x0200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) F(12500000, P_GPLL0_DIV2, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) F(16000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .cmd_rcgr = 0x02024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .cmd_rcgr = 0x03000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .cmd_rcgr = 0x03014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .cmd_rcgr = 0x04000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .cmd_rcgr = 0x04014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .cmd_rcgr = 0x05000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .cmd_rcgr = 0x05014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .cmd_rcgr = 0x06000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .cmd_rcgr = 0x06014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .cmd_rcgr = 0x07000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .cmd_rcgr = 0x07014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) F(16000000, P_GPLL0_DIV2, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) F(24000000, P_GPLL0, 1, 3, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) F(32000000, P_GPLL0, 1, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) F(40000000, P_GPLL0, 1, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) F(46400000, P_GPLL0, 1, 29, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) F(48000000, P_GPLL0, 1, 3, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) F(51200000, P_GPLL0, 1, 8, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) F(56000000, P_GPLL0, 1, 7, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) F(58982400, P_GPLL0, 1, 1152, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) F(60000000, P_GPLL0, 1, 3, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) F(64000000, P_GPLL0, 12.5, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .cmd_rcgr = 0x02044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .cmd_rcgr = 0x03034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .cmd_rcgr = 0x04034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .name = "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .cmd_rcgr = 0x05034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .name = "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .cmd_rcgr = 0x06034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .name = "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .cmd_rcgr = 0x07034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .name = "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const struct clk_parent_data gcc_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static struct clk_rcg2 pcie0_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .cmd_rcgr = 0x75054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .freq_tbl = ftbl_pcie_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = "pcie0_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static struct clk_rcg2 pcie0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .cmd_rcgr = 0x75024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .freq_tbl = ftbl_pcie_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .parent_map = gcc_xo_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .name = "pcie0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .parent_names = gcc_xo_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static struct clk_regmap_mux pcie0_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .reg = 0x7501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .name = "pcie0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static struct clk_rcg2 pcie1_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .cmd_rcgr = 0x76054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .freq_tbl = ftbl_pcie_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .name = "pcie1_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static struct clk_rcg2 pcie1_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .cmd_rcgr = 0x76024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .freq_tbl = ftbl_pcie_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .parent_map = gcc_xo_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .name = "pcie1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .parent_names = gcc_xo_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static struct clk_regmap_mux pcie1_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .reg = 0x7601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .name = "pcie1_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) F(24000000, P_GPLL2, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) F(48000000, P_GPLL2, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) F(96000000, P_GPLL2, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) F(177777778, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) F(192000000, P_GPLL2, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) F(384000000, P_GPLL2, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .cmd_rcgr = 0x42004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .freq_tbl = ftbl_sdcc_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) F(308570000, P_GPLL6, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static struct clk_rcg2 sdcc1_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .cmd_rcgr = 0x5d000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .freq_tbl = ftbl_sdcc_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .name = "sdcc1_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .cmd_rcgr = 0x43004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .freq_tbl = ftbl_sdcc_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const struct freq_tbl ftbl_usb_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) F(80000000, P_GPLL0_DIV2, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) F(133330000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static struct clk_rcg2 usb0_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .cmd_rcgr = 0x3e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .freq_tbl = ftbl_usb_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .name = "usb0_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static struct clk_rcg2 usb0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .cmd_rcgr = 0x3e05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .freq_tbl = ftbl_usb_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .parent_map = gcc_xo_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .name = "usb0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .parent_names = gcc_xo_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) F(20000000, P_GPLL6, 6, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) F(60000000, P_GPLL6, 6, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static struct clk_rcg2 usb0_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .cmd_rcgr = 0x3e020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .freq_tbl = ftbl_usb_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .name = "usb0_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static struct clk_regmap_mux usb0_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .reg = 0x3e048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .name = "usb0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static struct clk_rcg2 usb1_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .cmd_rcgr = 0x3f00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .freq_tbl = ftbl_usb_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .name = "usb1_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static struct clk_rcg2 usb1_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .cmd_rcgr = 0x3f05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .freq_tbl = ftbl_usb_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .parent_map = gcc_xo_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .name = "usb1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .parent_names = gcc_xo_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static struct clk_rcg2 usb1_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .cmd_rcgr = 0x3f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .freq_tbl = ftbl_usb_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .name = "usb1_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static struct clk_regmap_mux usb1_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .reg = 0x3f048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .name = "usb1_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static struct clk_branch gcc_xo_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .halt_reg = 0x30018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .enable_reg = 0x30018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .name = "gcc_xo_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static struct clk_fixed_factor gcc_xo_div4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .name = "gcc_xo_div4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) "gcc_xo_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) F(50000000, P_GPLL0_DIV2, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) F(133333333, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) F(266666667, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static struct clk_rcg2 system_noc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .cmd_rcgr = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .name = "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static struct clk_fixed_factor system_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .name = "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "system_noc_bfdcd_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static struct clk_rcg2 nss_ce_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .cmd_rcgr = 0x68098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .freq_tbl = ftbl_nss_ce_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .name = "nss_ce_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .cmd_rcgr = 0x68088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .name = "nss_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static struct clk_fixed_factor nss_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .name = "nss_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) "nss_noc_bfdcd_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static struct clk_rcg2 nss_crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .cmd_rcgr = 0x68144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .freq_tbl = ftbl_nss_crypto_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .name = "nss_crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .parent_names = gcc_xo_nss_crypto_pll_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) F(187200000, P_UBI32_PLL, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) F(748800000, P_UBI32_PLL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) F(1497600000, P_UBI32_PLL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) F(1689600000, P_UBI32_PLL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static struct clk_rcg2 nss_ubi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .cmd_rcgr = 0x68104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .freq_tbl = ftbl_nss_ubi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .name = "nss_ubi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static struct clk_regmap_div nss_ubi0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .reg = 0x68118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .name = "nss_ubi0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) "nss_ubi0_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static struct clk_rcg2 nss_ubi1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .cmd_rcgr = 0x68124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .freq_tbl = ftbl_nss_ubi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .name = "nss_ubi1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static struct clk_regmap_div nss_ubi1_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .reg = 0x68138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .name = "nss_ubi1_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) "nss_ubi1_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) F(25000000, P_GPLL0_DIV2, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static struct clk_rcg2 ubi_mpt_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .cmd_rcgr = 0x68090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .freq_tbl = ftbl_ubi_mpt_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .parent_map = gcc_xo_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .name = "ubi_mpt_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .parent_names = gcc_xo_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static struct clk_rcg2 nss_imem_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .cmd_rcgr = 0x68158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .freq_tbl = ftbl_nss_imem_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .parent_map = gcc_xo_gpll0_gpll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .name = "nss_imem_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .parent_names = gcc_xo_gpll0_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) F(300000000, P_BIAS_PLL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static struct clk_rcg2 nss_ppe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .cmd_rcgr = 0x68080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .freq_tbl = ftbl_nss_ppe_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .name = "nss_ppe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .name = "nss_ppe_cdiv_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) F(25000000, P_UNIPHY0_RX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) F(125000000, P_UNIPHY0_RX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static struct clk_rcg2 nss_port1_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .cmd_rcgr = 0x68020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .name = "nss_port1_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static struct clk_regmap_div nss_port1_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .reg = 0x68400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .name = "nss_port1_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) "nss_port1_rx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) F(25000000, P_UNIPHY0_TX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) F(125000000, P_UNIPHY0_TX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static struct clk_rcg2 nss_port1_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .cmd_rcgr = 0x68028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .name = "nss_port1_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static struct clk_regmap_div nss_port1_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .reg = 0x68404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .name = "nss_port1_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) "nss_port1_tx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static struct clk_rcg2 nss_port2_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .cmd_rcgr = 0x68030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .name = "nss_port2_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static struct clk_regmap_div nss_port2_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .reg = 0x68410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .name = "nss_port2_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) "nss_port2_rx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static struct clk_rcg2 nss_port2_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .cmd_rcgr = 0x68038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .name = "nss_port2_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static struct clk_regmap_div nss_port2_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .reg = 0x68414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .name = "nss_port2_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) "nss_port2_tx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static struct clk_rcg2 nss_port3_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .cmd_rcgr = 0x68040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .name = "nss_port3_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static struct clk_regmap_div nss_port3_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .reg = 0x68420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .name = "nss_port3_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) "nss_port3_rx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static struct clk_rcg2 nss_port3_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .cmd_rcgr = 0x68048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .name = "nss_port3_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static struct clk_regmap_div nss_port3_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .reg = 0x68424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .name = "nss_port3_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) "nss_port3_tx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static struct clk_rcg2 nss_port4_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .cmd_rcgr = 0x68050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .name = "nss_port4_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static struct clk_regmap_div nss_port4_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .reg = 0x68430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .name = "nss_port4_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) "nss_port4_rx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static struct clk_rcg2 nss_port4_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .cmd_rcgr = 0x68058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .name = "nss_port4_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static struct clk_regmap_div nss_port4_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .reg = 0x68434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .name = "nss_port4_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) "nss_port4_tx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) F(78125000, P_UNIPHY1_RX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) F(156250000, P_UNIPHY1_RX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) F(312500000, P_UNIPHY1_RX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static struct clk_rcg2 nss_port5_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .cmd_rcgr = 0x68060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .freq_tbl = ftbl_nss_port5_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .name = "nss_port5_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static struct clk_regmap_div nss_port5_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .reg = 0x68440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .name = "nss_port5_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) "nss_port5_rx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) F(78125000, P_UNIPHY1_TX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) F(156250000, P_UNIPHY1_TX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) F(312500000, P_UNIPHY1_TX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static struct clk_rcg2 nss_port5_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .cmd_rcgr = 0x68068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .freq_tbl = ftbl_nss_port5_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .name = "nss_port5_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static struct clk_regmap_div nss_port5_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .reg = 0x68444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .name = "nss_port5_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) "nss_port5_tx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) F(78125000, P_UNIPHY2_RX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) F(156250000, P_UNIPHY2_RX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) F(312500000, P_UNIPHY2_RX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static struct clk_rcg2 nss_port6_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .cmd_rcgr = 0x68070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .freq_tbl = ftbl_nss_port6_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .name = "nss_port6_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static struct clk_regmap_div nss_port6_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .reg = 0x68450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .name = "nss_port6_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) "nss_port6_rx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) F(78125000, P_UNIPHY2_TX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) F(156250000, P_UNIPHY2_TX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) F(312500000, P_UNIPHY2_TX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static struct clk_rcg2 nss_port6_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .cmd_rcgr = 0x68078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .freq_tbl = ftbl_nss_port6_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .name = "nss_port6_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static struct clk_regmap_div nss_port6_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .reg = 0x68454,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .name = "nss_port6_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) "nss_port6_tx_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static struct freq_tbl ftbl_crypto_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) F(40000000, P_GPLL0_DIV2, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static struct clk_rcg2 crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .cmd_rcgr = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .freq_tbl = ftbl_crypto_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .name = "crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static struct freq_tbl ftbl_gp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .cmd_rcgr = 0x08004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .freq_tbl = ftbl_gp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .cmd_rcgr = 0x09004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .freq_tbl = ftbl_gp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .cmd_rcgr = 0x0a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .freq_tbl = ftbl_gp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .halt_reg = 0x01008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .enable_reg = 0x01008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .halt_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .enable_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) "blsp1_qup1_i2c_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .halt_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .enable_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) "blsp1_qup1_spi_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .halt_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .enable_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) "blsp1_qup2_i2c_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .halt_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .enable_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) "blsp1_qup2_spi_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .halt_reg = 0x04010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .enable_reg = 0x04010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) "blsp1_qup3_i2c_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .halt_reg = 0x0400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .enable_reg = 0x0400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) "blsp1_qup3_spi_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .halt_reg = 0x05010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .enable_reg = 0x05010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) "blsp1_qup4_i2c_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .halt_reg = 0x0500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .enable_reg = 0x0500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) "blsp1_qup4_spi_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .halt_reg = 0x06010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .enable_reg = 0x06010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) "blsp1_qup5_i2c_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .halt_reg = 0x0600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .enable_reg = 0x0600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) "blsp1_qup5_spi_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .halt_reg = 0x07010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .enable_reg = 0x07010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .name = "gcc_blsp1_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) "blsp1_qup6_i2c_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .halt_reg = 0x0700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .enable_reg = 0x0700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) "blsp1_qup6_spi_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .halt_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .enable_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) "blsp1_uart1_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .halt_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .enable_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) "blsp1_uart2_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static struct clk_branch gcc_blsp1_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .halt_reg = 0x0402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .enable_reg = 0x0402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .name = "gcc_blsp1_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) "blsp1_uart3_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) static struct clk_branch gcc_blsp1_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .halt_reg = 0x0502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .enable_reg = 0x0502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .name = "gcc_blsp1_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) "blsp1_uart4_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) static struct clk_branch gcc_blsp1_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .halt_reg = 0x0602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .enable_reg = 0x0602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .name = "gcc_blsp1_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) "blsp1_uart5_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) static struct clk_branch gcc_blsp1_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .halt_reg = 0x0702c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .enable_reg = 0x0702c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .name = "gcc_blsp1_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) "blsp1_uart6_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .halt_reg = 0x13004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) static struct clk_branch gcc_qpic_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .halt_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .enable_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .name = "gcc_qpic_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) static struct clk_branch gcc_qpic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .halt_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .enable_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .name = "gcc_qpic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) static struct clk_branch gcc_pcie0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .name = "gcc_pcie0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static struct clk_branch gcc_pcie0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .halt_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .enable_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .name = "gcc_pcie0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "pcie0_aux_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static struct clk_branch gcc_pcie0_axi_m_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .halt_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .enable_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .name = "gcc_pcie0_axi_m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) "pcie0_axi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) static struct clk_branch gcc_pcie0_axi_s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .halt_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .enable_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .name = "gcc_pcie0_axi_s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) "pcie0_axi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static struct clk_branch gcc_pcie0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .halt_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .enable_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .name = "gcc_pcie0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) "pcie0_pipe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .halt_reg = 0x26048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .enable_reg = 0x26048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .name = "gcc_sys_noc_pcie0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) "pcie0_axi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) static struct clk_branch gcc_pcie1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .halt_reg = 0x76010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .enable_reg = 0x76010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .name = "gcc_pcie1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static struct clk_branch gcc_pcie1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .halt_reg = 0x76014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .enable_reg = 0x76014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .name = "gcc_pcie1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) "pcie1_aux_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) static struct clk_branch gcc_pcie1_axi_m_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .halt_reg = 0x76008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .enable_reg = 0x76008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .name = "gcc_pcie1_axi_m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) "pcie1_axi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) static struct clk_branch gcc_pcie1_axi_s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .halt_reg = 0x7600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .enable_reg = 0x7600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .name = "gcc_pcie1_axi_s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) "pcie1_axi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static struct clk_branch gcc_pcie1_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .halt_reg = 0x76018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .enable_reg = 0x76018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .name = "gcc_pcie1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) "pcie1_pipe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .halt_reg = 0x2604c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .enable_reg = 0x2604c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .name = "gcc_sys_noc_pcie1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) "pcie1_axi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static struct clk_branch gcc_usb0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .halt_reg = 0x3e044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .enable_reg = 0x3e044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .name = "gcc_usb0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) "usb0_aux_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .halt_reg = 0x26040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .enable_reg = 0x26040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .name = "gcc_sys_noc_usb0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) "usb0_master_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static struct clk_branch gcc_usb0_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .halt_reg = 0x3e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .enable_reg = 0x3e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .name = "gcc_usb0_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) "usb0_master_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static struct clk_branch gcc_usb0_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .halt_reg = 0x3e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .enable_reg = 0x3e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .name = "gcc_usb0_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) "usb0_mock_utmi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .halt_reg = 0x3e080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .enable_reg = 0x3e080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .name = "gcc_usb0_phy_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static struct clk_branch gcc_usb0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .halt_reg = 0x3e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .enable_reg = 0x3e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .name = "gcc_usb0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) "usb0_pipe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) static struct clk_branch gcc_usb0_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .halt_reg = 0x3e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .enable_reg = 0x3e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .name = "gcc_usb0_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) "gcc_sleep_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static struct clk_branch gcc_usb1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .halt_reg = 0x3f044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .enable_reg = 0x3f044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .name = "gcc_usb1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) "usb1_aux_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .halt_reg = 0x26044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .enable_reg = 0x26044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .name = "gcc_sys_noc_usb1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) "usb1_master_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) static struct clk_branch gcc_usb1_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .halt_reg = 0x3f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .enable_reg = 0x3f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .name = "gcc_usb1_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) "usb1_master_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) static struct clk_branch gcc_usb1_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .halt_reg = 0x3f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .enable_reg = 0x3f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .name = "gcc_usb1_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) "usb1_mock_utmi_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .halt_reg = 0x3f080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .enable_reg = 0x3f080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .name = "gcc_usb1_phy_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) static struct clk_branch gcc_usb1_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .halt_reg = 0x3f040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .enable_reg = 0x3f040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .name = "gcc_usb1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) "usb1_pipe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) static struct clk_branch gcc_usb1_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .halt_reg = 0x3f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .enable_reg = 0x3f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .name = "gcc_usb1_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) "gcc_sleep_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .halt_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .enable_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .halt_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .enable_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) "sdcc1_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) static struct clk_branch gcc_sdcc1_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .halt_reg = 0x5d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .enable_reg = 0x5d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .name = "gcc_sdcc1_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) "sdcc1_ice_core_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .halt_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .enable_reg = 0x4301c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .halt_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .enable_reg = 0x43018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) "sdcc2_apps_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) static struct clk_branch gcc_mem_noc_nss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .halt_reg = 0x1d03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .enable_reg = 0x1d03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) .name = "gcc_mem_noc_nss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) "nss_noc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) static struct clk_branch gcc_nss_ce_apb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .halt_reg = 0x68174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .enable_reg = 0x68174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) .name = "gcc_nss_ce_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static struct clk_branch gcc_nss_ce_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .halt_reg = 0x68170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .enable_reg = 0x68170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .name = "gcc_nss_ce_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) static struct clk_branch gcc_nss_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) .halt_reg = 0x68160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .enable_reg = 0x68160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .name = "gcc_nss_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) static struct clk_branch gcc_nss_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) .halt_reg = 0x68164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .enable_reg = 0x68164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .name = "gcc_nss_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) "nss_crypto_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static struct clk_branch gcc_nss_csr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .halt_reg = 0x68318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .enable_reg = 0x68318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .name = "gcc_nss_csr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) static struct clk_branch gcc_nss_edma_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .halt_reg = 0x6819c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .enable_reg = 0x6819c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .name = "gcc_nss_edma_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) static struct clk_branch gcc_nss_edma_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) .halt_reg = 0x68198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) .enable_reg = 0x68198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .name = "gcc_nss_edma_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) static struct clk_branch gcc_nss_imem_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .halt_reg = 0x68178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) .enable_reg = 0x68178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .name = "gcc_nss_imem_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) "nss_imem_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) static struct clk_branch gcc_nss_noc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .halt_reg = 0x68168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .enable_reg = 0x68168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) .name = "gcc_nss_noc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) "nss_noc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) static struct clk_branch gcc_nss_ppe_btq_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) .halt_reg = 0x6833c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) .enable_reg = 0x6833c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) .name = "gcc_nss_ppe_btq_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static struct clk_branch gcc_nss_ppe_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .halt_reg = 0x68194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) .enable_reg = 0x68194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) .name = "gcc_nss_ppe_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) static struct clk_branch gcc_nss_ppe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) .halt_reg = 0x68190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) .enable_reg = 0x68190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) .name = "gcc_nss_ppe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) static struct clk_branch gcc_nss_ppe_ipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .halt_reg = 0x68338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) .enable_reg = 0x68338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) .name = "gcc_nss_ppe_ipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) static struct clk_branch gcc_nss_ptp_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .halt_reg = 0x6816c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) .enable_reg = 0x6816c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) .name = "gcc_nss_ptp_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) "nss_ppe_cdiv_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) static struct clk_branch gcc_nssnoc_ce_apb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) .halt_reg = 0x6830c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) .enable_reg = 0x6830c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) .name = "gcc_nssnoc_ce_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) static struct clk_branch gcc_nssnoc_ce_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) .halt_reg = 0x68308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) .enable_reg = 0x68308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .name = "gcc_nssnoc_ce_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) static struct clk_branch gcc_nssnoc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) .halt_reg = 0x68314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) .enable_reg = 0x68314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .name = "gcc_nssnoc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) "nss_crypto_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) .halt_reg = 0x68304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .enable_reg = 0x68304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) .name = "gcc_nssnoc_ppe_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) static struct clk_branch gcc_nssnoc_ppe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) .halt_reg = 0x68300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) .enable_reg = 0x68300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) .name = "gcc_nssnoc_ppe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .halt_reg = 0x68180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) .enable_reg = 0x68180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) .name = "gcc_nssnoc_qosgen_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) "gcc_xo_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) static struct clk_branch gcc_nssnoc_snoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) .halt_reg = 0x68188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .enable_reg = 0x68188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .name = "gcc_nssnoc_snoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) "system_noc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) .halt_reg = 0x68184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) .enable_reg = 0x68184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) .name = "gcc_nssnoc_timeout_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) "gcc_xo_div4_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) .halt_reg = 0x68270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) .enable_reg = 0x68270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) .name = "gcc_nssnoc_ubi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) .halt_reg = 0x68274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .enable_reg = 0x68274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .name = "gcc_nssnoc_ubi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) static struct clk_branch gcc_ubi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) .halt_reg = 0x6820c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) .enable_reg = 0x6820c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) .name = "gcc_ubi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) static struct clk_branch gcc_ubi0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) .halt_reg = 0x68200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .enable_reg = 0x68200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) .name = "gcc_ubi0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) "nss_noc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) static struct clk_branch gcc_ubi0_nc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) .halt_reg = 0x68204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) .enable_reg = 0x68204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) .name = "gcc_ubi0_nc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) "nss_noc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) static struct clk_branch gcc_ubi0_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) .halt_reg = 0x68210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) .enable_reg = 0x68210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) .name = "gcc_ubi0_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) "nss_ubi0_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) static struct clk_branch gcc_ubi0_mpt_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) .halt_reg = 0x68208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) .enable_reg = 0x68208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) .name = "gcc_ubi0_mpt_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) "ubi_mpt_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) static struct clk_branch gcc_ubi1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) .halt_reg = 0x6822c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) .enable_reg = 0x6822c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) .name = "gcc_ubi1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) "nss_ce_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) static struct clk_branch gcc_ubi1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) .halt_reg = 0x68220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) .enable_reg = 0x68220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) .name = "gcc_ubi1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) "nss_noc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) static struct clk_branch gcc_ubi1_nc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) .halt_reg = 0x68224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) .enable_reg = 0x68224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) .name = "gcc_ubi1_nc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) "nss_noc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) static struct clk_branch gcc_ubi1_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) .halt_reg = 0x68230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) .enable_reg = 0x68230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) .name = "gcc_ubi1_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) "nss_ubi1_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) static struct clk_branch gcc_ubi1_mpt_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) .halt_reg = 0x68228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) .enable_reg = 0x68228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) .name = "gcc_ubi1_mpt_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) "ubi_mpt_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) .halt_reg = 0x56308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) .enable_reg = 0x56308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) .name = "gcc_cmn_12gpll_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) static struct clk_branch gcc_cmn_12gpll_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) .halt_reg = 0x5630c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) .enable_reg = 0x5630c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) .name = "gcc_cmn_12gpll_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) "gcc_xo_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) static struct clk_branch gcc_mdio_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) .halt_reg = 0x58004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) .enable_reg = 0x58004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) .name = "gcc_mdio_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) static struct clk_branch gcc_uniphy0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) .halt_reg = 0x56008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) .enable_reg = 0x56008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) .name = "gcc_uniphy0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) static struct clk_branch gcc_uniphy0_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) .halt_reg = 0x5600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) .enable_reg = 0x5600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) .name = "gcc_uniphy0_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) "gcc_xo_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) static struct clk_branch gcc_uniphy1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) .halt_reg = 0x56108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) .enable_reg = 0x56108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) .name = "gcc_uniphy1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) static struct clk_branch gcc_uniphy1_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) .halt_reg = 0x5610c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) .enable_reg = 0x5610c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) .name = "gcc_uniphy1_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) "gcc_xo_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) static struct clk_branch gcc_uniphy2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) .halt_reg = 0x56208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) .enable_reg = 0x56208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) .name = "gcc_uniphy2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) static struct clk_branch gcc_uniphy2_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) .halt_reg = 0x5620c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) .enable_reg = 0x5620c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) .name = "gcc_uniphy2_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) "gcc_xo_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) static struct clk_branch gcc_nss_port1_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) .halt_reg = 0x68240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) .enable_reg = 0x68240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) .name = "gcc_nss_port1_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) "nss_port1_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) static struct clk_branch gcc_nss_port1_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) .halt_reg = 0x68244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) .enable_reg = 0x68244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) .name = "gcc_nss_port1_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) "nss_port1_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) static struct clk_branch gcc_nss_port2_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) .halt_reg = 0x68248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) .enable_reg = 0x68248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) .name = "gcc_nss_port2_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) "nss_port2_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) static struct clk_branch gcc_nss_port2_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) .halt_reg = 0x6824c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) .enable_reg = 0x6824c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) .name = "gcc_nss_port2_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) "nss_port2_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) static struct clk_branch gcc_nss_port3_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) .halt_reg = 0x68250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) .enable_reg = 0x68250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) .name = "gcc_nss_port3_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) "nss_port3_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) static struct clk_branch gcc_nss_port3_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) .halt_reg = 0x68254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) .enable_reg = 0x68254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) .name = "gcc_nss_port3_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) "nss_port3_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) static struct clk_branch gcc_nss_port4_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) .halt_reg = 0x68258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) .enable_reg = 0x68258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) .name = "gcc_nss_port4_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) "nss_port4_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) static struct clk_branch gcc_nss_port4_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) .halt_reg = 0x6825c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) .enable_reg = 0x6825c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) .name = "gcc_nss_port4_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) "nss_port4_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) static struct clk_branch gcc_nss_port5_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) .halt_reg = 0x68260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) .enable_reg = 0x68260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) .name = "gcc_nss_port5_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) "nss_port5_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) static struct clk_branch gcc_nss_port5_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) .halt_reg = 0x68264,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) .enable_reg = 0x68264,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) .name = "gcc_nss_port5_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) "nss_port5_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) static struct clk_branch gcc_nss_port6_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) .halt_reg = 0x68268,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) .enable_reg = 0x68268,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) .name = "gcc_nss_port6_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) "nss_port6_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) static struct clk_branch gcc_nss_port6_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) .halt_reg = 0x6826c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) .enable_reg = 0x6826c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) .name = "gcc_nss_port6_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) "nss_port6_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) static struct clk_branch gcc_port1_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) .halt_reg = 0x68320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) .enable_reg = 0x68320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) .name = "gcc_port1_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) static struct clk_branch gcc_port2_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) .halt_reg = 0x68324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) .enable_reg = 0x68324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) .name = "gcc_port2_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) static struct clk_branch gcc_port3_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) .halt_reg = 0x68328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) .enable_reg = 0x68328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) .name = "gcc_port3_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) static struct clk_branch gcc_port4_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) .halt_reg = 0x6832c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) .enable_reg = 0x6832c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) .name = "gcc_port4_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) static struct clk_branch gcc_port5_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) .halt_reg = 0x68330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) .enable_reg = 0x68330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) .name = "gcc_port5_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) static struct clk_branch gcc_port6_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) .halt_reg = 0x68334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) .enable_reg = 0x68334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) .name = "gcc_port6_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) "nss_ppe_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) static struct clk_branch gcc_uniphy0_port1_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) .halt_reg = 0x56010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) .enable_reg = 0x56010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) .name = "gcc_uniphy0_port1_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) "nss_port1_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) static struct clk_branch gcc_uniphy0_port1_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) .halt_reg = 0x56014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) .enable_reg = 0x56014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) .name = "gcc_uniphy0_port1_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) "nss_port1_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) static struct clk_branch gcc_uniphy0_port2_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) .halt_reg = 0x56018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) .enable_reg = 0x56018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) .name = "gcc_uniphy0_port2_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) "nss_port2_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) static struct clk_branch gcc_uniphy0_port2_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) .halt_reg = 0x5601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) .enable_reg = 0x5601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) .name = "gcc_uniphy0_port2_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) "nss_port2_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) static struct clk_branch gcc_uniphy0_port3_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) .halt_reg = 0x56020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) .enable_reg = 0x56020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) .name = "gcc_uniphy0_port3_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) "nss_port3_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) static struct clk_branch gcc_uniphy0_port3_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) .halt_reg = 0x56024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) .enable_reg = 0x56024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) .name = "gcc_uniphy0_port3_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) "nss_port3_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) static struct clk_branch gcc_uniphy0_port4_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) .halt_reg = 0x56028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) .enable_reg = 0x56028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) .name = "gcc_uniphy0_port4_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) "nss_port4_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) static struct clk_branch gcc_uniphy0_port4_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) .halt_reg = 0x5602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) .enable_reg = 0x5602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) .name = "gcc_uniphy0_port4_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) "nss_port4_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) static struct clk_branch gcc_uniphy0_port5_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) .halt_reg = 0x56030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) .enable_reg = 0x56030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) .name = "gcc_uniphy0_port5_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) "nss_port5_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) static struct clk_branch gcc_uniphy0_port5_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) .halt_reg = 0x56034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) .enable_reg = 0x56034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) .name = "gcc_uniphy0_port5_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) "nss_port5_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) static struct clk_branch gcc_uniphy1_port5_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) .halt_reg = 0x56110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) .enable_reg = 0x56110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) .name = "gcc_uniphy1_port5_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) "nss_port5_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) static struct clk_branch gcc_uniphy1_port5_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) .halt_reg = 0x56114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) .enable_reg = 0x56114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) .name = "gcc_uniphy1_port5_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) "nss_port5_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) static struct clk_branch gcc_uniphy2_port6_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) .halt_reg = 0x56210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) .enable_reg = 0x56210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) .name = "gcc_uniphy2_port6_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) "nss_port6_rx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) static struct clk_branch gcc_uniphy2_port6_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) .halt_reg = 0x56214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) .enable_reg = 0x56214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) .name = "gcc_uniphy2_port6_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) "nss_port6_tx_div_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) static struct clk_branch gcc_crypto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) .halt_reg = 0x16024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) .name = "gcc_crypto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) static struct clk_branch gcc_crypto_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) .halt_reg = 0x16020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) .name = "gcc_crypto_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) "pcnoc_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) static struct clk_branch gcc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) .halt_reg = 0x1601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) .name = "gcc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) "crypto_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) .halt_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) .enable_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) "gp1_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) .halt_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) .enable_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) "gp2_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) .halt_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) .enable_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) "gp3_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) static struct clk_rcg2 pcie0_rchng_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) .cmd_rcgr = 0x75070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) .freq_tbl = ftbl_pcie_rchng_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) .name = "pcie0_rchng_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) static struct clk_branch gcc_pcie0_rchng_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) .halt_reg = 0x75070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) .halt_bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) .enable_reg = 0x75070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) .name = "gcc_pcie0_rchng_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) &pcie0_rchng_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) .halt_reg = 0x75048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) .halt_bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) .enable_reg = 0x75048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) .name = "gcc_pcie0_axi_s_bridge_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) &pcie0_axi_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) static struct clk_hw *gcc_ipq8074_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) &gpll0_out_main_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) &gpll6_out_main_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) &pcnoc_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) &system_noc_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) &gcc_xo_div4_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) &nss_noc_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) &nss_ppe_cdiv_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) static struct clk_regmap *gcc_ipq8074_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) [GPLL0_MAIN] = &gpll0_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) [GPLL2_MAIN] = &gpll2_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) [GPLL2] = &gpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) [GPLL4_MAIN] = &gpll4_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) [GPLL6_MAIN] = &gpll6_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) [GPLL6] = &gpll6.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) [UBI32_PLL] = &ubi32_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) static const struct qcom_reset_map gcc_ipq8074_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) [GCC_BLSP1_BCR] = { 0x01000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) [GCC_IMEM_BCR] = { 0x0e000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) [GCC_SMMU_BCR] = { 0x12000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) [GCC_PRNG_BCR] = { 0x13000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) [GCC_CRYPTO_BCR] = { 0x16000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) [GCC_WCSS_BCR] = { 0x18000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) [GCC_NSS_BCR] = { 0x19000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) [GCC_ADSS_BCR] = { 0x1c000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) [GCC_DDRSS_BCR] = { 0x1e000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) [GCC_PCNOC_BCR] = { 0x27018, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) [GCC_TCSR_BCR] = { 0x28000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) [GCC_QDSS_BCR] = { 0x29000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) [GCC_DCD_BCR] = { 0x2a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) [GCC_MPM_BCR] = { 0x2c000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) [GCC_SPMI_BCR] = { 0x2e000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) [GCC_SPDM_BCR] = { 0x2f000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) [GCC_RBCPR_BCR] = { 0x33000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) [GCC_TLMM_BCR] = { 0x34000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) [GCC_USB0_BCR] = { 0x3e070, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) [GCC_USB1_BCR] = { 0x3f070, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) [GCC_SDCC1_BCR] = { 0x42000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) [GCC_SDCC2_BCR] = { 0x43000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) [GCC_QPIC_BCR] = { 0x57018, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) [GCC_MDIO_BCR] = { 0x58000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) [GCC_PCIE0_BCR] = { 0x75004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) [GCC_PCIE1_BCR] = { 0x76004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) [GCC_DCC_BCR] = { 0x77000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) static const struct of_device_id gcc_ipq8074_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) { .compatible = "qcom,gcc-ipq8074" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) static const struct regmap_config gcc_ipq8074_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) .max_register = 0x7fffc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) static const struct qcom_cc_desc gcc_ipq8074_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) .config = &gcc_ipq8074_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) .clks = gcc_ipq8074_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) .resets = gcc_ipq8074_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) .clk_hws = gcc_ipq8074_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) static int gcc_ipq8074_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) static struct platform_driver gcc_ipq8074_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) .probe = gcc_ipq8074_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) .name = "qcom,gcc-ipq8074",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) .of_match_table = gcc_ipq8074_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) static int __init gcc_ipq8074_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) return platform_driver_register(&gcc_ipq8074_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) core_initcall(gcc_ipq8074_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) static void __exit gcc_ipq8074_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) platform_driver_unregister(&gcc_ipq8074_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) module_exit(gcc_ipq8074_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) MODULE_ALIAS("platform:gcc-ipq8074");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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