^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk-hfpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct clk_pll pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .l_reg = 0x30c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .m_reg = 0x30c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .n_reg = 0x30cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .config_reg = 0x30d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .mode_reg = 0x30c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .status_reg = 0x30d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = "pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct clk_regmap pll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "pll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .parent_names = (const char *[]){ "pll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct clk_pll pll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .l_reg = 0x3164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .m_reg = 0x3168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .n_reg = 0x316c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .config_reg = 0x3174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .mode_reg = 0x3160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .status_reg = 0x3178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct clk_regmap pll4_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "pll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .parent_names = (const char *[]){ "pll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct clk_pll pll8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .l_reg = 0x3144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .m_reg = 0x3148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .n_reg = 0x314c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .config_reg = 0x3154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .mode_reg = 0x3140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .status_reg = 0x3158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "pll8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct clk_regmap pll8_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .parent_names = (const char *[]){ "pll8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct hfpll_data hfpll0_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .mode_reg = 0x3200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .l_reg = 0x3208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .m_reg = 0x320c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .n_reg = 0x3210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .config_reg = 0x3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .status_reg = 0x321c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .droop_reg = 0x3214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct clk_hfpll hfpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .d = &hfpll0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "hfpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct hfpll_data hfpll1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mode_reg = 0x3240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .l_reg = 0x3248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .m_reg = 0x324c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .n_reg = 0x3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .config_reg = 0x3244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .status_reg = 0x325c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .droop_reg = 0x3314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct clk_hfpll hfpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .d = &hfpll1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "hfpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct hfpll_data hfpll_l2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .mode_reg = 0x3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .l_reg = 0x3308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .m_reg = 0x330c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .n_reg = 0x3310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .config_reg = 0x3304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .status_reg = 0x331c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .config_val = 0x7845c665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .droop_reg = 0x3314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .droop_val = 0x0108c000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .min_rate = 600000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .max_rate = 1800000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct clk_hfpll hfpll_l2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .d = &hfpll_l2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = "hfpll_l2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .ops = &clk_ops_hfpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct clk_pll pll14 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .l_reg = 0x31c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .m_reg = 0x31c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .n_reg = 0x31cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .config_reg = 0x31d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .mode_reg = 0x31c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .status_reg = 0x31d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .name = "pll14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct clk_regmap pll14_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .enable_reg = 0x34c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "pll14_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .parent_names = (const char *[]){ "pll14" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define NSS_PLL_RATE(f, _l, _m, _n, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .freq = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .l = _l, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .m = _m, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .n = _n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ibits = i, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct pll_freq_tbl pll18_freq_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct clk_pll pll18 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .l_reg = 0x31a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .m_reg = 0x31a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .n_reg = 0x31ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .config_reg = 0x31b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .mode_reg = 0x31a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .status_reg = 0x31b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .status_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .post_div_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .post_div_width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .freq_tbl = pll18_freq_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = "pll18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) P_PXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) P_PLL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) P_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) P_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) P_CXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) P_PLL14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) P_PLL18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct parent_map gcc_pxo_pll8_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { P_PLL8, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const char * const gcc_pxo_pll8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { P_PLL8, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { P_CXO, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const char * const gcc_pxo_pll8_cxo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "cxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct parent_map gcc_pxo_pll3_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { P_PLL3, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct parent_map gcc_pxo_pll3_sata_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { P_PLL3, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char * const gcc_pxo_pll3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct parent_map gcc_pxo_pll8_pll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { P_PLL8, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { P_PLL0, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const char * const gcc_pxo_pll8_pll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "pll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { P_PXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { P_PLL8, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { P_PLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { P_PLL14, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { P_PLL18, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "pxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "pll8_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "pll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "pll14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "pll18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct freq_tbl clk_tbl_gsbi_uart[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 1843200, P_PLL8, 2, 6, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 3686400, P_PLL8, 2, 12, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 7372800, P_PLL8, 2, 24, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 14745600, P_PLL8, 2, 48, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 32000000, P_PLL8, 4, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 40000000, P_PLL8, 1, 5, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 46400000, P_PLL8, 1, 29, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 56000000, P_PLL8, 1, 7, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 58982400, P_PLL8, 1, 96, 625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct clk_rcg gsbi1_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .ns_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .md_reg = 0x29d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct clk_branch gsbi1_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .enable_reg = 0x29d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "gsbi1_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "gsbi1_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct clk_rcg gsbi2_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .ns_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .md_reg = 0x29f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .name = "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct clk_branch gsbi2_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .enable_reg = 0x29f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .name = "gsbi2_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "gsbi2_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct clk_rcg gsbi4_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .ns_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .md_reg = 0x2a30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .name = "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct clk_branch gsbi4_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .enable_reg = 0x2a34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = "gsbi4_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "gsbi4_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct clk_rcg gsbi5_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .ns_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .md_reg = 0x2a50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .name = "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct clk_branch gsbi5_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .enable_reg = 0x2a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .name = "gsbi5_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "gsbi5_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static struct clk_rcg gsbi6_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ns_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .md_reg = 0x2a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .enable_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .name = "gsbi6_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct clk_branch gsbi6_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .enable_reg = 0x2a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .name = "gsbi6_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "gsbi6_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct clk_rcg gsbi7_uart_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .ns_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .md_reg = 0x2a90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .freq_tbl = clk_tbl_gsbi_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .enable_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .name = "gsbi7_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static struct clk_branch gsbi7_uart_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .enable_reg = 0x2a94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .name = "gsbi7_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "gsbi7_uart_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct freq_tbl clk_tbl_gsbi_qup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { 1100000, P_PXO, 1, 2, 49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { 5400000, P_PXO, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { 10800000, P_PXO, 1, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { 15060000, P_PLL8, 1, 2, 51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { 25000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { 25600000, P_PLL8, 1, 1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { 51200000, P_PLL8, 1, 2, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct clk_rcg gsbi1_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .ns_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .md_reg = 0x29c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .name = "gsbi1_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct clk_branch gsbi1_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .enable_reg = 0x29cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .name = "gsbi1_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .parent_names = (const char *[]){ "gsbi1_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static struct clk_rcg gsbi2_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .ns_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .md_reg = 0x29e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .name = "gsbi2_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct clk_branch gsbi2_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .enable_reg = 0x29ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .name = "gsbi2_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .parent_names = (const char *[]){ "gsbi2_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct clk_rcg gsbi4_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .ns_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .md_reg = 0x2a28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .name = "gsbi4_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static struct clk_branch gsbi4_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .enable_reg = 0x2a2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .name = "gsbi4_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .parent_names = (const char *[]){ "gsbi4_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static struct clk_rcg gsbi5_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .ns_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .md_reg = 0x2a48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .name = "gsbi5_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static struct clk_branch gsbi5_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .enable_reg = 0x2a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .name = "gsbi5_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .parent_names = (const char *[]){ "gsbi5_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static struct clk_rcg gsbi6_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .ns_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .md_reg = 0x2a68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .enable_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .name = "gsbi6_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static struct clk_branch gsbi6_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .halt_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .enable_reg = 0x2a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .name = "gsbi6_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .parent_names = (const char *[]){ "gsbi6_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static struct clk_rcg gsbi7_qup_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .ns_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .md_reg = 0x2a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .freq_tbl = clk_tbl_gsbi_qup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .enable_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .name = "gsbi7_qup_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static struct clk_branch gsbi7_qup_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .enable_reg = 0x2a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = "gsbi7_qup_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .parent_names = (const char *[]){ "gsbi7_qup_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static struct clk_branch gsbi1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .hwcg_reg = 0x29c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .enable_reg = 0x29c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .name = "gsbi1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static struct clk_branch gsbi2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .hwcg_reg = 0x29e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .enable_reg = 0x29e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .name = "gsbi2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static struct clk_branch gsbi4_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .hwcg_reg = 0x2a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .enable_reg = 0x2a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .name = "gsbi4_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static struct clk_branch gsbi5_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .hwcg_reg = 0x2a40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .enable_reg = 0x2a40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .name = "gsbi5_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static struct clk_branch gsbi6_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .hwcg_reg = 0x2a60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .enable_reg = 0x2a60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .name = "gsbi6_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static struct clk_branch gsbi7_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .hwcg_reg = 0x2a80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .halt_reg = 0x2fd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .enable_reg = 0x2a80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .name = "gsbi7_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const struct freq_tbl clk_tbl_gp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) { 12500000, P_PXO, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { 25000000, P_PXO, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { 64000000, P_PLL8, 2, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { 76800000, P_PLL8, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { 96000000, P_PLL8, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { 128000000, P_PLL8, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) { 192000000, P_PLL8, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static struct clk_rcg gp0_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .ns_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .md_reg = 0x2d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .name = "gp0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .flags = CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static struct clk_branch gp0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .enable_reg = 0x2d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .name = "gp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .parent_names = (const char *[]){ "gp0_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static struct clk_rcg gp1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .ns_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .md_reg = 0x2d40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .name = "gp1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static struct clk_branch gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .enable_reg = 0x2d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .name = "gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .parent_names = (const char *[]){ "gp1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static struct clk_rcg gp2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .ns_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .md_reg = 0x2d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .parent_map = gcc_pxo_pll8_cxo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .freq_tbl = clk_tbl_gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .name = "gp2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .parent_names = gcc_pxo_pll8_cxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static struct clk_branch gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .enable_reg = 0x2d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .name = "gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .parent_names = (const char *[]){ "gp2_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static struct clk_branch pmem_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .hwcg_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .enable_reg = 0x25a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .name = "pmem_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static struct clk_rcg prng_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .ns_reg = 0x2e80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .enable_reg = 0x2e80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .name = "prng_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static struct clk_branch prng_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .name = "prng_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .parent_names = (const char *[]){ "prng_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static const struct freq_tbl clk_tbl_sdc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) { 200000, P_PXO, 2, 2, 125 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) { 400000, P_PLL8, 4, 1, 240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) { 16000000, P_PLL8, 4, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) { 17070000, P_PLL8, 1, 2, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) { 20210000, P_PLL8, 1, 1, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) { 24000000, P_PLL8, 4, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) { 48000000, P_PLL8, 4, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) { 64000000, P_PLL8, 3, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) { 96000000, P_PLL8, 4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) { 192000000, P_PLL8, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static struct clk_rcg sdc1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .ns_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .md_reg = 0x2828,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .name = "sdc1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static struct clk_branch sdc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .enable_reg = 0x282c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .name = "sdc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .parent_names = (const char *[]){ "sdc1_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static struct clk_rcg sdc3_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .ns_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .md_reg = 0x2868,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .freq_tbl = clk_tbl_sdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .enable_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .name = "sdc3_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static struct clk_branch sdc3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .enable_reg = 0x286c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .name = "sdc3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .parent_names = (const char *[]){ "sdc3_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static struct clk_branch sdc1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .hwcg_reg = 0x2820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .enable_reg = 0x2820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .name = "sdc1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static struct clk_branch sdc3_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .hwcg_reg = 0x2860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .enable_reg = 0x2860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .name = "sdc3_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static const struct freq_tbl clk_tbl_tsif_ref[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) { 105000, P_PXO, 1, 1, 256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static struct clk_rcg tsif_ref_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .ns_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .md_reg = 0x270c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .parent_map = gcc_pxo_pll8_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .freq_tbl = clk_tbl_tsif_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .enable_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .name = "tsif_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .parent_names = gcc_pxo_pll8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static struct clk_branch tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .enable_reg = 0x2710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .name = "tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .parent_names = (const char *[]){ "tsif_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static struct clk_branch tsif_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .hwcg_reg = 0x2700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .enable_reg = 0x2700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .name = "tsif_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static struct clk_branch dma_bam_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .hwcg_reg = 0x25c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .enable_reg = 0x25c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .name = "dma_bam_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static struct clk_branch adm0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .name = "adm0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static struct clk_branch adm0_pbus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .hwcg_reg = 0x2208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .halt_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .name = "adm0_pbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static struct clk_branch pmic_arb0_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .name = "pmic_arb0_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static struct clk_branch pmic_arb1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .name = "pmic_arb1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static struct clk_branch pmic_ssbi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .name = "pmic_ssbi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static struct clk_branch rpm_msg_ram_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .hwcg_reg = 0x27e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .halt_reg = 0x2fd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .enable_reg = 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .name = "rpm_msg_ram_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const struct freq_tbl clk_tbl_pcie_ref[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) { 100000000, P_PLL3, 12, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static struct clk_rcg pcie_ref_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .ns_reg = 0x3860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .parent_map = gcc_pxo_pll3_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .freq_tbl = clk_tbl_pcie_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .enable_reg = 0x3860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .name = "pcie_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .parent_names = gcc_pxo_pll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static struct clk_branch pcie_ref_src_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .halt_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .enable_reg = 0x3860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .name = "pcie_ref_src_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .parent_names = (const char *[]){ "pcie_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static struct clk_branch pcie_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .halt_reg = 0x2fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .halt_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .enable_reg = 0x22c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .name = "pcie_a_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static struct clk_branch pcie_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .halt_bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .enable_reg = 0x22c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .name = "pcie_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static struct clk_branch pcie_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .halt_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .enable_reg = 0x22cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .name = "pcie_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static struct clk_branch pcie_phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .halt_bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .enable_reg = 0x22d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .name = "pcie_phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static struct clk_rcg pcie1_ref_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .ns_reg = 0x3aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .parent_map = gcc_pxo_pll3_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .freq_tbl = clk_tbl_pcie_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .enable_reg = 0x3aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .name = "pcie1_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .parent_names = gcc_pxo_pll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static struct clk_branch pcie1_ref_src_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .halt_bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .enable_reg = 0x3aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .name = "pcie1_ref_src_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .parent_names = (const char *[]){ "pcie1_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static struct clk_branch pcie1_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .halt_reg = 0x2fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .enable_reg = 0x3a80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .name = "pcie1_a_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static struct clk_branch pcie1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .halt_bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .enable_reg = 0x3a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .name = "pcie1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static struct clk_branch pcie1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .enable_reg = 0x3a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .name = "pcie1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static struct clk_branch pcie1_phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .halt_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .enable_reg = 0x3a90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .name = "pcie1_phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static struct clk_rcg pcie2_ref_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .ns_reg = 0x3ae0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .parent_map = gcc_pxo_pll3_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .freq_tbl = clk_tbl_pcie_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .enable_reg = 0x3ae0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .name = "pcie2_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .parent_names = gcc_pxo_pll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static struct clk_branch pcie2_ref_src_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .halt_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .enable_reg = 0x3ae0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .name = "pcie2_ref_src_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .parent_names = (const char *[]){ "pcie2_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static struct clk_branch pcie2_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .halt_reg = 0x2fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .halt_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .enable_reg = 0x3ac0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .name = "pcie2_a_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static struct clk_branch pcie2_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .halt_bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .enable_reg = 0x3ac8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .name = "pcie2_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static struct clk_branch pcie2_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .halt_reg = 0x2fd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .halt_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .enable_reg = 0x3acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .name = "pcie2_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static struct clk_branch pcie2_phy_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .halt_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .enable_reg = 0x3ad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .name = "pcie2_phy_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static const struct freq_tbl clk_tbl_sata_ref[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) { 100000000, P_PLL3, 12, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static struct clk_rcg sata_ref_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .ns_reg = 0x2c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .parent_map = gcc_pxo_pll3_sata_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .freq_tbl = clk_tbl_sata_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .enable_reg = 0x2c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .name = "sata_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .parent_names = gcc_pxo_pll3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static struct clk_branch sata_rxoob_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .halt_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .enable_reg = 0x2c0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .name = "sata_rxoob_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .parent_names = (const char *[]){ "sata_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static struct clk_branch sata_pmalive_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .enable_reg = 0x2c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .name = "sata_pmalive_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .parent_names = (const char *[]){ "sata_ref_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static struct clk_branch sata_phy_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .enable_reg = 0x2c14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .name = "sata_phy_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .parent_names = (const char *[]){ "pxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static struct clk_branch sata_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .halt_reg = 0x2fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .halt_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .enable_reg = 0x2c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .name = "sata_a_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) static struct clk_branch sata_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .halt_reg = 0x2fdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .enable_reg = 0x2c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .name = "sata_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static struct clk_branch sfab_sata_s_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .halt_reg = 0x2fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .enable_reg = 0x2480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .name = "sfab_sata_s_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static struct clk_branch sata_phy_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .enable_reg = 0x2c40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .name = "sata_phy_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static const struct freq_tbl clk_tbl_usb30_master[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) { 125000000, P_PLL0, 1, 5, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static struct clk_rcg usb30_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .ns_reg = 0x3b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .md_reg = 0x3b28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .parent_map = gcc_pxo_pll8_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .freq_tbl = clk_tbl_usb30_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .enable_reg = 0x3b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .name = "usb30_master_ref_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .parent_names = gcc_pxo_pll8_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static struct clk_branch usb30_0_branch_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .halt_reg = 0x2fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .halt_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .enable_reg = 0x3b24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .name = "usb30_0_branch_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .parent_names = (const char *[]){ "usb30_master_ref_src", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static struct clk_branch usb30_1_branch_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .halt_reg = 0x2fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .enable_reg = 0x3b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .name = "usb30_1_branch_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .parent_names = (const char *[]){ "usb30_master_ref_src", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static const struct freq_tbl clk_tbl_usb30_utmi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) { 60000000, P_PLL8, 1, 5, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static struct clk_rcg usb30_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .ns_reg = 0x3b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .md_reg = 0x3b40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .parent_map = gcc_pxo_pll8_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .freq_tbl = clk_tbl_usb30_utmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .enable_reg = 0x3b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .name = "usb30_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .parent_names = gcc_pxo_pll8_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) static struct clk_branch usb30_0_utmi_clk_ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .halt_reg = 0x2fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .halt_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .enable_reg = 0x3b48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .name = "usb30_0_utmi_clk_ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .parent_names = (const char *[]){ "usb30_utmi_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static struct clk_branch usb30_1_utmi_clk_ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .halt_reg = 0x2fc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .halt_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .enable_reg = 0x3b4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .name = "usb30_1_utmi_clk_ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .parent_names = (const char *[]){ "usb30_utmi_clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static const struct freq_tbl clk_tbl_usb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) { 60000000, P_PLL8, 1, 5, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) static struct clk_rcg usb_hs1_xcvr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .ns_reg = 0x290C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .md_reg = 0x2908,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .parent_map = gcc_pxo_pll8_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .enable_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .name = "usb_hs1_xcvr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .parent_names = gcc_pxo_pll8_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static struct clk_branch usb_hs1_xcvr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .enable_reg = 0x290c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .name = "usb_hs1_xcvr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) static struct clk_branch usb_hs1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .hwcg_reg = 0x2900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .halt_reg = 0x2fc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .enable_reg = 0x2900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .name = "usb_hs1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static struct clk_rcg usb_fs1_xcvr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .ns_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .md_reg = 0x2964,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .mn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .parent_map = gcc_pxo_pll8_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .freq_tbl = clk_tbl_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .enable_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .enable_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .name = "usb_fs1_xcvr_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .parent_names = gcc_pxo_pll8_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .ops = &clk_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static struct clk_branch usb_fs1_xcvr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .halt_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .enable_reg = 0x2968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .enable_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .name = "usb_fs1_xcvr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static struct clk_branch usb_fs1_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .halt_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .enable_reg = 0x296c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .name = "usb_fs1_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static struct clk_branch usb_fs1_h_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .halt_bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .enable_reg = 0x2960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .name = "usb_fs1_h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) static struct clk_branch ebi2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .hwcg_reg = 0x3b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .halt_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .enable_reg = 0x3b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .name = "ebi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) static struct clk_branch ebi2_aon_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .halt_reg = 0x2fcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .halt_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .enable_reg = 0x3b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .name = "ebi2_always_on_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static const struct freq_tbl clk_tbl_gmac[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) { 133000000, P_PLL0, 1, 50, 301 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) { 266000000, P_PLL0, 1, 127, 382 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) static struct clk_dyn_rcg gmac_core1_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .ns_reg[0] = 0x3cac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .ns_reg[1] = 0x3cb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .md_reg[0] = 0x3ca4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .md_reg[1] = 0x3ca8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .bank_reg = 0x3ca0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .mux_sel_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .freq_tbl = clk_tbl_gmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .enable_reg = 0x3ca0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .name = "gmac_core1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static struct clk_branch gmac_core1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .halt_reg = 0x3c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .halt_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .hwcg_reg = 0x3cb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .enable_reg = 0x3cb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .name = "gmac_core1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) "gmac_core1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) static struct clk_dyn_rcg gmac_core2_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .ns_reg[0] = 0x3ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .ns_reg[1] = 0x3cd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .md_reg[0] = 0x3cc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .md_reg[1] = 0x3cc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .bank_reg = 0x3ca0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .mux_sel_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .freq_tbl = clk_tbl_gmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .enable_reg = 0x3cc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .name = "gmac_core2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static struct clk_branch gmac_core2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .halt_reg = 0x3c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .halt_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .hwcg_reg = 0x3cd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .enable_reg = 0x3cd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .name = "gmac_core2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) "gmac_core2_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) static struct clk_dyn_rcg gmac_core3_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .ns_reg[0] = 0x3cec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .ns_reg[1] = 0x3cf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .md_reg[0] = 0x3ce4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .md_reg[1] = 0x3ce8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .bank_reg = 0x3ce0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .mux_sel_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .freq_tbl = clk_tbl_gmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .enable_reg = 0x3ce0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .name = "gmac_core3_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static struct clk_branch gmac_core3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .halt_reg = 0x3c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .halt_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .hwcg_reg = 0x3cf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .enable_reg = 0x3cf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .name = "gmac_core3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) "gmac_core3_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static struct clk_dyn_rcg gmac_core4_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .ns_reg[0] = 0x3d0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .ns_reg[1] = 0x3d10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .md_reg[0] = 0x3d04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .md_reg[1] = 0x3d08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .bank_reg = 0x3d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .mux_sel_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .freq_tbl = clk_tbl_gmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .enable_reg = 0x3d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .name = "gmac_core4_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static struct clk_branch gmac_core4_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .halt_reg = 0x3c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .halt_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .hwcg_reg = 0x3d14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .hwcg_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .enable_reg = 0x3d14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .name = "gmac_core4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) "gmac_core4_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static const struct freq_tbl clk_tbl_nss_tcm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) { 266000000, P_PLL0, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) { 400000000, P_PLL0, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static struct clk_dyn_rcg nss_tcm_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .ns_reg[0] = 0x3dc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .ns_reg[1] = 0x3dc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .bank_reg = 0x3dc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .pre_div_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .mux_sel_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .freq_tbl = clk_tbl_nss_tcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .enable_reg = 0x3dc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .name = "nss_tcm_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) static struct clk_branch nss_tcm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .halt_reg = 0x3c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .halt_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .enable_reg = 0x3dd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .enable_mask = BIT(6) | BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .name = "nss_tcm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) "nss_tcm_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .ops = &clk_branch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const struct freq_tbl clk_tbl_nss[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) { 110000000, P_PLL18, 1, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) { 275000000, P_PLL18, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) { 550000000, P_PLL18, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) { 733000000, P_PLL18, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static struct clk_dyn_rcg ubi32_core1_src_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .ns_reg[0] = 0x3d2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .ns_reg[1] = 0x3d30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .md_reg[0] = 0x3d24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .md_reg[1] = 0x3d28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .bank_reg = 0x3d20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .mux_sel_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .freq_tbl = clk_tbl_nss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .enable_reg = 0x3d20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .name = "ubi32_core1_src_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static struct clk_dyn_rcg ubi32_core2_src_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .ns_reg[0] = 0x3d4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .ns_reg[1] = 0x3d50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .md_reg[0] = 0x3d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .md_reg[1] = 0x3d48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .bank_reg = 0x3d40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .mn[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .mn[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .mnctr_en_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .mnctr_reset_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .mnctr_mode_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .n_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .m_val_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .s[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .s[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .src_sel_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .p[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .p[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .pre_div_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .pre_div_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .mux_sel_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .freq_tbl = clk_tbl_nss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .enable_reg = 0x3d40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .name = "ubi32_core2_src_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .ops = &clk_dyn_rcg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) static struct clk_regmap *gcc_ipq806x_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) [PLL0] = &pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) [PLL0_VOTE] = &pll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) [PLL3] = &pll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) [PLL4_VOTE] = &pll4_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) [PLL8] = &pll8.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) [PLL8_VOTE] = &pll8_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) [PLL14] = &pll14.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) [PLL14_VOTE] = &pll14_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) [PLL18] = &pll18.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) [GP0_SRC] = &gp0_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) [GP0_CLK] = &gp0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) [GP1_SRC] = &gp1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) [GP1_CLK] = &gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) [GP2_SRC] = &gp2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) [GP2_CLK] = &gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) [PMEM_A_CLK] = &pmem_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) [PRNG_SRC] = &prng_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) [PRNG_CLK] = &prng_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) [SDC1_SRC] = &sdc1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [SDC1_CLK] = &sdc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [SDC3_SRC] = &sdc3_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) [SDC3_CLK] = &sdc3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) [TSIF_REF_SRC] = &tsif_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) [TSIF_H_CLK] = &tsif_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) [SDC1_H_CLK] = &sdc1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) [SDC3_H_CLK] = &sdc3_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) [ADM0_CLK] = &adm0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) [PCIE_A_CLK] = &pcie_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) [PCIE_H_CLK] = &pcie_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) [SATA_H_CLK] = &sata_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) [SATA_CLK_SRC] = &sata_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) [SATA_A_CLK] = &sata_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) [EBI2_CLK] = &ebi2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) [NSSTCM_CLK] = &nss_tcm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) [PLL9] = &hfpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) [PLL10] = &hfpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) [PLL12] = &hfpll_l2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) static const struct qcom_reset_map gcc_ipq806x_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) [QDSS_STM_RESET] = { 0x2060, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) [ADM0_C2_RESET] = { 0x220c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) [ADM0_C1_RESET] = { 0x220c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) [ADM0_C0_RESET] = { 0x220c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) [ADM0_PBUS_RESET] = { 0x220c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) [ADM0_RESET] = { 0x220c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) [QDSS_POR_RESET] = { 0x2260, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) [QDSS_TSCTR_RESET] = { 0x2260, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) [QDSS_HRESET_RESET] = { 0x2260, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) [QDSS_AXI_RESET] = { 0x2260, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) [QDSS_DBG_RESET] = { 0x2260, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) [PCIE_EXT_RESET] = { 0x22dc, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) [PCIE_PHY_RESET] = { 0x22dc, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) [PCIE_PCI_RESET] = { 0x22dc, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) [PCIE_POR_RESET] = { 0x22dc, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) [PCIE_HCLK_RESET] = { 0x22dc, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) [PCIE_ACLK_RESET] = { 0x22dc, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) [SFAB_LPASS_RESET] = { 0x23a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) [SFAB_SATA_S_RESET] = { 0x2480, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) [DFAB_SWAY0_RESET] = { 0x2540, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) [DFAB_SWAY1_RESET] = { 0x2544, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) [DFAB_ARB0_RESET] = { 0x2560, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) [DFAB_ARB1_RESET] = { 0x2564, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) [PPSS_PROC_RESET] = { 0x2594, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) [PPSS_RESET] = { 0x2594, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) [DMA_BAM_RESET] = { 0x25c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) [SPS_TIC_H_RESET] = { 0x2600, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) [TSIF_H_RESET] = { 0x2700, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) [CE1_H_RESET] = { 0x2720, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) [CE1_CORE_RESET] = { 0x2724, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) [CE1_SLEEP_RESET] = { 0x2728, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) [CE2_H_RESET] = { 0x2740, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) [CE2_CORE_RESET] = { 0x2744, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) [RPM_PROC_RESET] = { 0x27c0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) [PMIC_SSBI2_RESET] = { 0x280c, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) [SDC1_RESET] = { 0x2830, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) [SDC2_RESET] = { 0x2850, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) [SDC3_RESET] = { 0x2870, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) [SDC4_RESET] = { 0x2890, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) [USB_HS1_RESET] = { 0x2910, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) [USB_HSIC_RESET] = { 0x2934, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) [USB_FS1_RESET] = { 0x2974, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) [GSBI1_RESET] = { 0x29dc, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) [GSBI2_RESET] = { 0x29fc, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) [GSBI3_RESET] = { 0x2a1c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) [GSBI4_RESET] = { 0x2a3c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) [GSBI5_RESET] = { 0x2a5c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) [GSBI6_RESET] = { 0x2a7c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) [GSBI7_RESET] = { 0x2a9c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) [SPDM_RESET] = { 0x2b6c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) [SEC_CTRL_RESET] = { 0x2b80, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) [TLMM_H_RESET] = { 0x2ba0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) [SATA_RESET] = { 0x2c1c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) [TSSC_RESET] = { 0x2ca0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) [PDM_RESET] = { 0x2cc0, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) [MPM_H_RESET] = { 0x2da0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) [MPM_RESET] = { 0x2da4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) [PRNG_RESET] = { 0x2e80, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) [CE3_SLEEP_RESET] = { 0x36d0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) [PCIE_1_M_RESET] = { 0x3a98, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) [PCIE_1_S_RESET] = { 0x3a98, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) [PCIE_2_M_RESET] = { 0x3ad8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) [PCIE_2_S_RESET] = { 0x3ad8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) [PCIE_2_POR_RESET] = { 0x3adc, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) [USB30_0_PHY_RESET] = { 0x3b50, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) [USB30_1_PHY_RESET] = { 0x3b58, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) [NSSFB0_RESET] = { 0x3b60, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) [NSSFB1_RESET] = { 0x3b60, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) [GMAC_AHB_RESET] = { 0x3e24, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) static const struct regmap_config gcc_ipq806x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) .max_register = 0x3e40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) static const struct qcom_cc_desc gcc_ipq806x_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .config = &gcc_ipq806x_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .clks = gcc_ipq806x_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .resets = gcc_ipq806x_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) static const struct of_device_id gcc_ipq806x_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) { .compatible = "qcom,gcc-ipq8064" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) static int gcc_ipq806x_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) regmap = dev_get_regmap(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) if (!regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /* Setup PLL18 static bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) regmap_write(regmap, 0x31b0, 0x3080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) /* Set GMAC footswitch sleep/wakeup values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) regmap_write(regmap, 0x3cb8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) regmap_write(regmap, 0x3cd8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) regmap_write(regmap, 0x3cf8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) regmap_write(regmap, 0x3d18, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) static struct platform_driver gcc_ipq806x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .probe = gcc_ipq806x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) .name = "gcc-ipq806x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .of_match_table = gcc_ipq806x_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) static int __init gcc_ipq806x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) return platform_driver_register(&gcc_ipq806x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) core_initcall(gcc_ipq806x_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static void __exit gcc_ipq806x_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) platform_driver_unregister(&gcc_ipq806x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) module_exit(gcc_ipq806x_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) MODULE_ALIAS("platform:gcc-ipq806x");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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