^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "clk-regmap-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_BIAS_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_UNIPHY0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_UNIPHY0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_UNIPHY1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_BIAS_PLL_NSS_NOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_UNIPHY1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_PCIE20_PHY0_PIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_USB3PHY_0_PIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_GPLL0_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) P_GPLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) P_GPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) P_GPLL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) P_UBI32_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) P_NSS_CRYPTO_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) P_PI_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct clk_alpha_pll gpll0_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .offset = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "gpll0_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct clk_fixed_factor gpll0_out_main_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .name = "gpll0_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &gpll0_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct clk_alpha_pll_postdiv gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .offset = 0x21000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) &gpll0_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .hw = &gpll0.clkr.hw},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .hw = &gpll0_out_main_div2.hw},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct clk_alpha_pll ubi32_pll_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .offset = 0x25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = SUPPORTS_DYNAMIC_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .enable_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "ubi32_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .ops = &clk_alpha_pll_huayra_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct clk_alpha_pll_postdiv ubi32_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .offset = 0x25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "ubi32_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) &ubi32_pll_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clk_alpha_pll gpll6_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .offset = 0x37000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .enable_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = "gpll6_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct clk_alpha_pll_postdiv gpll6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .offset = 0x37000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "gpll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &gpll6_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct clk_alpha_pll gpll4_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .offset = 0x24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "gpll4_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct clk_alpha_pll_postdiv gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .offset = 0x24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &gpll4_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .cmd_rcgr = 0x27000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "pcnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct clk_alpha_pll gpll2_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .offset = 0x4a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "gpll2_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct clk_alpha_pll_postdiv gpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .offset = 0x4a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "gpll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) &gpll2_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct clk_alpha_pll nss_crypto_pll_main = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .offset = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .enable_reg = 0x0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "nss_crypto_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .ops = &clk_alpha_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct clk_alpha_pll_postdiv nss_crypto_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .offset = 0x22000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "nss_crypto_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) &nss_crypto_pll_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .ops = &clk_alpha_pll_postdiv_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) F(320000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) F(600000000, P_GPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { P_GPLL4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { P_GPLL6, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct clk_rcg2 qdss_tsctr_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .cmd_rcgr = 0x29064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .freq_tbl = ftbl_qdss_tsctr_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "qdss_tsctr_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct clk_fixed_factor qdss_dap_sync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "qdss_dap_sync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) &qdss_tsctr_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) F(66670000, P_GPLL0_DIV2, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) F(240000000, P_GPLL4, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct clk_rcg2 qdss_at_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .cmd_rcgr = 0x2900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .freq_tbl = ftbl_qdss_at_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "qdss_at_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "qdss_tsctr_div2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) &qdss_tsctr_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) F(300000000, P_BIAS_PLL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { .fw_name = "bias_pll_cc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { .hw = &nss_crypto_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .hw = &ubi32_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { P_BIAS_PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { P_GPLL4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { P_NSS_CRYPTO_PLL, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct clk_rcg2 nss_ppe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .cmd_rcgr = 0x68080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .freq_tbl = ftbl_nss_ppe_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .name = "nss_ppe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct clk_branch gcc_xo_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .halt_reg = 0x30018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .enable_reg = 0x30018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .name = "gcc_xo_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct clk_parent_data gcc_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct parent_map gcc_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct clk_rcg2 nss_ce_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .cmd_rcgr = 0x68098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .freq_tbl = ftbl_nss_ce_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = "nss_ce_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct clk_branch gcc_sleep_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .halt_reg = 0x30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .enable_reg = 0x30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .name = "gcc_sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .fw_name = "sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) F(50000000, P_GPLL0_DIV2, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) F(133333333, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) F(266666667, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct clk_parent_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { P_GPLL0_DIV2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .cmd_rcgr = 0x76054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .name = "snoc_nssnoc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) F(25000000, P_GPLL0_DIV2, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct clk_rcg2 apss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .cmd_rcgr = 0x46000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .freq_tbl = ftbl_apss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .name = "apss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) F(25000000, P_UNIPHY0_RX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) F(78125000, P_UNIPHY1_RX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) F(125000000, P_UNIPHY0_RX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) F(156250000, P_UNIPHY1_RX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) F(312500000, P_UNIPHY1_RX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct clk_parent_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .fw_name = "uniphy0_gcc_rx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .fw_name = "uniphy0_gcc_tx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .fw_name = "uniphy1_gcc_rx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { .fw_name = "uniphy1_gcc_tx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .hw = &ubi32_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { .fw_name = "bias_pll_cc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct parent_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { P_UNIPHY0_RX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { P_UNIPHY0_TX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { P_UNIPHY1_RX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { P_UNIPHY1_TX, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct clk_rcg2 nss_port5_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .cmd_rcgr = 0x68060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .freq_tbl = ftbl_nss_port5_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "nss_port5_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) F(25000000, P_UNIPHY0_TX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) F(78125000, P_UNIPHY1_TX, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) F(125000000, P_UNIPHY0_TX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) F(156250000, P_UNIPHY1_TX, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) F(312500000, P_UNIPHY1_TX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct clk_parent_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { .fw_name = "uniphy0_gcc_tx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { .fw_name = "uniphy0_gcc_rx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { .fw_name = "uniphy1_gcc_tx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { .fw_name = "uniphy1_gcc_rx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { .hw = &ubi32_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { .fw_name = "bias_pll_cc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct parent_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { P_UNIPHY0_TX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { P_UNIPHY0_RX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { P_UNIPHY1_TX, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { P_UNIPHY1_RX, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static struct clk_rcg2 nss_port5_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .cmd_rcgr = 0x68068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .freq_tbl = ftbl_nss_port5_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "nss_port5_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .num_parents = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) F(240000000, P_GPLL4, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { P_GPLL4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static struct clk_rcg2 pcie0_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .cmd_rcgr = 0x75054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .freq_tbl = ftbl_pcie_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .parent_map = gcc_xo_gpll0_gpll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "pcie0_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .parent_data = gcc_xo_gpll0_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) F(80000000, P_GPLL0_DIV2, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) F(133330000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { P_GPLL0_DIV2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct clk_rcg2 usb0_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .cmd_rcgr = 0x3e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .freq_tbl = ftbl_usb0_master_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .name = "usb0_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .reg = 0x46018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .name = "apss_ahb_postdiv_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &apss_ahb_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static struct clk_fixed_factor gcc_xo_div4_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "gcc_xo_div4_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) &gcc_xo_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) F(25000000, P_UNIPHY0_RX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) F(125000000, P_UNIPHY0_RX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { .fw_name = "uniphy0_gcc_rx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { .fw_name = "uniphy0_gcc_tx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { .hw = &ubi32_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { .fw_name = "bias_pll_cc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { P_UNIPHY0_RX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { P_UNIPHY0_TX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct clk_rcg2 nss_port1_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .cmd_rcgr = 0x68020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .name = "nss_port1_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) F(25000000, P_UNIPHY0_TX, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) F(125000000, P_UNIPHY0_TX, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) { .fw_name = "uniphy0_gcc_tx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { .fw_name = "uniphy0_gcc_rx_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { .hw = &ubi32_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) { .fw_name = "bias_pll_cc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) { P_UNIPHY0_TX, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) { P_UNIPHY0_RX, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) { P_UBI32_PLL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) { P_BIAS_PLL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static struct clk_rcg2 nss_port1_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .cmd_rcgr = 0x68028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .name = "nss_port1_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static struct clk_rcg2 nss_port2_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .cmd_rcgr = 0x68030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .name = "nss_port2_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static struct clk_rcg2 nss_port2_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .cmd_rcgr = 0x68038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .name = "nss_port2_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static struct clk_rcg2 nss_port3_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .cmd_rcgr = 0x68040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .name = "nss_port3_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static struct clk_rcg2 nss_port3_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .cmd_rcgr = 0x68048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .name = "nss_port3_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct clk_rcg2 nss_port4_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .cmd_rcgr = 0x68050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .freq_tbl = ftbl_nss_port1_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .name = "nss_port4_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static struct clk_rcg2 nss_port4_tx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .cmd_rcgr = 0x68058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .freq_tbl = ftbl_nss_port1_tx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .name = "nss_port4_tx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct clk_regmap_div nss_port5_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .reg = 0x68440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .name = "nss_port5_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &nss_port5_rx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static struct clk_regmap_div nss_port5_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .reg = 0x68444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .name = "nss_port5_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &nss_port5_tx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) F(100000000, P_GPLL0_DIV2, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) F(308570000, P_GPLL6, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) F(533000000, P_GPLL0, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) { .hw = &ubi32_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const struct parent_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) { P_UBI32_PLL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { P_GPLL0_DIV2, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static struct clk_rcg2 apss_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .cmd_rcgr = 0x38048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .freq_tbl = ftbl_apss_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .name = "apss_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { .hw = &nss_crypto_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { P_NSS_CRYPTO_PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static struct clk_rcg2 nss_crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .cmd_rcgr = 0x68144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .freq_tbl = ftbl_nss_crypto_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .name = "nss_crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .parent_data = gcc_xo_nss_crypto_pll_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static struct clk_regmap_div nss_port1_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .reg = 0x68400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .name = "nss_port1_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) &nss_port1_rx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static struct clk_regmap_div nss_port1_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .reg = 0x68404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .name = "nss_port1_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) &nss_port1_tx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static struct clk_regmap_div nss_port2_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .reg = 0x68410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .name = "nss_port2_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) &nss_port2_rx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static struct clk_regmap_div nss_port2_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .reg = 0x68414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .name = "nss_port2_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) &nss_port2_tx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static struct clk_regmap_div nss_port3_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .reg = 0x68420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .name = "nss_port3_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) &nss_port3_rx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static struct clk_regmap_div nss_port3_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .reg = 0x68424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .name = "nss_port3_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) &nss_port3_tx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static struct clk_regmap_div nss_port4_rx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .reg = 0x68430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .name = "nss_port4_rx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) &nss_port4_rx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static struct clk_regmap_div nss_port4_tx_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .reg = 0x68434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .name = "nss_port4_tx_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) &nss_port4_tx_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) F(149760000, P_UBI32_PLL, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) F(187200000, P_UBI32_PLL, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) F(249600000, P_UBI32_PLL, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) F(374400000, P_UBI32_PLL, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) F(748800000, P_UBI32_PLL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) F(1497600000, P_UBI32_PLL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static const struct clk_parent_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) { .hw = &ubi32_pll.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) { .hw = &gpll2.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) { P_UBI32_PLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) { P_GPLL2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) { P_GPLL4, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) { P_GPLL6, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static struct clk_rcg2 nss_ubi0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .cmd_rcgr = 0x68104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .freq_tbl = ftbl_nss_ubi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .name = "nss_ubi0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static struct clk_rcg2 adss_pwm_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .cmd_rcgr = 0x1c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .freq_tbl = ftbl_adss_pwm_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .name = "adss_pwm_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) F(25000000, P_GPLL0_DIV2, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .cmd_rcgr = 0x0200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) F(960000, P_XO, 10, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) F(4800000, P_XO, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) F(9600000, P_XO, 2, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) F(12500000, P_GPLL0_DIV2, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) F(16000000, P_GPLL0, 10, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .cmd_rcgr = 0x02024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .cmd_rcgr = 0x03000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .cmd_rcgr = 0x03014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .cmd_rcgr = 0x04000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .cmd_rcgr = 0x04014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .cmd_rcgr = 0x05000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .cmd_rcgr = 0x05014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .cmd_rcgr = 0x06000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .cmd_rcgr = 0x06014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .cmd_rcgr = 0x07000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .cmd_rcgr = 0x07014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) F(16000000, P_GPLL0_DIV2, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) F(24000000, P_GPLL0, 1, 3, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) F(25000000, P_GPLL0, 16, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) F(32000000, P_GPLL0, 1, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) F(40000000, P_GPLL0, 1, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) F(46400000, P_GPLL0, 1, 29, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) F(48000000, P_GPLL0, 1, 3, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) F(51200000, P_GPLL0, 1, 8, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) F(56000000, P_GPLL0, 1, 7, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) F(58982400, P_GPLL0, 1, 1152, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) F(60000000, P_GPLL0, 1, 3, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) F(64000000, P_GPLL0, 12.5, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .cmd_rcgr = 0x02044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .cmd_rcgr = 0x03034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .cmd_rcgr = 0x04034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .name = "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .cmd_rcgr = 0x05034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .name = "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .cmd_rcgr = 0x06034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .name = "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .cmd_rcgr = 0x07034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .name = "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static const struct freq_tbl ftbl_crypto_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) F(40000000, P_GPLL0_DIV2, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) F(80000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static struct clk_rcg2 crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .cmd_rcgr = 0x16004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .freq_tbl = ftbl_crypto_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .name = "crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static const struct freq_tbl ftbl_gp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) F(50000000, P_GPLL0_DIV2, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) F(266666666, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) { .fw_name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) { P_SLEEP_CLK, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .cmd_rcgr = 0x08004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .freq_tbl = ftbl_gp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .cmd_rcgr = 0x09004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .freq_tbl = ftbl_gp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .cmd_rcgr = 0x0a004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .freq_tbl = ftbl_gp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .name = "nss_ppe_cdiv_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static struct clk_regmap_div nss_ubi0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .reg = 0x68118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .name = "nss_ubi0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) &nss_ubi0_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) { .fw_name = "sleep_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) { P_PI_SLEEP, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static struct clk_rcg2 pcie0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .cmd_rcgr = 0x75024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .freq_tbl = ftbl_pcie_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .name = "pcie0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) { .fw_name = "pcie20_phy0_pipe_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) { P_PCIE20_PHY0_PIPE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) { P_XO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static struct clk_regmap_mux pcie0_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .reg = 0x7501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .name = "pcie0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) F(144000, P_XO, 16, 12, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) F(400000, P_XO, 12, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) F(24000000, P_GPLL2, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) F(48000000, P_GPLL2, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) F(96000000, P_GPLL2, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) F(177777778, P_GPLL0, 4.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) F(192000000, P_GPLL2, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) F(384000000, P_GPLL2, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static const struct clk_parent_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) { .hw = &gpll2.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) { P_GPLL2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .cmd_rcgr = 0x42004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .freq_tbl = ftbl_sdcc_apps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static struct clk_rcg2 usb0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .cmd_rcgr = 0x3e05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .freq_tbl = ftbl_usb_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .name = "usb0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) F(60000000, P_GPLL6, 6, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static const struct clk_parent_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) { P_GPLL6, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) { P_GPLL0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static struct clk_rcg2 usb0_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .cmd_rcgr = 0x3e020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .freq_tbl = ftbl_usb_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .name = "usb0_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) { .fw_name = "usb3phy_0_cc_pipe_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) { P_USB3PHY_0_PIPE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) { P_XO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static struct clk_regmap_mux usb0_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .reg = 0x3e048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .name = "usb0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .ops = &clk_regmap_mux_closest_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) F(80000000, P_GPLL0_DIV2, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) F(216000000, P_GPLL6, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) F(308570000, P_GPLL6, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) { .fw_name = "xo"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) { P_GPLL6, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static struct clk_rcg2 sdcc1_ice_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .cmd_rcgr = 0x5d000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .freq_tbl = ftbl_sdcc_ice_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .name = "sdcc1_ice_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) F(50000000, P_GPLL0_DIV2, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static struct clk_rcg2 qdss_stm_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .cmd_rcgr = 0x2902C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .freq_tbl = ftbl_qdss_stm_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .name = "qdss_stm_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) F(80000000, P_GPLL0_DIV2, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) F(300000000, P_GPLL4, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) { .hw = &gpll0_out_main_div2.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) { P_GPLL4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) { P_GPLL0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) { P_GPLL0_DIV2, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static struct clk_rcg2 qdss_traceclkin_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .cmd_rcgr = 0x29048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .freq_tbl = ftbl_qdss_traceclkin_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .name = "qdss_traceclkin_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static struct clk_rcg2 usb1_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .cmd_rcgr = 0x3f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .freq_tbl = ftbl_usb_mock_utmi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .name = "usb1_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static struct clk_branch gcc_adss_pwm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .halt_reg = 0x1c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .enable_reg = 0x1c020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .name = "gcc_adss_pwm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) &adss_pwm_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static struct clk_branch gcc_apss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .halt_reg = 0x4601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .name = "gcc_apss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) &apss_ahb_postdiv_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) F(50000000, P_GPLL0_DIV2, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) F(133333333, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) F(160000000, P_GPLL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) F(200000000, P_GPLL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) F(266666667, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static struct clk_rcg2 system_noc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .cmd_rcgr = 0x26004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .name = "system_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) F(533333333, P_GPLL0, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) static const struct clk_parent_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) { .hw = &gpll2.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) { .fw_name = "bias_pll_nss_noc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) { P_GPLL2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) { P_BIAS_PLL_NSS_NOC, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .cmd_rcgr = 0x68088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .name = "ubi32_mem_noc_bfdcd_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static struct clk_branch gcc_apss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .halt_reg = 0x46020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .name = "gcc_apss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) &apss_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .halt_reg = 0x01008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .halt_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .enable_reg = 0x02008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .halt_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .enable_reg = 0x02004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) &blsp1_qup1_spi_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .halt_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .enable_reg = 0x03010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .halt_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .enable_reg = 0x0300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) &blsp1_qup2_spi_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .halt_reg = 0x04010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .enable_reg = 0x04010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .halt_reg = 0x0400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .enable_reg = 0x0400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) &blsp1_qup3_spi_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .halt_reg = 0x05010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .enable_reg = 0x05010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .halt_reg = 0x0500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .enable_reg = 0x0500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) &blsp1_qup4_spi_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .halt_reg = 0x06010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .enable_reg = 0x06010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .halt_reg = 0x0600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .enable_reg = 0x0600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) &blsp1_qup5_spi_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .halt_reg = 0x0700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .enable_reg = 0x0700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) &blsp1_qup6_spi_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .halt_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .enable_reg = 0x0203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) &blsp1_uart1_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .halt_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .enable_reg = 0x0302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) &blsp1_uart2_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static struct clk_branch gcc_blsp1_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .halt_reg = 0x0402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .enable_reg = 0x0402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .name = "gcc_blsp1_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) &blsp1_uart3_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static struct clk_branch gcc_blsp1_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .halt_reg = 0x0502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .enable_reg = 0x0502c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .name = "gcc_blsp1_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) &blsp1_uart4_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static struct clk_branch gcc_blsp1_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .halt_reg = 0x0602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .enable_reg = 0x0602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .name = "gcc_blsp1_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) &blsp1_uart5_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static struct clk_branch gcc_blsp1_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .halt_reg = 0x0702c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .enable_reg = 0x0702c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .name = "gcc_blsp1_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) &blsp1_uart6_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static struct clk_branch gcc_crypto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .halt_reg = 0x16024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .name = "gcc_crypto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static struct clk_branch gcc_crypto_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .halt_reg = 0x16020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .name = "gcc_crypto_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) static struct clk_branch gcc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .halt_reg = 0x1601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .name = "gcc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) &crypto_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) static struct clk_fixed_factor gpll6_out_main_div2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .name = "gpll6_out_main_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) &gpll6_main.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .ops = &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static struct clk_branch gcc_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .halt_reg = 0x30030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .enable_reg = 0x30030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .name = "gcc_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) &gcc_xo_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .halt_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .enable_reg = 0x08000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) &gp1_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .halt_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .enable_reg = 0x09000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) &gp2_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .halt_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .enable_reg = 0x0a000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) &gp3_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) static struct clk_branch gcc_mdio_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .halt_reg = 0x58004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .enable_reg = 0x58004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .name = "gcc_mdio_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) static struct clk_branch gcc_crypto_ppe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .halt_reg = 0x68310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .enable_reg = 0x68310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .name = "gcc_crypto_ppe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static struct clk_branch gcc_nss_ce_apb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .halt_reg = 0x68174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .enable_reg = 0x68174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .name = "gcc_nss_ce_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) &nss_ce_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static struct clk_branch gcc_nss_ce_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .halt_reg = 0x68170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .enable_reg = 0x68170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .name = "gcc_nss_ce_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) &nss_ce_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static struct clk_branch gcc_nss_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .halt_reg = 0x68160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .enable_reg = 0x68160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .name = "gcc_nss_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static struct clk_branch gcc_nss_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .halt_reg = 0x68164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .enable_reg = 0x68164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .name = "gcc_nss_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) &nss_crypto_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static struct clk_branch gcc_nss_csr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .halt_reg = 0x68318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .enable_reg = 0x68318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .name = "gcc_nss_csr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) &nss_ce_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) static struct clk_branch gcc_nss_edma_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .halt_reg = 0x6819C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .enable_reg = 0x6819C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .name = "gcc_nss_edma_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) static struct clk_branch gcc_nss_edma_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .halt_reg = 0x68198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .enable_reg = 0x68198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .name = "gcc_nss_edma_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static struct clk_branch gcc_nss_noc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .halt_reg = 0x68168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .enable_reg = 0x68168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .name = "gcc_nss_noc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) static struct clk_branch gcc_ubi0_utcm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .halt_reg = 0x2606c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .enable_reg = 0x2606c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .name = "gcc_ubi0_utcm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static struct clk_branch gcc_snoc_nssnoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .halt_reg = 0x26070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .enable_reg = 0x26070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .name = "gcc_snoc_nssnoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) F(133333333, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static struct clk_rcg2 wcss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .cmd_rcgr = 0x59020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .freq_tbl = ftbl_wcss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .name = "wcss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) { .fw_name = "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) { .hw = &gpll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) { .hw = &gpll2.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) { .hw = &gpll4.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) { .hw = &gpll6.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) { P_GPLL2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) { P_GPLL4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) { P_GPLL6, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) static struct clk_rcg2 q6_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .cmd_rcgr = 0x59120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .freq_tbl = ftbl_q6_axi_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .name = "q6_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) F(100000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) static struct clk_rcg2 lpass_core_axim_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .cmd_rcgr = 0x1F020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .freq_tbl = ftbl_lpass_core_axim_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .name = "lpass_core_axim_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) F(266666667, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) static struct clk_rcg2 lpass_snoc_cfg_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .cmd_rcgr = 0x1F040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .freq_tbl = ftbl_lpass_snoc_cfg_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .name = "lpass_snoc_cfg_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) F(400000000, P_GPLL0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) static struct clk_rcg2 lpass_q6_axim_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .cmd_rcgr = 0x1F008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .freq_tbl = ftbl_lpass_q6_axim_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .name = "lpass_q6_axim_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) F(24000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) F(50000000, P_GPLL0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static struct clk_rcg2 rbcpr_wcss_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .cmd_rcgr = 0x3a00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .freq_tbl = ftbl_rbcpr_wcss_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .name = "rbcpr_wcss_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) static struct clk_branch gcc_lpass_core_axim_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .halt_reg = 0x1F028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .enable_reg = 0x1F028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .name = "gcc_lpass_core_axim_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) &lpass_core_axim_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) static struct clk_branch gcc_lpass_snoc_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .halt_reg = 0x1F048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .enable_reg = 0x1F048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .name = "gcc_lpass_snoc_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) &lpass_snoc_cfg_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) static struct clk_branch gcc_lpass_q6_axim_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .halt_reg = 0x1F010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .enable_reg = 0x1F010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .name = "gcc_lpass_q6_axim_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) &lpass_q6_axim_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static struct clk_branch gcc_lpass_q6_atbm_at_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .halt_reg = 0x1F018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .enable_reg = 0x1F018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .name = "gcc_lpass_q6_atbm_at_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) &qdss_at_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) static struct clk_branch gcc_lpass_q6_pclkdbg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .halt_reg = 0x1F01C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .enable_reg = 0x1F01C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .name = "gcc_lpass_q6_pclkdbg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) &qdss_dap_sync_clk_src.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .halt_reg = 0x1F014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .enable_reg = 0x1F014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .name = "gcc_lpass_q6ss_tsctr_1to2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) &qdss_tsctr_div2_clk_src.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) static struct clk_branch gcc_lpass_q6ss_trig_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .halt_reg = 0x1F038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .enable_reg = 0x1F038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .name = "gcc_lpass_q6ss_trig_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) &qdss_dap_sync_clk_src.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) static struct clk_branch gcc_lpass_tbu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .halt_reg = 0x12094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .enable_reg = 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .name = "gcc_lpass_tbu_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) &lpass_q6_axim_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static struct clk_branch gcc_pcnoc_lpass_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .halt_reg = 0x27020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .enable_reg = 0x27020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .name = "gcc_pcnoc_lpass_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) &lpass_core_axim_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static struct clk_branch gcc_mem_noc_lpass_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .halt_reg = 0x1D044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .enable_reg = 0x1D044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .name = "gcc_mem_noc_lpass_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) &lpass_q6_axim_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static struct clk_branch gcc_snoc_lpass_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .halt_reg = 0x26074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .enable_reg = 0x26074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .name = "gcc_snoc_lpass_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) &lpass_snoc_cfg_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) static struct clk_branch gcc_mem_noc_ubi32_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .halt_reg = 0x1D03C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .enable_reg = 0x1D03C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .name = "gcc_mem_noc_ubi32_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) &ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) static struct clk_branch gcc_nss_port1_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .halt_reg = 0x68240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .enable_reg = 0x68240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .name = "gcc_nss_port1_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) &nss_port1_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) static struct clk_branch gcc_nss_port1_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .halt_reg = 0x68244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .enable_reg = 0x68244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .name = "gcc_nss_port1_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) &nss_port1_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) static struct clk_branch gcc_nss_port2_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .halt_reg = 0x68248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .enable_reg = 0x68248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .name = "gcc_nss_port2_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) &nss_port2_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) static struct clk_branch gcc_nss_port2_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .halt_reg = 0x6824c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .enable_reg = 0x6824c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .name = "gcc_nss_port2_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) &nss_port2_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static struct clk_branch gcc_nss_port3_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .halt_reg = 0x68250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .enable_reg = 0x68250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .name = "gcc_nss_port3_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) &nss_port3_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static struct clk_branch gcc_nss_port3_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .halt_reg = 0x68254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .enable_reg = 0x68254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .name = "gcc_nss_port3_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) &nss_port3_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) static struct clk_branch gcc_nss_port4_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .halt_reg = 0x68258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .enable_reg = 0x68258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .name = "gcc_nss_port4_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) &nss_port4_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) static struct clk_branch gcc_nss_port4_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .halt_reg = 0x6825c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .enable_reg = 0x6825c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .name = "gcc_nss_port4_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) &nss_port4_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) static struct clk_branch gcc_nss_port5_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .halt_reg = 0x68260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .enable_reg = 0x68260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .name = "gcc_nss_port5_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) &nss_port5_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) static struct clk_branch gcc_nss_port5_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .halt_reg = 0x68264,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .enable_reg = 0x68264,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .name = "gcc_nss_port5_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) &nss_port5_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) static struct clk_branch gcc_nss_ppe_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .halt_reg = 0x68194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .enable_reg = 0x68194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .name = "gcc_nss_ppe_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) static struct clk_branch gcc_nss_ppe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .halt_reg = 0x68190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .enable_reg = 0x68190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .name = "gcc_nss_ppe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) static struct clk_branch gcc_nss_ppe_ipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) .halt_reg = 0x68338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .enable_reg = 0x68338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .name = "gcc_nss_ppe_ipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) static struct clk_branch gcc_nss_ptp_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) .halt_reg = 0x6816C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) .enable_reg = 0x6816C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .name = "gcc_nss_ptp_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) &nss_ppe_cdiv_clk_src.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static struct clk_branch gcc_nssnoc_ce_apb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .halt_reg = 0x6830C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) .enable_reg = 0x6830C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) .name = "gcc_nssnoc_ce_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) &nss_ce_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) static struct clk_branch gcc_nssnoc_ce_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) .halt_reg = 0x68308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) .enable_reg = 0x68308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) .name = "gcc_nssnoc_ce_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) &nss_ce_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static struct clk_branch gcc_nssnoc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .halt_reg = 0x68314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .enable_reg = 0x68314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .name = "gcc_nssnoc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) &nss_crypto_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .halt_reg = 0x68304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .enable_reg = 0x68304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) .name = "gcc_nssnoc_ppe_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) static struct clk_branch gcc_nssnoc_ppe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) .halt_reg = 0x68300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .enable_reg = 0x68300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) .name = "gcc_nssnoc_ppe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .halt_reg = 0x68180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .enable_reg = 0x68180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) .name = "gcc_nssnoc_qosgen_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) &gcc_xo_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) static struct clk_branch gcc_nssnoc_snoc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .halt_reg = 0x68188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .enable_reg = 0x68188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .name = "gcc_nssnoc_snoc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) &system_noc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) .halt_reg = 0x68184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) .enable_reg = 0x68184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) .name = "gcc_nssnoc_timeout_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) &gcc_xo_div4_clk_src.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) .halt_reg = 0x68270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) .enable_reg = 0x68270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) .name = "gcc_nssnoc_ubi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) &nss_ce_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) static struct clk_branch gcc_port1_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) .halt_reg = 0x68320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) .enable_reg = 0x68320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) .name = "gcc_port1_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) static struct clk_branch gcc_port2_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) .halt_reg = 0x68324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) .enable_reg = 0x68324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) .name = "gcc_port2_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) static struct clk_branch gcc_port3_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .halt_reg = 0x68328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) .enable_reg = 0x68328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) .name = "gcc_port3_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) static struct clk_branch gcc_port4_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) .halt_reg = 0x6832c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .enable_reg = 0x6832c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) .name = "gcc_port4_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) static struct clk_branch gcc_port5_mac_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) .halt_reg = 0x68330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) .enable_reg = 0x68330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) .name = "gcc_port5_mac_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) &nss_ppe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) static struct clk_branch gcc_ubi0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .halt_reg = 0x6820C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .enable_reg = 0x6820C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) .name = "gcc_ubi0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) &nss_ce_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) static struct clk_branch gcc_ubi0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) .halt_reg = 0x68200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) .enable_reg = 0x68200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) .name = "gcc_ubi0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) &ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) static struct clk_branch gcc_ubi0_nc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .halt_reg = 0x68204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) .enable_reg = 0x68204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) .name = "gcc_ubi0_nc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) static struct clk_branch gcc_ubi0_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) .halt_reg = 0x68210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) .enable_reg = 0x68210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) .name = "gcc_ubi0_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) &nss_ubi0_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) static struct clk_branch gcc_pcie0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) .halt_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) .enable_reg = 0x75010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) .name = "gcc_pcie0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) static struct clk_branch gcc_pcie0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) .halt_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) .enable_reg = 0x75014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) .name = "gcc_pcie0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) &pcie0_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) static struct clk_branch gcc_pcie0_axi_m_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) .halt_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) .enable_reg = 0x75008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) .name = "gcc_pcie0_axi_m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) &pcie0_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) static struct clk_branch gcc_pcie0_axi_s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) .halt_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) .enable_reg = 0x7500c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) .name = "gcc_pcie0_axi_s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) &pcie0_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) .halt_reg = 0x26048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) .enable_reg = 0x26048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) .name = "gcc_sys_noc_pcie0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) &pcie0_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) static struct clk_branch gcc_pcie0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) .halt_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) .enable_reg = 0x75018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) .name = "gcc_pcie0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) &pcie0_pipe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) .halt_reg = 0x13004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) .enable_reg = 0x0b004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) static struct clk_branch gcc_qdss_dap_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) .halt_reg = 0x29084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) .enable_reg = 0x29084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) .name = "gcc_qdss_dap_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) &qdss_dap_sync_clk_src.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) static struct clk_branch gcc_qpic_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) .halt_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) .enable_reg = 0x57024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) .name = "gcc_qpic_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) static struct clk_branch gcc_qpic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) .halt_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) .enable_reg = 0x57020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) .name = "gcc_qpic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) .halt_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) .enable_reg = 0x4201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) .halt_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) .enable_reg = 0x42018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) &sdcc1_apps_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) static struct clk_branch gcc_uniphy0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) .halt_reg = 0x56008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) .enable_reg = 0x56008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) .name = "gcc_uniphy0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) static struct clk_branch gcc_uniphy0_port1_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) .halt_reg = 0x56010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) .enable_reg = 0x56010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) .name = "gcc_uniphy0_port1_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) &nss_port1_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) static struct clk_branch gcc_uniphy0_port1_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) .halt_reg = 0x56014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) .enable_reg = 0x56014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) .name = "gcc_uniphy0_port1_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) &nss_port1_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) static struct clk_branch gcc_uniphy0_port2_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) .halt_reg = 0x56018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) .enable_reg = 0x56018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) .name = "gcc_uniphy0_port2_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) &nss_port2_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) static struct clk_branch gcc_uniphy0_port2_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) .halt_reg = 0x5601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) .enable_reg = 0x5601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) .name = "gcc_uniphy0_port2_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) &nss_port2_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) static struct clk_branch gcc_uniphy0_port3_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) .halt_reg = 0x56020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) .enable_reg = 0x56020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) .name = "gcc_uniphy0_port3_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) &nss_port3_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) static struct clk_branch gcc_uniphy0_port3_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) .halt_reg = 0x56024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) .enable_reg = 0x56024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) .name = "gcc_uniphy0_port3_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) &nss_port3_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) static struct clk_branch gcc_uniphy0_port4_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) .halt_reg = 0x56028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) .enable_reg = 0x56028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) .name = "gcc_uniphy0_port4_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) &nss_port4_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) static struct clk_branch gcc_uniphy0_port4_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) .halt_reg = 0x5602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) .enable_reg = 0x5602c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) .name = "gcc_uniphy0_port4_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) &nss_port4_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) static struct clk_branch gcc_uniphy0_port5_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) .halt_reg = 0x56030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) .enable_reg = 0x56030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) .name = "gcc_uniphy0_port5_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) &nss_port5_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) static struct clk_branch gcc_uniphy0_port5_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) .halt_reg = 0x56034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) .enable_reg = 0x56034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) .name = "gcc_uniphy0_port5_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) &nss_port5_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) static struct clk_branch gcc_uniphy0_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) .halt_reg = 0x5600C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) .enable_reg = 0x5600C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) .name = "gcc_uniphy0_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) &gcc_xo_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) static struct clk_branch gcc_uniphy1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) .halt_reg = 0x56108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) .enable_reg = 0x56108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) .name = "gcc_uniphy1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) static struct clk_branch gcc_uniphy1_port5_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) .halt_reg = 0x56110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) .enable_reg = 0x56110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) .name = "gcc_uniphy1_port5_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) &nss_port5_rx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) static struct clk_branch gcc_uniphy1_port5_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) .halt_reg = 0x56114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) .enable_reg = 0x56114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) .name = "gcc_uniphy1_port5_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) &nss_port5_tx_div_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) static struct clk_branch gcc_uniphy1_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) .halt_reg = 0x5610C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) .enable_reg = 0x5610C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) .name = "gcc_uniphy1_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) &gcc_xo_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) static struct clk_branch gcc_usb0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) .halt_reg = 0x3e044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) .enable_reg = 0x3e044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) .name = "gcc_usb0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) &usb0_aux_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) static struct clk_branch gcc_usb0_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) .halt_reg = 0x3e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) .enable_reg = 0x3e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) .name = "gcc_usb0_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) &usb0_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) .halt_reg = 0x47014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) .enable_reg = 0x47014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) .name = "gcc_snoc_bus_timeout2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) &usb0_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) static struct clk_rcg2 pcie0_rchng_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) .cmd_rcgr = 0x75070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) .freq_tbl = ftbl_pcie_rchng_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) .name = "pcie0_rchng_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) .parent_data = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) static struct clk_branch gcc_pcie0_rchng_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) .halt_reg = 0x75070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) .enable_reg = 0x75070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) .name = "gcc_pcie0_rchng_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) &pcie0_rchng_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) .halt_reg = 0x75048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) .enable_reg = 0x75048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) .name = "gcc_pcie0_axi_s_bridge_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) &pcie0_axi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) .halt_reg = 0x26040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) .enable_reg = 0x26040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) .name = "gcc_sys_noc_usb0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) &usb0_master_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) static struct clk_branch gcc_usb0_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) .halt_reg = 0x3e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) .enable_reg = 0x3e008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) .name = "gcc_usb0_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) &usb0_mock_utmi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) .halt_reg = 0x3e080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) .enable_reg = 0x3e080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) .name = "gcc_usb0_phy_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) static struct clk_branch gcc_usb0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) .halt_reg = 0x3e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) .halt_check = BRANCH_HALT_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) .enable_reg = 0x3e040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) .name = "gcc_usb0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) &usb0_pipe_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) static struct clk_branch gcc_usb0_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) .halt_reg = 0x3e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) .enable_reg = 0x3e004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) .name = "gcc_usb0_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) &gcc_sleep_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) static struct clk_branch gcc_usb1_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) .halt_reg = 0x3f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) .enable_reg = 0x3f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) .name = "gcc_usb1_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) static struct clk_branch gcc_usb1_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) .halt_reg = 0x3f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) .enable_reg = 0x3f008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) .name = "gcc_usb1_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) &usb1_mock_utmi_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) .halt_reg = 0x3f080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) .enable_reg = 0x3f080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) .name = "gcc_usb1_phy_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) static struct clk_branch gcc_usb1_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) .halt_reg = 0x3f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) .enable_reg = 0x3f004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) .name = "gcc_usb1_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) &gcc_sleep_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) .halt_reg = 0x56308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) .enable_reg = 0x56308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) .name = "gcc_cmn_12gpll_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) static struct clk_branch gcc_cmn_12gpll_sys_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) .halt_reg = 0x5630c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) .enable_reg = 0x5630c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) .name = "gcc_cmn_12gpll_sys_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) &gcc_xo_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) static struct clk_branch gcc_sdcc1_ice_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) .halt_reg = 0x5d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) .enable_reg = 0x5d014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) .name = "gcc_sdcc1_ice_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) &sdcc1_ice_core_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) static struct clk_branch gcc_dcc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) .halt_reg = 0x77004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) .enable_reg = 0x77004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) .name = "gcc_dcc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) .parent_hws = (const struct clk_hw *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) &pcnoc_bfdcd_clk_src.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) static const struct alpha_pll_config ubi32_pll_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) .l = 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) .alpha = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) .config_ctl_val = 0x240d6aa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) .config_ctl_hi_val = 0x3c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) .aux_output_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) .pre_div_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) .post_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) .post_div_mask = GENMASK(9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) static const struct alpha_pll_config nss_crypto_pll_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) .l = 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) .alpha = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) .alpha_hi = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) .config_ctl_val = 0x4001055b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) .pre_div_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) .pre_div_mask = GENMASK(14, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) .post_div_val = 0x1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) .post_div_mask = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) .vco_mask = GENMASK(21, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) .vco_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) .alpha_en_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) static struct clk_hw *gcc_ipq6018_hws[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) &gpll0_out_main_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) &gcc_xo_div4_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) &nss_ppe_cdiv_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) &gpll6_out_main_div2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) &qdss_dap_sync_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) &qdss_tsctr_div2_clk_src.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) static struct clk_regmap *gcc_ipq6018_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) [GPLL0_MAIN] = &gpll0_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) [UBI32_PLL] = &ubi32_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) [GPLL6_MAIN] = &gpll6_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) [GPLL6] = &gpll6.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) [GPLL4_MAIN] = &gpll4_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) [GPLL2_MAIN] = &gpll2_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) [GPLL2] = &gpll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) [SNOC_NSSNOC_BFDCD_CLK_SRC] = &snoc_nssnoc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) [UBI32_MEM_NOC_BFDCD_CLK_SRC] = &ubi32_mem_noc_bfdcd_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) [APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) [GCC_XO_CLK] = &gcc_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) [PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) [RBCPR_WCSS_CLK_SRC] = &rbcpr_wcss_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) [LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) [GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) [LPASS_SNOC_CFG_CLK_SRC] = &lpass_snoc_cfg_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) [GCC_LPASS_Q6_AXIM_CLK] = &gcc_lpass_q6_axim_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) [LPASS_Q6_AXIM_CLK_SRC] = &lpass_q6_axim_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) [GCC_LPASS_Q6_ATBM_AT_CLK] = &gcc_lpass_q6_atbm_at_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) [GCC_LPASS_Q6_PCLKDBG_CLK] = &gcc_lpass_q6_pclkdbg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) [GCC_LPASS_Q6SS_TSCTR_1TO2_CLK] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) [GCC_LPASS_Q6SS_TRIG_CLK] = &gcc_lpass_q6ss_trig_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) [GCC_LPASS_TBU_CLK] = &gcc_lpass_tbu_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) [GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) [GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) static const struct qcom_reset_map gcc_ipq6018_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) [GCC_BLSP1_BCR] = { 0x01000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) [GCC_IMEM_BCR] = { 0x0e000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) [GCC_SMMU_BCR] = { 0x12000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) [GCC_PRNG_BCR] = { 0x13000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) [GCC_CRYPTO_BCR] = { 0x16000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) [GCC_WCSS_BCR] = { 0x18000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) [GCC_NSS_BCR] = { 0x19000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) [GCC_ADSS_BCR] = { 0x1c000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) [GCC_DDRSS_BCR] = { 0x1e000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) [GCC_PCNOC_BCR] = { 0x27018, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) [GCC_TCSR_BCR] = { 0x28000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) [GCC_QDSS_BCR] = { 0x29000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) [GCC_DCD_BCR] = { 0x2a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) [GCC_MPM_BCR] = { 0x2c000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) [GCC_SPDM_BCR] = { 0x2f000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) [GCC_RBCPR_BCR] = { 0x33000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) [GCC_TLMM_BCR] = { 0x34000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) [GCC_USB0_BCR] = { 0x3e070, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) [GCC_USB1_BCR] = { 0x3f070, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) [GCC_SDCC1_BCR] = { 0x42000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) [GCC_QPIC_BCR] = { 0x57018, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) [GCC_MDIO_BCR] = { 0x58000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) [GCC_PCIE0_BCR] = { 0x75004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) [GCC_DCC_BCR] = { 0x77000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) [GCC_PPE_FULL_RESET] = { 0x68014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) [GCC_EDMA_HW_RESET] = { 0x68014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) [GCC_NSSPORT1_RESET] = { 0x68014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) [GCC_NSSPORT2_RESET] = { 0x68014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) [GCC_NSSPORT3_RESET] = { 0x68014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) [GCC_NSSPORT4_RESET] = { 0x68014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) [GCC_NSSPORT5_RESET] = { 0x68014, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) [GCC_LPASS_BCR] = {0x1F000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) [GCC_UBI32_TBU_BCR] = {0x65000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) [GCC_WCSSAON_RESET] = {0x59010, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) [GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) [GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) [GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) [GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) [GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) [GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) [GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) [GCC_WCSS_DBG_ARES] = {0x59008, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) [GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) [GCC_WCSS_ACMT_ARES] = {0x59008, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) [GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) [GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) [GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) [GCC_Q6SS_DBG_ARES] = {0x59110, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) [GCC_Q6_AHB_S_ARES] = {0x59110, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) [GCC_Q6_AHB_ARES] = {0x59110, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) [GCC_Q6_AXIM2_ARES] = {0x59110, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) [GCC_Q6_AXIM_ARES] = {0x59110, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) static const struct of_device_id gcc_ipq6018_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) { .compatible = "qcom,gcc-ipq6018" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) MODULE_DEVICE_TABLE(of, gcc_ipq6018_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) static const struct regmap_config gcc_ipq6018_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) .max_register = 0x7fffc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) static const struct qcom_cc_desc gcc_ipq6018_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) .config = &gcc_ipq6018_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) .clks = gcc_ipq6018_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) .num_clks = ARRAY_SIZE(gcc_ipq6018_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) .resets = gcc_ipq6018_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) .num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) .clk_hws = gcc_ipq6018_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) .num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) static int gcc_ipq6018_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) regmap = qcom_cc_map(pdev, &gcc_ipq6018_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) /* Disable SW_COLLAPSE for USB0 GDSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) /* Enable SW_OVERRIDE for USB0 GDSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) /* Disable SW_COLLAPSE for USB1 GDSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) /* Enable SW_OVERRIDE for USB1 GDSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) /* SW Workaround for UBI Huyara PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) &nss_crypto_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) static struct platform_driver gcc_ipq6018_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) .probe = gcc_ipq6018_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) .name = "qcom,gcc-ipq6018",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) .of_match_table = gcc_ipq6018_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) static int __init gcc_ipq6018_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) return platform_driver_register(&gcc_ipq6018_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) core_initcall(gcc_ipq6018_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) static void __exit gcc_ipq6018_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) platform_driver_unregister(&gcc_ipq6018_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) module_exit(gcc_ipq6018_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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