^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define to_clk_regmap_div(_hw) container_of(to_clk_regmap(_hw),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk_regmap_div, clkr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define to_clk_fepll(_hw) container_of(to_clk_regmap_div(_hw),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_fepll, cdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_FEPLL200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_FEPLL500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_DDRPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_FEPLLWCSS2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_FEPLLWCSS5G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) P_FEPLL125DLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) P_DDRPLLAPSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @fdbkdiv_shift: lowest bit for FDBKDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @fdbkdiv_width: number of bits in FDBKDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @refclkdiv_shift: lowest bit for REFCLKDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @refclkdiv_width: number of bits in REFCLKDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @reg: PLL_DIV register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk_fepll_vco {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 fdbkdiv_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 fdbkdiv_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 refclkdiv_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 refclkdiv_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * struct clk_fepll - clk divider corresponds to FEPLL clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @fixed_div: fixed divider value if divider is fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @parent_map: map from software's parent index to hardware's src_sel field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @cdiv: divider values for PLL_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @pll_vco: vco feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @div_table: mapping for actual divider value to register divider value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * in case of non fixed divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @freq_tbl: frequency table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk_fepll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const u8 *parent_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk_regmap_div cdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct clk_fepll_vco *pll_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const struct freq_tbl *freq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct parent_map gcc_xo_200_500_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { P_FEPLL200, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { P_FEPLL500, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const gcc_xo_200_500[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "fepll500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct parent_map gcc_xo_200_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { P_FEPLL200, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char * const gcc_xo_200[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct parent_map gcc_xo_200_spi_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { P_FEPLL200, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char * const gcc_xo_200_spi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct parent_map gcc_xo_sdcc1_500_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { P_DDRPLL, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { P_FEPLL500, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const gcc_xo_sdcc1_500[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "ddrpllsdcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "fepll500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct parent_map gcc_xo_wcss2g_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { P_FEPLLWCSS2G, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const char * const gcc_xo_wcss2g[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "fepllwcss2g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct parent_map gcc_xo_wcss5g_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { P_FEPLLWCSS5G, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const char * const gcc_xo_wcss5g[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "fepllwcss5g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct parent_map gcc_xo_125_dly_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { P_FEPLL125DLY, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char * const gcc_xo_125_dly[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "fepll125dly",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct parent_map gcc_xo_ddr_500_200_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { P_FEPLL200, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { P_FEPLL500, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { P_DDRPLLAPSS, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Contains index for safe clock during APSS freq change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * fepll500 is being used as safe clock so initialize it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * with its index in parents list gcc_xo_ddr_500_200.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const int gcc_ipq4019_cpu_safe_parent = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const char * const gcc_xo_ddr_500_200[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "fepll500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "ddrpllapss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) F(200000000, P_FEPLL200, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct clk_rcg2 audio_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .cmd_rcgr = 0x1b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .parent_map = gcc_xo_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .freq_tbl = ftbl_gcc_audio_pwm_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "audio_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .parent_names = gcc_xo_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct clk_branch gcc_audio_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .halt_reg = 0x1b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .enable_reg = 0x1b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "gcc_audio_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct clk_branch gcc_audio_pwm_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .halt_reg = 0x1b00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .enable_reg = 0x1b00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "gcc_audio_pwm_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "audio_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) F(19050000, P_FEPLL200, 10.5, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .cmd_rcgr = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .parent_map = gcc_xo_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .parent_names = gcc_xo_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .halt_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .enable_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .cmd_rcgr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .parent_map = gcc_xo_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .parent_names = gcc_xo_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .halt_reg = 0x3010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .enable_reg = 0x3010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) F(960000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) F(4800000, P_XO, 1, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) F(9600000, P_XO, 1, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) F(15000000, P_XO, 1, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) F(19200000, P_XO, 1, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) F(24000000, P_XO, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .cmd_rcgr = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .parent_map = gcc_xo_200_spi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .parent_names = gcc_xo_200_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .halt_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .enable_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .cmd_rcgr = 0x3014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .parent_map = gcc_xo_200_spi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .parent_names = gcc_xo_200_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .halt_reg = 0x300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .enable_reg = 0x300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) F(1843200, P_FEPLL200, 1, 144, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) F(3686400, P_FEPLL200, 1, 288, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) F(7372800, P_FEPLL200, 1, 576, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) F(14745600, P_FEPLL200, 1, 1152, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) F(16000000, P_FEPLL200, 1, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) F(24000000, P_XO, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) F(32000000, P_FEPLL200, 1, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) F(40000000, P_FEPLL200, 1, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) F(46400000, P_FEPLL200, 1, 29, 125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .cmd_rcgr = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .parent_map = gcc_xo_200_spi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .parent_names = gcc_xo_200_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .halt_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .enable_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .cmd_rcgr = 0x3034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .parent_map = gcc_xo_200_spi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .parent_names = gcc_xo_200_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .halt_reg = 0x302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .enable_reg = 0x302c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct freq_tbl ftbl_gcc_gp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) F(1250000, P_FEPLL200, 1, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) F(2500000, P_FEPLL200, 1, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) F(5000000, P_FEPLL200, 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .cmd_rcgr = 0x8004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .parent_map = gcc_xo_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .parent_names = gcc_xo_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .halt_reg = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .enable_reg = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .cmd_rcgr = 0x9004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .parent_map = gcc_xo_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .parent_names = gcc_xo_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .halt_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .enable_reg = 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .cmd_rcgr = 0xa004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .parent_map = gcc_xo_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .parent_names = gcc_xo_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .halt_reg = 0xa000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .enable_reg = 0xa000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) F(144000, P_XO, 1, 3, 240),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) F(400000, P_XO, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) F(20000000, P_FEPLL500, 1, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) F(25000000, P_FEPLL500, 1, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) F(50000000, P_FEPLL500, 1, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) F(100000000, P_FEPLL500, 1, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) F(192000000, P_DDRPLL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .cmd_rcgr = 0x18004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .parent_map = gcc_xo_sdcc1_500_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .parent_names = gcc_xo_sdcc1_500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct freq_tbl ftbl_gcc_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) F(200000000, P_FEPLL200, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) F(384000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) F(413000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) F(448000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) F(488000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) F(500000000, P_FEPLL500, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) F(512000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) F(537000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) F(565000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) F(597000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) F(632000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) F(672000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) F(716000000, P_DDRPLLAPSS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static struct clk_rcg2 apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .cmd_rcgr = 0x1900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .freq_tbl = ftbl_gcc_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .parent_map = gcc_xo_ddr_500_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .parent_names = gcc_xo_ddr_500_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) F(100000000, P_FEPLL200, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct clk_rcg2 apps_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .cmd_rcgr = 0x19014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .parent_map = gcc_xo_200_500_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .freq_tbl = ftbl_gcc_apps_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "apps_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .parent_names = gcc_xo_200_500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static struct clk_branch gcc_apss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .halt_reg = 0x19004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .enable_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .name = "gcc_apss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "apps_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .halt_reg = 0x1008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct clk_branch gcc_dcd_xo_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .halt_reg = 0x2103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .enable_reg = 0x2103c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = "gcc_dcd_xo_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .halt_reg = 0x1300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .enable_reg = 0x1300c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static struct clk_branch gcc_crypto_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .halt_reg = 0x16024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .name = "gcc_crypto_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct clk_branch gcc_crypto_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .halt_reg = 0x16020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .name = "gcc_crypto_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "fepll125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static struct clk_branch gcc_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .halt_reg = 0x1601c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = "gcc_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) "fepll125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static struct clk_branch gcc_ess_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .halt_reg = 0x12010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .enable_reg = 0x12010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .name = "gcc_ess_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "fephy_125m_dly_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct clk_branch gcc_imem_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .halt_reg = 0xe004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .name = "gcc_imem_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static struct clk_branch gcc_imem_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .halt_reg = 0xe008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .enable_reg = 0xe008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .name = "gcc_imem_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static struct clk_branch gcc_pcie_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .halt_reg = 0x1d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .enable_reg = 0x1d00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .name = "gcc_pcie_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static struct clk_branch gcc_pcie_axi_m_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .halt_reg = 0x1d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .enable_reg = 0x1d004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .name = "gcc_pcie_axi_m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct clk_branch gcc_pcie_axi_s_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .halt_reg = 0x1d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .enable_reg = 0x1d008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .name = "gcc_pcie_axi_s_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .halt_reg = 0x13004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .enable_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static struct clk_branch gcc_qpic_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .halt_reg = 0x1c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .enable_reg = 0x1c008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .name = "gcc_qpic_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct clk_branch gcc_qpic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .halt_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .enable_reg = 0x1c004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "gcc_qpic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .halt_reg = 0x18010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .enable_reg = 0x18010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .halt_reg = 0x1800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .enable_reg = 0x1800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static struct clk_branch gcc_tlmm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .halt_reg = 0x5004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .enable_reg = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .name = "gcc_tlmm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static struct clk_branch gcc_usb2_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .halt_reg = 0x1e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .enable_reg = 0x1e00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .name = "gcc_usb2_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static struct clk_branch gcc_usb2_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .halt_reg = 0x1e010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .enable_reg = 0x1e010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .name = "gcc_usb2_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "gcc_sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static struct clk_branch gcc_usb2_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .halt_reg = 0x1e014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .enable_reg = 0x1e014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .name = "gcc_usb2_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) F(2000000, P_FEPLL200, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static struct clk_rcg2 usb30_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .cmd_rcgr = 0x1e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .parent_map = gcc_xo_200_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .name = "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .parent_names = gcc_xo_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static struct clk_branch gcc_usb3_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .halt_reg = 0x1e028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .enable_reg = 0x1e028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .name = "gcc_usb3_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "fepll125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static struct clk_branch gcc_usb3_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .halt_reg = 0x1e02C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .enable_reg = 0x1e02C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .name = "gcc_usb3_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) "gcc_sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static struct clk_branch gcc_usb3_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .halt_reg = 0x1e030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .enable_reg = 0x1e030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .name = "gcc_usb3_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) F(125000000, P_FEPLL125DLY, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static struct clk_rcg2 fephy_125m_dly_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .cmd_rcgr = 0x12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .parent_map = gcc_xo_125_dly_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .freq_tbl = ftbl_gcc_fephy_dly_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .name = "fephy_125m_dly_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .parent_names = gcc_xo_125_dly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static struct clk_rcg2 wcss2g_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .cmd_rcgr = 0x1f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .freq_tbl = ftbl_gcc_wcss2g_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .parent_map = gcc_xo_wcss2g_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .name = "wcss2g_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .parent_names = gcc_xo_wcss2g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct clk_branch gcc_wcss2g_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .halt_reg = 0x1f00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .enable_reg = 0x1f00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .name = "gcc_wcss2g_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) "wcss2g_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static struct clk_branch gcc_wcss2g_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .halt_reg = 0x1f00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .enable_reg = 0x1f00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .name = "gcc_wcss2g_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static struct clk_branch gcc_wcss2g_rtc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .halt_reg = 0x1f010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .enable_reg = 0x1f010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .name = "gcc_wcss2g_rtc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) "gcc_sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static struct clk_rcg2 wcss5g_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .cmd_rcgr = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .parent_map = gcc_xo_wcss5g_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .freq_tbl = ftbl_gcc_wcss5g_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .name = "wcss5g_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .parent_names = gcc_xo_wcss5g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static struct clk_branch gcc_wcss5g_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .halt_reg = 0x2000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .enable_reg = 0x2000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .name = "gcc_wcss5g_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) "wcss5g_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static struct clk_branch gcc_wcss5g_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .halt_reg = 0x2000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .enable_reg = 0x2000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .name = "gcc_wcss5g_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static struct clk_branch gcc_wcss5g_rtc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .halt_reg = 0x20010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .enable_reg = 0x20010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .name = "gcc_wcss5g_rtc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) "gcc_sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Calculates the VCO rate for FEPLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static u64 clk_fepll_vco_calc_rate(struct clk_fepll *pll_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) const struct clk_fepll_vco *pll_vco = pll_div->pll_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u32 fdbkdiv, refclkdiv, cdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u64 vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) (BIT(pll_vco->refclkdiv_width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) (BIT(pll_vco->fdbkdiv_width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) vco = parent_rate / refclkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) vco *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) vco *= fdbkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static const struct clk_fepll_vco gcc_apss_ddrpll_vco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .fdbkdiv_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .fdbkdiv_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .refclkdiv_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .refclkdiv_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .reg = 0x2e020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static const struct clk_fepll_vco gcc_fepll_vco = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .fdbkdiv_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .fdbkdiv_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .refclkdiv_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .refclkdiv_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .reg = 0x2f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * Round rate function for APSS CPU PLL Clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * It looks up the frequency table and returns the next higher frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * supported in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) unsigned long *p_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct clk_fepll *pll = to_clk_fepll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct clk_hw *p_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) const struct freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) f = qcom_find_freq(pll->freq_tbl, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) p_hw = clk_hw_get_parent_by_index(hw, f->src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) *p_rate = clk_hw_get_rate(p_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return f->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * Clock set rate function for APSS CPU PLL Clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * It looks up the frequency table and updates the PLL divider to corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * divider value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct clk_fepll *pll = to_clk_fepll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) const struct freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) f = qcom_find_freq(pll->freq_tbl, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = regmap_update_bits(pll->cdiv.clkr.regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) pll->cdiv.reg, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) f->pre_div << pll->cdiv.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * There is no status bit which can be checked for successful CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * divider update operation so using delay for the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * Clock frequency calculation function for APSS CPU PLL Clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * This clock divider is nonlinear so this function calculates the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * divider and returns the output frequency by dividing VCO Frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * with this actual divider value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) clk_cpu_div_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct clk_fepll *pll = to_clk_fepll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 cdiv, pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * Some dividers have value in 0.5 fraction so multiply both VCO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * frequency(parent_rate) and pre_div with 2 to make integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (cdiv > 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) pre_div = (cdiv + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pre_div = cdiv + 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) do_div(rate, pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const struct clk_ops clk_regmap_cpu_div_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .round_rate = clk_cpu_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .set_rate = clk_cpu_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .recalc_rate = clk_cpu_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const struct freq_tbl ftbl_apss_ddr_pll[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) { 384000000, P_XO, 0xd, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { 413000000, P_XO, 0xc, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { 448000000, P_XO, 0xb, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { 488000000, P_XO, 0xa, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { 512000000, P_XO, 0x9, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { 537000000, P_XO, 0x8, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) { 565000000, P_XO, 0x7, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) { 597000000, P_XO, 0x6, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) { 632000000, P_XO, 0x5, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) { 672000000, P_XO, 0x4, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) { 716000000, P_XO, 0x3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) { 768000000, P_XO, 0x2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) { 823000000, P_XO, 0x1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) { 896000000, P_XO, 0x0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static struct clk_fepll gcc_apss_cpu_plldiv_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .cdiv.reg = 0x2e020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .cdiv.shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .cdiv.width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .enable_reg = 0x2e000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .name = "ddrpllapss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .ops = &clk_regmap_cpu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .freq_tbl = ftbl_apss_ddr_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .pll_vco = &gcc_apss_ddrpll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* Calculates the rate for PLL divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * If the divider value is not fixed then it gets the actual divider value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * from divider table. Then, it calculate the clock rate by dividing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * parent rate with actual divider value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) clk_regmap_clk_div_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct clk_fepll *pll = to_clk_fepll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) u32 cdiv, pre_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) const struct clk_div_table *clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (pll->fixed_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) pre_div = pll->fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) for (clkt = pll->div_table; clkt->div; clkt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (clkt->val == cdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) pre_div = clkt->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) rate = clk_fepll_vco_calc_rate(pll, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) do_div(rate, pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static const struct clk_ops clk_fepll_div_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .recalc_rate = clk_regmap_clk_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static struct clk_fepll gcc_apss_sdcc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .fixed_div = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .name = "ddrpllsdcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .ops = &clk_fepll_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .pll_vco = &gcc_apss_ddrpll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static struct clk_fepll gcc_fepll125_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .fixed_div = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .name = "fepll125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .ops = &clk_fepll_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .pll_vco = &gcc_fepll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static struct clk_fepll gcc_fepll125dly_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .fixed_div = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .name = "fepll125dly",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .ops = &clk_fepll_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .pll_vco = &gcc_fepll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static struct clk_fepll gcc_fepll200_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .fixed_div = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .name = "fepll200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .ops = &clk_fepll_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .pll_vco = &gcc_fepll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static struct clk_fepll gcc_fepll500_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .fixed_div = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .name = "fepll500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .ops = &clk_fepll_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .pll_vco = &gcc_fepll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const struct clk_div_table fepllwcss_clk_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) { 0, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) { 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) { 2, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) { 3, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static struct clk_fepll gcc_fepllwcss2g_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .cdiv.reg = 0x2f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .cdiv.shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .cdiv.width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .name = "fepllwcss2g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .ops = &clk_fepll_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .div_table = fepllwcss_clk_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .pll_vco = &gcc_fepll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static struct clk_fepll gcc_fepllwcss5g_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .cdiv.reg = 0x2f020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .cdiv.shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .cdiv.width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .cdiv.clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .name = "fepllwcss5g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .ops = &clk_fepll_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .div_table = fepllwcss_clk_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .pll_vco = &gcc_fepll_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) F(48000000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) F(100000000, P_FEPLL200, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .cmd_rcgr = 0x21024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .parent_map = gcc_xo_200_500_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .freq_tbl = ftbl_gcc_pcnoc_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .name = "gcc_pcnoc_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .parent_names = gcc_xo_200_500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static struct clk_branch pcnoc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .halt_reg = 0x21030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .enable_reg = 0x21030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .name = "pcnoc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) "gcc_pcnoc_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .flags = CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static struct clk_regmap *gcc_ipq4019_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) [AUDIO_CLK_SRC] = &audio_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) [GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) [GCC_APPS_CLK_SRC] = &apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) [GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) [FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) [WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) [WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) [GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) [GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) [GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) [GCC_ESS_CLK] = &gcc_ess_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) [GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) [GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) [GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) [GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) [GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) [GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) [GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) [GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) [GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) [GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) [GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) [GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) [GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) [GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) [GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) [GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) [GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) [GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) [GCC_SDCC_PLLDIV_CLK] = &gcc_apss_sdcc_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) [GCC_FEPLL125_CLK] = &gcc_fepll125_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) [GCC_FEPLL125DLY_CLK] = &gcc_fepll125dly_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) [GCC_FEPLL200_CLK] = &gcc_fepll200_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) [GCC_FEPLL500_CLK] = &gcc_fepll500_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) [GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) [GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) [GCC_APSS_CPU_PLLDIV_CLK] = &gcc_apss_cpu_plldiv_clk.cdiv.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) [GCC_PCNOC_AHB_CLK_SRC] = &gcc_pcnoc_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) [GCC_PCNOC_AHB_CLK] = &pcnoc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const struct qcom_reset_map gcc_ipq4019_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) [PCIE_AHB_ARES] = { 0x1d010, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) [PCIE_PWR_ARES] = { 0x1d010, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) [PCIE_PHY_ARES] = { 0x1d010, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) [PCIE_PIPE_ARES] = { 0x1d010, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) [ESS_RESET] = { 0x12008, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) [GCC_BLSP1_BCR] = {0x01000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) [GCC_BIMC_BCR] = {0x04000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) [GCC_TLMM_BCR] = {0x05000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) [GCC_IMEM_BCR] = {0x0E000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) [GCC_ESS_BCR] = {0x12008, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) [GCC_PRNG_BCR] = {0x13000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) [GCC_BOOT_ROM_BCR] = {0x13008, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) [GCC_CRYPTO_BCR] = {0x16000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) [GCC_SDCC1_BCR] = {0x18000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) [GCC_AUDIO_BCR] = {0x1B008, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) [GCC_QPIC_BCR] = {0x1C000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) [GCC_PCIE_BCR] = {0x1D000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) [GCC_USB2_BCR] = {0x1E008, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) [GCC_USB2_PHY_BCR] = {0x1E018, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) [GCC_USB3_BCR] = {0x1E024, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) [GCC_USB3_PHY_BCR] = {0x1E034, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) [GCC_PCNOC_BCR] = {0x2102C, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) [GCC_DCD_BCR] = {0x21038, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) [GCC_TCSR_BCR] = {0x22000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) [GCC_MPM_BCR] = {0x24000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) [GCC_SPDM_BCR] = {0x25000, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static const struct regmap_config gcc_ipq4019_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .max_register = 0x2ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const struct qcom_cc_desc gcc_ipq4019_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .config = &gcc_ipq4019_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .clks = gcc_ipq4019_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .resets = gcc_ipq4019_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static const struct of_device_id gcc_ipq4019_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) { .compatible = "qcom,gcc-ipq4019" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) gcc_ipq4019_cpu_clk_notifier_fn(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (action == PRE_RATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) err = clk_rcg2_ops.set_parent(&apps_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) gcc_ipq4019_cpu_safe_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return notifier_from_errno(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static struct notifier_block gcc_ipq4019_cpu_clk_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .notifier_call = gcc_ipq4019_cpu_clk_notifier_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static int gcc_ipq4019_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) err = qcom_cc_probe(pdev, &gcc_ipq4019_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return clk_notifier_register(apps_clk_src.clkr.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) &gcc_ipq4019_cpu_clk_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static int gcc_ipq4019_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return clk_notifier_unregister(apps_clk_src.clkr.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) &gcc_ipq4019_cpu_clk_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static struct platform_driver gcc_ipq4019_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .probe = gcc_ipq4019_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .remove = gcc_ipq4019_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .name = "qcom,gcc-ipq4019",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .of_match_table = gcc_ipq4019_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static int __init gcc_ipq4019_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return platform_driver_register(&gcc_ipq4019_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) core_initcall(gcc_ipq4019_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static void __exit gcc_ipq4019_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) platform_driver_unregister(&gcc_ipq4019_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) module_exit(gcc_ipq4019_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) MODULE_ALIAS("platform:gcc-ipq4019");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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