^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,gcc-apq8084.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/qcom,gcc-apq8084.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_XO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_PCIE_0_1_PIPE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_SATA_ASIC0_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_SATA_RX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct parent_map gcc_xo_gpll0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { P_GPLL0, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char * const gcc_xo_gpll0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { P_GPLL0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { P_GPLL4, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char * const gcc_xo_gpll0_gpll4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "gpll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct parent_map gcc_xo_sata_asic0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { P_SATA_ASIC0_CLK, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const char * const gcc_xo_sata_asic0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "sata_asic0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct parent_map gcc_xo_sata_rx_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { P_SATA_RX_CLK, 2}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char * const gcc_xo_sata_rx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "sata_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct parent_map gcc_xo_pcie_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { P_PCIE_0_1_PIPE_CLK, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const gcc_xo_pcie[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "pcie_pipe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct parent_map gcc_xo_pcie_sleep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { P_SLEEP_CLK, 6 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const char * const gcc_xo_pcie_sleep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct clk_pll gpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .l_reg = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .m_reg = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .n_reg = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .config_reg = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .mode_reg = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .status_reg = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "gpll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct clk_regmap gpll0_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .name = "gpll0_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .parent_names = (const char *[]){ "gpll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct clk_rcg2 config_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .cmd_rcgr = 0x0150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clk_rcg2 periph_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .cmd_rcgr = 0x0190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct clk_rcg2 system_noc_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .cmd_rcgr = 0x0120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct clk_pll gpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .l_reg = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .m_reg = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .n_reg = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .config_reg = 0x0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mode_reg = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .status_reg = 0x005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "gpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct clk_regmap gpll1_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .parent_names = (const char *[]){ "gpll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct clk_pll gpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .l_reg = 0x1dc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .m_reg = 0x1dc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .n_reg = 0x1dcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .config_reg = 0x1dd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .mode_reg = 0x1dc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .status_reg = 0x1ddc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .status_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "gpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .ops = &clk_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct clk_regmap gpll4_vote = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .enable_reg = 0x1480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "gpll4_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .parent_names = (const char *[]){ "gpll4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .ops = &clk_pll_vote_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) F(240000000, P_GPLL0, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct clk_rcg2 ufs_axi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .cmd_rcgr = 0x1d64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .freq_tbl = ftbl_gcc_ufs_axi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) F(125000000, P_GPLL0, 1, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct clk_rcg2 usb30_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .cmd_rcgr = 0x03d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .freq_tbl = ftbl_gcc_usb30_master_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) F(125000000, P_GPLL0, 1, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct clk_rcg2 usb30_sec_master_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .cmd_rcgr = 0x1bd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = "usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .halt_reg = 0x1bd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .enable_reg = 0x1bd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "gcc_usb30_sec_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "usb30_sec_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct clk_branch gcc_usb30_sec_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .halt_reg = 0x1bcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .enable_reg = 0x1bcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "gcc_usb30_sec_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .cmd_rcgr = 0x0660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .name = "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) F(960000, P_XO, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) F(4800000, P_XO, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) F(15000000, P_GPLL0, 10, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .cmd_rcgr = 0x064c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .name = "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .cmd_rcgr = 0x06e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .cmd_rcgr = 0x06cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .name = "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .cmd_rcgr = 0x0760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .cmd_rcgr = 0x074c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .cmd_rcgr = 0x07e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .name = "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .cmd_rcgr = 0x07cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .cmd_rcgr = 0x0860,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .name = "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .cmd_rcgr = 0x084c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .cmd_rcgr = 0x08e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .cmd_rcgr = 0x08cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .name = "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) F(3686400, P_GPLL0, 1, 96, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) F(7372800, P_GPLL0, 1, 192, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) F(14745600, P_GPLL0, 1, 384, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) F(16000000, P_GPLL0, 5, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) F(24000000, P_GPLL0, 5, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) F(32000000, P_GPLL0, 1, 4, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) F(40000000, P_GPLL0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) F(46400000, P_GPLL0, 1, 29, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) F(48000000, P_GPLL0, 12.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) F(51200000, P_GPLL0, 1, 32, 375),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) F(56000000, P_GPLL0, 1, 7, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) F(58982400, P_GPLL0, 1, 1536, 15625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) F(63160000, P_GPLL0, 9.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .cmd_rcgr = 0x068c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .name = "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .cmd_rcgr = 0x070c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .name = "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .cmd_rcgr = 0x078c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .name = "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .cmd_rcgr = 0x080c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .name = "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .cmd_rcgr = 0x088c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .name = "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .cmd_rcgr = 0x090c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .cmd_rcgr = 0x09a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .cmd_rcgr = 0x098c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .cmd_rcgr = 0x0a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .name = "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .cmd_rcgr = 0x0a0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .name = "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .cmd_rcgr = 0x0aa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .name = "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .cmd_rcgr = 0x0a8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .name = "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .cmd_rcgr = 0x0b20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .name = "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .cmd_rcgr = 0x0b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .name = "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .cmd_rcgr = 0x0ba0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .cmd_rcgr = 0x0b8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .cmd_rcgr = 0x0c20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .name = "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .cmd_rcgr = 0x0c0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .name = "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .cmd_rcgr = 0x09cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .cmd_rcgr = 0x0a4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .name = "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .cmd_rcgr = 0x0acc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .cmd_rcgr = 0x0b4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .name = "blsp2_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .cmd_rcgr = 0x0bcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .name = "blsp2_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .cmd_rcgr = 0x0c4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .name = "blsp2_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) F(85710000, P_GPLL0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) F(171430000, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static struct clk_rcg2 ce1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .cmd_rcgr = 0x1050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .freq_tbl = ftbl_gcc_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .name = "ce1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) F(85710000, P_GPLL0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) F(171430000, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct clk_rcg2 ce2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .cmd_rcgr = 0x1090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .freq_tbl = ftbl_gcc_ce2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "ce2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) F(85710000, P_GPLL0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) F(171430000, P_GPLL0, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct clk_rcg2 ce3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .cmd_rcgr = 0x1d10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .freq_tbl = ftbl_gcc_ce3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .name = "ce3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const struct freq_tbl ftbl_gcc_gp_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static struct clk_rcg2 gp1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .cmd_rcgr = 0x1904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .name = "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static struct clk_rcg2 gp2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .cmd_rcgr = 0x1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .name = "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static struct clk_rcg2 gp3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .cmd_rcgr = 0x1984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .freq_tbl = ftbl_gcc_gp_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) F(1010000, P_XO, 1, 1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static struct clk_rcg2 pcie_0_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .cmd_rcgr = 0x1b2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .parent_map = gcc_xo_pcie_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .name = "pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .parent_names = gcc_xo_pcie_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static struct clk_rcg2 pcie_1_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .cmd_rcgr = 0x1bac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .parent_map = gcc_xo_pcie_sleep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .name = "pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .parent_names = gcc_xo_pcie_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct clk_rcg2 pcie_0_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .cmd_rcgr = 0x1b18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .parent_map = gcc_xo_pcie_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .name = "pcie_0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .parent_names = gcc_xo_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static struct clk_rcg2 pcie_1_pipe_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .cmd_rcgr = 0x1b98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .parent_map = gcc_xo_pcie_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .name = "pcie_1_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .parent_names = gcc_xo_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static struct clk_rcg2 pdm2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .cmd_rcgr = 0x0cd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .freq_tbl = ftbl_gcc_pdm2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .name = "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static struct clk_rcg2 sata_asic0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .cmd_rcgr = 0x1c94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .parent_map = gcc_xo_sata_asic0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .freq_tbl = ftbl_gcc_sata_asic0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .name = "sata_asic0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .parent_names = gcc_xo_sata_asic0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) F(19200000, P_XO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static struct clk_rcg2 sata_pmalive_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .cmd_rcgr = 0x1c80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .freq_tbl = ftbl_gcc_sata_pmalive_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .name = "sata_pmalive_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) F(75000000, P_SATA_RX_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) F(150000000, P_SATA_RX_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) F(300000000, P_SATA_RX_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static struct clk_rcg2 sata_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .cmd_rcgr = 0x1ca8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .parent_map = gcc_xo_sata_rx_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .freq_tbl = ftbl_gcc_sata_rx_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .name = "sata_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .parent_names = gcc_xo_sata_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static struct clk_rcg2 sata_rx_oob_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .cmd_rcgr = 0x1c5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .name = "sata_rx_oob_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) F(144000, P_XO, 16, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) F(400000, P_XO, 12, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) F(20000000, P_GPLL0, 15, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) F(25000000, P_GPLL0, 12, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) F(50000000, P_GPLL0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) F(100000000, P_GPLL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) F(192000000, P_GPLL4, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) F(200000000, P_GPLL0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) F(384000000, P_GPLL4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static struct clk_rcg2 sdcc1_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .cmd_rcgr = 0x04d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .parent_map = gcc_xo_gpll0_gpll4_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .name = "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .parent_names = gcc_xo_gpll0_gpll4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .num_parents = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static struct clk_rcg2 sdcc2_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .cmd_rcgr = 0x0510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .name = "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static struct clk_rcg2 sdcc3_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .cmd_rcgr = 0x0550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .name = "sdcc3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static struct clk_rcg2 sdcc4_apps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .cmd_rcgr = 0x0590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .name = "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .ops = &clk_rcg2_floor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) F(105000, P_XO, 2, 1, 91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static struct clk_rcg2 tsif_ref_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .cmd_rcgr = 0x0d90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .freq_tbl = ftbl_gcc_tsif_ref_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .name = "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static struct clk_rcg2 usb30_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .cmd_rcgr = 0x03e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .name = "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) F(125000000, P_GPLL0, 1, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .cmd_rcgr = 0x1be8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .name = "usb30_sec_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static struct clk_rcg2 usb_hs_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .cmd_rcgr = 0x0490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .freq_tbl = ftbl_gcc_usb_hs_system_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .name = "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) F(480000000, P_GPLL1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const struct parent_map usb_hsic_clk_src_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) { P_XO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) { P_GPLL1, 4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static struct clk_rcg2 usb_hsic_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .cmd_rcgr = 0x0440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .parent_map = usb_hsic_clk_src_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .freq_tbl = ftbl_gcc_usb_hsic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .name = "usb_hsic_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) F(60000000, P_GPLL1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static struct clk_rcg2 usb_hsic_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .cmd_rcgr = 0x046c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .parent_map = usb_hsic_clk_src_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .name = "usb_hsic_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) "gpll1_vote",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) F(9600000, P_XO, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .cmd_rcgr = 0x0458,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .name = "usb_hsic_io_cal_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .halt_reg = 0x1f14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .enable_reg = 0x1f14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .name = "gcc_usb_hsic_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) "usb_hsic_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) F(60000000, P_GPLL0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .cmd_rcgr = 0x1f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .name = "usb_hsic_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) F(75000000, P_GPLL0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static struct clk_rcg2 usb_hsic_system_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .cmd_rcgr = 0x041c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .parent_map = gcc_xo_gpll0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .name = "usb_hsic_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .parent_names = gcc_xo_gpll0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static struct clk_branch gcc_bam_dma_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .halt_reg = 0x0d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .enable_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .name = "gcc_bam_dma_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static struct clk_branch gcc_blsp1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .halt_reg = 0x05c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .enable_mask = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .name = "gcc_blsp1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .halt_reg = 0x0648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .enable_reg = 0x0648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .name = "gcc_blsp1_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) "blsp1_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .halt_reg = 0x0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .enable_reg = 0x0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .name = "gcc_blsp1_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) "blsp1_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .halt_reg = 0x06c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .enable_reg = 0x06c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .name = "gcc_blsp1_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) "blsp1_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .halt_reg = 0x06c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .enable_reg = 0x06c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .name = "gcc_blsp1_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) "blsp1_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .halt_reg = 0x0748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .enable_reg = 0x0748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .name = "gcc_blsp1_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) "blsp1_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .halt_reg = 0x0744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .enable_reg = 0x0744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .name = "gcc_blsp1_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) "blsp1_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .halt_reg = 0x07c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .enable_reg = 0x07c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .name = "gcc_blsp1_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) "blsp1_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .halt_reg = 0x07c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .enable_reg = 0x07c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .name = "gcc_blsp1_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) "blsp1_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .halt_reg = 0x0848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .enable_reg = 0x0848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .name = "gcc_blsp1_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) "blsp1_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .halt_reg = 0x0844,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .enable_reg = 0x0844,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .name = "gcc_blsp1_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) "blsp1_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .halt_reg = 0x08c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .enable_reg = 0x08c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .name = "gcc_blsp1_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) "blsp1_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .halt_reg = 0x08c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .enable_reg = 0x08c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .name = "gcc_blsp1_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) "blsp1_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static struct clk_branch gcc_blsp1_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .halt_reg = 0x0684,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .enable_reg = 0x0684,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .name = "gcc_blsp1_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) "blsp1_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static struct clk_branch gcc_blsp1_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .halt_reg = 0x0704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .enable_reg = 0x0704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .name = "gcc_blsp1_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) "blsp1_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static struct clk_branch gcc_blsp1_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .halt_reg = 0x0784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .enable_reg = 0x0784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .name = "gcc_blsp1_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) "blsp1_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static struct clk_branch gcc_blsp1_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .halt_reg = 0x0804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .enable_reg = 0x0804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .name = "gcc_blsp1_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) "blsp1_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static struct clk_branch gcc_blsp1_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .halt_reg = 0x0884,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .enable_reg = 0x0884,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .name = "gcc_blsp1_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) "blsp1_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static struct clk_branch gcc_blsp1_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .halt_reg = 0x0904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .enable_reg = 0x0904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .name = "gcc_blsp1_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) "blsp1_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static struct clk_branch gcc_blsp2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .halt_reg = 0x0944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .enable_mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .name = "gcc_blsp2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .halt_reg = 0x0988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .enable_reg = 0x0988,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .name = "gcc_blsp2_qup1_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) "blsp2_qup1_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .halt_reg = 0x0984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .enable_reg = 0x0984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .name = "gcc_blsp2_qup1_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) "blsp2_qup1_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .halt_reg = 0x0a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .enable_reg = 0x0a08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .name = "gcc_blsp2_qup2_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) "blsp2_qup2_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .halt_reg = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .enable_reg = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .name = "gcc_blsp2_qup2_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) "blsp2_qup2_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .halt_reg = 0x0a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .enable_reg = 0x0a88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .name = "gcc_blsp2_qup3_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) "blsp2_qup3_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .halt_reg = 0x0a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .enable_reg = 0x0a84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .name = "gcc_blsp2_qup3_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) "blsp2_qup3_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .halt_reg = 0x0b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .enable_reg = 0x0b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .name = "gcc_blsp2_qup4_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) "blsp2_qup4_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .halt_reg = 0x0b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .enable_reg = 0x0b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .name = "gcc_blsp2_qup4_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) "blsp2_qup4_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .halt_reg = 0x0b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .enable_reg = 0x0b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .name = "gcc_blsp2_qup5_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) "blsp2_qup5_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .halt_reg = 0x0b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .enable_reg = 0x0b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .name = "gcc_blsp2_qup5_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) "blsp2_qup5_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .halt_reg = 0x0c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .enable_reg = 0x0c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .name = "gcc_blsp2_qup6_i2c_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) "blsp2_qup6_i2c_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .halt_reg = 0x0c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .enable_reg = 0x0c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .name = "gcc_blsp2_qup6_spi_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) "blsp2_qup6_spi_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct clk_branch gcc_blsp2_uart1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .halt_reg = 0x09c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .enable_reg = 0x09c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .name = "gcc_blsp2_uart1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) "blsp2_uart1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static struct clk_branch gcc_blsp2_uart2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .halt_reg = 0x0a44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .enable_reg = 0x0a44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .name = "gcc_blsp2_uart2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "blsp2_uart2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static struct clk_branch gcc_blsp2_uart3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .halt_reg = 0x0ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .enable_reg = 0x0ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .name = "gcc_blsp2_uart3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) "blsp2_uart3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static struct clk_branch gcc_blsp2_uart4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .halt_reg = 0x0b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .enable_reg = 0x0b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .name = "gcc_blsp2_uart4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) "blsp2_uart4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static struct clk_branch gcc_blsp2_uart5_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .halt_reg = 0x0bc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .enable_reg = 0x0bc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .name = "gcc_blsp2_uart5_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "blsp2_uart5_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static struct clk_branch gcc_blsp2_uart6_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .halt_reg = 0x0c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .enable_reg = 0x0c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .name = "gcc_blsp2_uart6_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) "blsp2_uart6_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static struct clk_branch gcc_boot_rom_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .halt_reg = 0x0e04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .enable_mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .name = "gcc_boot_rom_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static struct clk_branch gcc_ce1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .halt_reg = 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .enable_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .name = "gcc_ce1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) static struct clk_branch gcc_ce1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .halt_reg = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .enable_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .name = "gcc_ce1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static struct clk_branch gcc_ce1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .halt_reg = 0x1050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .enable_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .name = "gcc_ce1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) "ce1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) static struct clk_branch gcc_ce2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .halt_reg = 0x108c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .name = "gcc_ce2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) static struct clk_branch gcc_ce2_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .halt_reg = 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .enable_mask = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .name = "gcc_ce2_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static struct clk_branch gcc_ce2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .halt_reg = 0x1090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .enable_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .name = "gcc_ce2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) "ce2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) static struct clk_branch gcc_ce3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .halt_reg = 0x1d0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .enable_reg = 0x1d0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .name = "gcc_ce3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static struct clk_branch gcc_ce3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .halt_reg = 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .enable_reg = 0x1d08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .name = "gcc_ce3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) "system_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static struct clk_branch gcc_ce3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .halt_reg = 0x1090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .enable_reg = 0x1d04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .name = "gcc_ce3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) "ce3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static struct clk_branch gcc_gp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .halt_reg = 0x1900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .enable_reg = 0x1900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .name = "gcc_gp1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) "gp1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static struct clk_branch gcc_gp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .halt_reg = 0x1940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .enable_reg = 0x1940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .name = "gcc_gp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) "gp2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static struct clk_branch gcc_gp3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .halt_reg = 0x1980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .enable_reg = 0x1980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .name = "gcc_gp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) "gp3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .halt_reg = 0x0248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .enable_reg = 0x0248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .name = "gcc_ocmem_noc_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) static struct clk_branch gcc_pcie_0_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .halt_reg = 0x1b10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .enable_reg = 0x1b10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .name = "gcc_pcie_0_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) "pcie_0_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .halt_reg = 0x1b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .enable_reg = 0x1b0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .name = "gcc_pcie_0_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .halt_reg = 0x1b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .enable_reg = 0x1b08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .name = "gcc_pcie_0_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static struct clk_branch gcc_pcie_0_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .halt_reg = 0x1b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .enable_reg = 0x1b14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .name = "gcc_pcie_0_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) "pcie_0_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static struct clk_branch gcc_pcie_0_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .halt_reg = 0x1b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .enable_reg = 0x1b04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .name = "gcc_pcie_0_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) static struct clk_branch gcc_pcie_1_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .halt_reg = 0x1b90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .enable_reg = 0x1b90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .name = "gcc_pcie_1_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) "pcie_1_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .halt_reg = 0x1b8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .enable_reg = 0x1b8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .name = "gcc_pcie_1_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .halt_reg = 0x1b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .enable_reg = 0x1b88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .name = "gcc_pcie_1_mstr_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) static struct clk_branch gcc_pcie_1_pipe_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .halt_reg = 0x1b94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .enable_reg = 0x1b94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .name = "gcc_pcie_1_pipe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) "pcie_1_pipe_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static struct clk_branch gcc_pcie_1_slv_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .halt_reg = 0x1b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .enable_reg = 0x1b84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .name = "gcc_pcie_1_slv_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) static struct clk_branch gcc_pdm2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .halt_reg = 0x0ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .enable_reg = 0x0ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .name = "gcc_pdm2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) "pdm2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static struct clk_branch gcc_pdm_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .halt_reg = 0x0cc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .enable_reg = 0x0cc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .name = "gcc_pdm_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .halt_reg = 0x01a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .enable_reg = 0x01a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .name = "gcc_periph_noc_usb_hsic_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) "usb_hsic_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static struct clk_branch gcc_prng_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .halt_reg = 0x0d04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .halt_check = BRANCH_HALT_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .enable_reg = 0x1484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .enable_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .name = "gcc_prng_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static struct clk_branch gcc_sata_asic0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .halt_reg = 0x1c54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .enable_reg = 0x1c54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .name = "gcc_sata_asic0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) "sata_asic0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) static struct clk_branch gcc_sata_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .halt_reg = 0x1c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .enable_reg = 0x1c44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .name = "gcc_sata_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static struct clk_branch gcc_sata_cfg_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .halt_reg = 0x1c48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .enable_reg = 0x1c48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .name = "gcc_sata_cfg_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) static struct clk_branch gcc_sata_pmalive_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .halt_reg = 0x1c50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .enable_reg = 0x1c50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .name = "gcc_sata_pmalive_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) "sata_pmalive_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) static struct clk_branch gcc_sata_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .halt_reg = 0x1c58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .enable_reg = 0x1c58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .name = "gcc_sata_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) "sata_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) static struct clk_branch gcc_sata_rx_oob_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .halt_reg = 0x1c4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .enable_reg = 0x1c4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .name = "gcc_sata_rx_oob_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) "sata_rx_oob_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) static struct clk_branch gcc_sdcc1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .halt_reg = 0x04c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .enable_reg = 0x04c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .name = "gcc_sdcc1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static struct clk_branch gcc_sdcc1_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .halt_reg = 0x04c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .enable_reg = 0x04c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .name = "gcc_sdcc1_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) "sdcc1_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .halt_reg = 0x04e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .enable_reg = 0x04e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .name = "gcc_sdcc1_cdccal_ff_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) "xo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .halt_reg = 0x04e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .enable_reg = 0x04e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .name = "gcc_sdcc1_cdccal_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) "sleep_clk_src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static struct clk_branch gcc_sdcc2_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .halt_reg = 0x0508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .enable_reg = 0x0508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .name = "gcc_sdcc2_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) static struct clk_branch gcc_sdcc2_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .halt_reg = 0x0504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .enable_reg = 0x0504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .name = "gcc_sdcc2_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) "sdcc2_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static struct clk_branch gcc_sdcc3_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .halt_reg = 0x0548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .enable_reg = 0x0548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .name = "gcc_sdcc3_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) static struct clk_branch gcc_sdcc3_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .halt_reg = 0x0544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .enable_reg = 0x0544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .name = "gcc_sdcc3_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) "sdcc3_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static struct clk_branch gcc_sdcc4_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .halt_reg = 0x0588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .enable_reg = 0x0588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .name = "gcc_sdcc4_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) static struct clk_branch gcc_sdcc4_apps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .halt_reg = 0x0584,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .enable_reg = 0x0584,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .name = "gcc_sdcc4_apps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) "sdcc4_apps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .halt_reg = 0x013c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .enable_reg = 0x013c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .name = "gcc_sys_noc_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .halt_reg = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .enable_reg = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .name = "gcc_sys_noc_usb3_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .halt_reg = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .enable_reg = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .name = "gcc_sys_noc_usb3_sec_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) "usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static struct clk_branch gcc_tsif_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .halt_reg = 0x0d84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .enable_reg = 0x0d84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .name = "gcc_tsif_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) static struct clk_branch gcc_tsif_inactivity_timers_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .halt_reg = 0x0d8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .enable_reg = 0x0d8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .name = "gcc_tsif_inactivity_timers_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static struct clk_branch gcc_tsif_ref_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .halt_reg = 0x0d88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .enable_reg = 0x0d88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .name = "gcc_tsif_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) "tsif_ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) static struct clk_branch gcc_ufs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .halt_reg = 0x1d48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .enable_reg = 0x1d48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .name = "gcc_ufs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) "config_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) static struct clk_branch gcc_ufs_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .halt_reg = 0x1d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .enable_reg = 0x1d44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .name = "gcc_ufs_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) static struct clk_branch gcc_ufs_rx_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) .halt_reg = 0x1d50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .enable_reg = 0x1d50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .name = "gcc_ufs_rx_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .halt_reg = 0x1d5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .enable_reg = 0x1d5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .name = "gcc_ufs_rx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) "ufs_rx_symbol_0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .halt_reg = 0x1d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .enable_reg = 0x1d60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .name = "gcc_ufs_rx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) "ufs_rx_symbol_1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static struct clk_branch gcc_ufs_tx_cfg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .halt_reg = 0x1d4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .enable_reg = 0x1d4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .name = "gcc_ufs_tx_cfg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) "ufs_axi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .halt_reg = 0x1d54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .enable_reg = 0x1d54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .name = "gcc_ufs_tx_symbol_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) "ufs_tx_symbol_0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) .halt_reg = 0x1d58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .enable_reg = 0x1d58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .name = "gcc_ufs_tx_symbol_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) "ufs_tx_symbol_1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static struct clk_branch gcc_usb2a_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .halt_reg = 0x04ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .enable_reg = 0x04ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .name = "gcc_usb2a_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) static struct clk_branch gcc_usb2b_phy_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .halt_reg = 0x04b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .enable_reg = 0x04b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .name = "gcc_usb2b_phy_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) static struct clk_branch gcc_usb30_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .halt_reg = 0x03c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) .enable_reg = 0x03c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .name = "gcc_usb30_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) "usb30_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) static struct clk_branch gcc_usb30_sec_master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) .halt_reg = 0x1bc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) .enable_reg = 0x1bc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .name = "gcc_usb30_sec_master_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) "usb30_sec_master_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) static struct clk_branch gcc_usb30_mock_utmi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) .halt_reg = 0x03d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) .enable_reg = 0x03d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .name = "gcc_usb30_mock_utmi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) "usb30_mock_utmi_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) static struct clk_branch gcc_usb30_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) .halt_reg = 0x03cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .enable_reg = 0x03cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .name = "gcc_usb30_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) static struct clk_branch gcc_usb_hs_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) .halt_reg = 0x0488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .enable_reg = 0x0488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .name = "gcc_usb_hs_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) .halt_reg = 0x048c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) .enable_reg = 0x048c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) .name = "gcc_usb_hs_inactivity_timers_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) static struct clk_branch gcc_usb_hs_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) .halt_reg = 0x0484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) .enable_reg = 0x0484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) .name = "gcc_usb_hs_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) "usb_hs_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) static struct clk_branch gcc_usb_hsic_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) .halt_reg = 0x0408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) .enable_reg = 0x0408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .name = "gcc_usb_hsic_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) "periph_noc_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) static struct clk_branch gcc_usb_hsic_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) .halt_reg = 0x0410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) .enable_reg = 0x0410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) .name = "gcc_usb_hsic_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) "usb_hsic_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) static struct clk_branch gcc_usb_hsic_io_cal_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .halt_reg = 0x0414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) .enable_reg = 0x0414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) .name = "gcc_usb_hsic_io_cal_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) "usb_hsic_io_cal_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .halt_reg = 0x0418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .enable_reg = 0x0418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) .name = "gcc_usb_hsic_io_cal_sleep_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) static struct clk_branch gcc_usb_hsic_system_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) .halt_reg = 0x040c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) .enable_reg = 0x040c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) .name = "gcc_usb_hsic_system_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) "usb_hsic_system_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) static struct gdsc usb_hs_hsic_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .gdscr = 0x404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) .name = "usb_hs_hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) static struct gdsc pcie0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) .gdscr = 0x1ac4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) .name = "pcie0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) static struct gdsc pcie1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) .gdscr = 0x1b44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .name = "pcie1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) static struct gdsc usb30_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) .gdscr = 0x1e84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .name = "usb30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) static struct clk_regmap *gcc_apq8084_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) [GPLL0] = &gpll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) [GPLL0_VOTE] = &gpll0_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) [GPLL1] = &gpll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) [GPLL1_VOTE] = &gpll1_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) [GPLL4] = &gpll4.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) [GPLL4_VOTE] = &gpll4_vote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [CE1_CLK_SRC] = &ce1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [CE2_CLK_SRC] = &ce2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) [CE3_CLK_SRC] = &ce3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [GP1_CLK_SRC] = &gp1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [GP2_CLK_SRC] = &gp2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [GP3_CLK_SRC] = &gp3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) static struct gdsc *gcc_apq8084_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) [PCIE0_GDSC] = &pcie0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) [PCIE1_GDSC] = &pcie1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) [USB30_GDSC] = &usb30_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) static const struct qcom_reset_map gcc_apq8084_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) [GCC_CONFIG_NOC_BCR] = { 0x0140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) [GCC_PERIPH_NOC_BCR] = { 0x0180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) [GCC_IMEM_BCR] = { 0x0200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) [GCC_MMSS_BCR] = { 0x0240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) [GCC_QDSS_BCR] = { 0x0300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) [GCC_USB_30_BCR] = { 0x03c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) [GCC_USB3_PHY_BCR] = { 0x03fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) [GCC_USB_HS_BCR] = { 0x0480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) [GCC_USB2A_PHY_BCR] = { 0x04a8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) [GCC_USB2B_PHY_BCR] = { 0x04b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) [GCC_SDCC1_BCR] = { 0x04c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) [GCC_SDCC2_BCR] = { 0x0500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) [GCC_SDCC3_BCR] = { 0x0540 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) [GCC_SDCC4_BCR] = { 0x0580 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) [GCC_BLSP1_BCR] = { 0x05c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) [GCC_BLSP1_UART1_BCR] = { 0x0680 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) [GCC_BLSP1_UART2_BCR] = { 0x0700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) [GCC_BLSP1_UART3_BCR] = { 0x0780 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) [GCC_BLSP1_UART4_BCR] = { 0x0800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) [GCC_BLSP1_UART5_BCR] = { 0x0880 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) [GCC_BLSP1_UART6_BCR] = { 0x0900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) [GCC_BLSP2_BCR] = { 0x0940 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) [GCC_PDM_BCR] = { 0x0cc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) [GCC_PRNG_BCR] = { 0x0d00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) [GCC_BAM_DMA_BCR] = { 0x0d40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) [GCC_TSIF_BCR] = { 0x0d80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) [GCC_TCSR_BCR] = { 0x0dc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) [GCC_BOOT_ROM_BCR] = { 0x0e00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) [GCC_MSG_RAM_BCR] = { 0x0e40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) [GCC_TLMM_BCR] = { 0x0e80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) [GCC_MPM_BCR] = { 0x0ec0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) [GCC_SEC_CTRL_BCR] = { 0x0f40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) [GCC_SPMI_BCR] = { 0x0fc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) [GCC_SPDM_BCR] = { 0x1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) [GCC_CE1_BCR] = { 0x1040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) [GCC_CE2_BCR] = { 0x1080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) [GCC_BIMC_BCR] = { 0x1100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) [GCC_DEHR_BCR] = { 0x1300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) [GCC_RBCPR_BCR] = { 0x1380 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) [GCC_MSS_RESTART] = { 0x1680 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) [GCC_LPASS_RESTART] = { 0x16c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) [GCC_WCSS_RESTART] = { 0x1700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) [GCC_VENUS_RESTART] = { 0x1740 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) [GCC_SPSS_BCR] = { 0x1a80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) [GCC_PCIE_0_BCR] = { 0x1ac0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) [GCC_PCIE_1_BCR] = { 0x1b40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) [GCC_SATA_BCR] = { 0x1c40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) [GCC_CE3_BCR] = { 0x1d00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) [GCC_UFS_BCR] = { 0x1d40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) static const struct regmap_config gcc_apq8084_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) .max_register = 0x1fc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) static const struct qcom_cc_desc gcc_apq8084_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) .config = &gcc_apq8084_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) .clks = gcc_apq8084_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) .resets = gcc_apq8084_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) .gdscs = gcc_apq8084_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) static const struct of_device_id gcc_apq8084_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) { .compatible = "qcom,gcc-apq8084" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) static int gcc_apq8084_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) ret = qcom_cc_register_sleep_clk(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) return qcom_cc_probe(pdev, &gcc_apq8084_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) static struct platform_driver gcc_apq8084_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) .probe = gcc_apq8084_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) .name = "gcc-apq8084",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) .of_match_table = gcc_apq8084_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) static int __init gcc_apq8084_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) return platform_driver_register(&gcc_apq8084_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) core_initcall(gcc_apq8084_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) static void __exit gcc_apq8084_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) platform_driver_unregister(&gcc_apq8084_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) module_exit(gcc_apq8084_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) MODULE_ALIAS("platform:gcc-apq8084");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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