^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) P_CHIP_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_DISP_CC_PLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_DISP_CC_PLL1_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_DISP_CC_PLL1_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_DP_PHY_PLL_LINK_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_DP_PHY_PLL_VCO_DIV_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_DPTX1_PHY_PLL_LINK_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_DPTX1_PHY_PLL_VCO_DIV_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_DPTX2_PHY_PLL_LINK_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_DPTX2_PHY_PLL_VCO_DIV_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) P_DSI0_PHY_PLL_OUT_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) P_DSI0_PHY_PLL_OUT_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) P_DSI1_PHY_PLL_OUT_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) P_DSI1_PHY_PLL_OUT_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P_EDP_PHY_PLL_LINK_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) P_EDP_PHY_PLL_VCO_DIV_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct pll_vco vco_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 249600000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct alpha_pll_config disp_cc_pll0_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .l = 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .alpha = 0xE000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .config_ctl_val = 0x20485699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .config_ctl_hi_val = 0x00002261,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .config_ctl_hi1_val = 0x329A699C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .user_ctl_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .user_ctl_hi_val = 0x00000805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .user_ctl_hi1_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct clk_init_data disp_cc_pll0_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "disp_cc_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .ops = &clk_alpha_pll_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct clk_alpha_pll disp_cc_pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .vco_table = vco_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .num_vco = ARRAY_SIZE(vco_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .clkr.hw.init = &disp_cc_pll0_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct alpha_pll_config disp_cc_pll1_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .l = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .alpha = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .config_ctl_val = 0x20485699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .config_ctl_hi_val = 0x00002261,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .config_ctl_hi1_val = 0x329A699C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .user_ctl_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .user_ctl_hi_val = 0x00000805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .user_ctl_hi1_val = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct clk_init_data disp_cc_pll1_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "disp_cc_pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .ops = &clk_alpha_pll_lucid_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct clk_alpha_pll disp_cc_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .vco_table = vco_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .num_vco = ARRAY_SIZE(vco_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .clkr.hw.init = &disp_cc_pll1_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct parent_map disp_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { P_DP_PHY_PLL_LINK_CLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct clk_parent_data disp_cc_parent_data_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .fw_name = "dp_phy_pll_link_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .fw_name = "dp_phy_pll_vco_div_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct parent_map disp_cc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct clk_parent_data disp_cc_parent_data_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct parent_map disp_cc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct clk_parent_data disp_cc_parent_data_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .fw_name = "dsi0_phy_pll_out_byteclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .fw_name = "dsi1_phy_pll_out_byteclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct parent_map disp_cc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { P_DISP_CC_PLL1_OUT_MAIN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct clk_parent_data disp_cc_parent_data_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .hw = &disp_cc_pll1.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct parent_map disp_cc_parent_map_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { P_DISP_CC_PLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { P_DISP_CC_PLL1_OUT_MAIN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct clk_parent_data disp_cc_parent_data_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .hw = &disp_cc_pll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .hw = &disp_cc_pll1.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct parent_map disp_cc_parent_map_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct clk_parent_data disp_cc_parent_data_6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .fw_name = "dsi0_phy_pll_out_dsiclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .fw_name = "dsi1_phy_pll_out_dsiclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .cmd_rcgr = 0x22bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .parent_map = disp_cc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "disp_cc_mdss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .parent_data = disp_cc_parent_data_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .cmd_rcgr = 0x2110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "disp_cc_mdss_byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .parent_data = disp_cc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .cmd_rcgr = 0x212c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "disp_cc_mdss_byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .parent_data = disp_cc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .cmd_rcgr = 0x2240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "disp_cc_mdss_dp_aux1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .parent_data = disp_cc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .cmd_rcgr = 0x21dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .name = "disp_cc_mdss_dp_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .parent_data = disp_cc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .cmd_rcgr = 0x220c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "disp_cc_mdss_dp_link1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .parent_data = disp_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .cmd_rcgr = 0x2178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "disp_cc_mdss_dp_link_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .parent_data = disp_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .cmd_rcgr = 0x21c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "disp_cc_mdss_dp_pixel1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .parent_data = disp_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .ops = &clk_dp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .cmd_rcgr = 0x21f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .name = "disp_cc_mdss_dp_pixel2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .parent_data = disp_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .ops = &clk_dp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .cmd_rcgr = 0x21ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .name = "disp_cc_mdss_dp_pixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .parent_data = disp_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .ops = &clk_dp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .cmd_rcgr = 0x2148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .name = "disp_cc_mdss_esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .parent_data = disp_cc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .cmd_rcgr = 0x2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .name = "disp_cc_mdss_esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .parent_data = disp_cc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .cmd_rcgr = 0x20c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .parent_map = disp_cc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = "disp_cc_mdss_mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .parent_data = disp_cc_parent_data_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .cmd_rcgr = 0x2098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .parent_map = disp_cc_parent_map_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .name = "disp_cc_mdss_pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .parent_data = disp_cc_parent_data_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .cmd_rcgr = 0x20b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .parent_map = disp_cc_parent_map_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "disp_cc_mdss_pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .parent_data = disp_cc_parent_data_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .cmd_rcgr = 0x20e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .parent_map = disp_cc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "disp_cc_mdss_rot_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .parent_data = disp_cc_parent_data_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .cmd_rcgr = 0x20f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .name = "disp_cc_mdss_vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .parent_data = disp_cc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .reg = 0x2128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .name = "disp_cc_mdss_byte0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .reg = 0x2144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .name = "disp_cc_mdss_byte1_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .reg = 0x2224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .name = "disp_cc_mdss_dp_link1_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .hw = &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .reg = 0x2190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = "disp_cc_mdss_dp_link_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .ops = &clk_regmap_div_ro_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct clk_branch disp_cc_mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .halt_reg = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .enable_reg = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "disp_cc_mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct clk_branch disp_cc_mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .halt_reg = 0x2028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .enable_reg = 0x2028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .name = "disp_cc_mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .halt_reg = 0x202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .enable_reg = 0x202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .name = "disp_cc_mdss_byte0_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static struct clk_branch disp_cc_mdss_byte1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .halt_reg = 0x2030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .enable_reg = 0x2030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .name = "disp_cc_mdss_byte1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .halt_reg = 0x2034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .enable_reg = 0x2034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "disp_cc_mdss_byte1_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .hw = &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .halt_reg = 0x2068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .enable_reg = 0x2068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .name = "disp_cc_mdss_dp_aux1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .hw = &disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct clk_branch disp_cc_mdss_dp_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .halt_reg = 0x2054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .enable_reg = 0x2054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .name = "disp_cc_mdss_dp_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct clk_branch disp_cc_mdss_dp_link1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .halt_reg = 0x205c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .enable_reg = 0x205c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .name = "disp_cc_mdss_dp_link1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .hw = &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .halt_reg = 0x2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .enable_reg = 0x2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .name = "disp_cc_mdss_dp_link1_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .hw = &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static struct clk_branch disp_cc_mdss_dp_link_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .halt_reg = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .enable_reg = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .name = "disp_cc_mdss_dp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .halt_reg = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .enable_reg = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .name = "disp_cc_mdss_dp_link_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .halt_reg = 0x2050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .enable_reg = 0x2050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .name = "disp_cc_mdss_dp_pixel1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .hw = &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .halt_reg = 0x2058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .enable_reg = 0x2058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .name = "disp_cc_mdss_dp_pixel2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .hw = &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .halt_reg = 0x204c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .enable_reg = 0x204c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .name = "disp_cc_mdss_dp_pixel_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static struct clk_branch disp_cc_mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .halt_reg = 0x2038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .enable_reg = 0x2038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .name = "disp_cc_mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static struct clk_branch disp_cc_mdss_esc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .halt_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .enable_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .name = "disp_cc_mdss_esc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .hw = &disp_cc_mdss_esc1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static struct clk_branch disp_cc_mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .halt_reg = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .enable_reg = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .name = "disp_cc_mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .halt_reg = 0x201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .enable_reg = 0x201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .name = "disp_cc_mdss_mdp_lut_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .halt_reg = 0x4004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .enable_reg = 0x4004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .name = "disp_cc_mdss_non_gdsc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static struct clk_branch disp_cc_mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .halt_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .enable_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .name = "disp_cc_mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static struct clk_branch disp_cc_mdss_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .halt_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .enable_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .name = "disp_cc_mdss_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .hw = &disp_cc_mdss_pclk1_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static struct clk_branch disp_cc_mdss_rot_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .halt_reg = 0x2014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .enable_reg = 0x2014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .name = "disp_cc_mdss_rot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .halt_reg = 0x400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .enable_reg = 0x400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .name = "disp_cc_mdss_rscc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .halt_reg = 0x4008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .enable_reg = 0x4008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .name = "disp_cc_mdss_rscc_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct clk_branch disp_cc_mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .halt_reg = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .enable_reg = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .name = "disp_cc_mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .gdscr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .name = "mdss_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static struct clk_regmap *disp_cc_sm8250_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static struct gdsc *disp_cc_sm8250_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const struct regmap_config disp_cc_sm8250_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .max_register = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const struct qcom_cc_desc disp_cc_sm8250_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .config = &disp_cc_sm8250_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .clks = disp_cc_sm8250_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .resets = disp_cc_sm8250_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .gdscs = disp_cc_sm8250_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const struct of_device_id disp_cc_sm8250_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { .compatible = "qcom,sm8150-dispcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { .compatible = "qcom,sm8250-dispcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int disp_cc_sm8250_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* note: trion == lucid, except for the prepare() op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Enable clock gating for MDP clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* DISP_CC_XO_CLK always-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static struct platform_driver disp_cc_sm8250_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .probe = disp_cc_sm8250_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .name = "disp_cc-sm8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .of_match_table = disp_cc_sm8250_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int __init disp_cc_sm8250_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return platform_driver_register(&disp_cc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) subsys_initcall(disp_cc_sm8250_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static void __exit disp_cc_sm8250_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) platform_driver_unregister(&disp_cc_sm8250_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) module_exit(disp_cc_sm8250_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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